Atomic layer deposition of sub-10 nm high-K gate dielectrics on top-gated MoS2 transistors without surface functionalization

Accepted Manuscript Full Length Article Atomic layer deposition of sub-10nm high-K gate dielectrics on top-gated MoS2 transistors without surface functionalization Yu-Shu Lin, Po-hsien Cheng, Kuei-Wen Huang, Hsin-Chih Lin, Miin-Jang Chen PII: DOI: Reference:

S0169-4332(18)30587-7 https://doi.org/10.1016/j.apsusc.2018.02.225 APSUSC 38683

To appear in:

Applied Surface Science

Received Date: Revised Date: Accepted Date:

15 September 2017 21 February 2018 22 February 2018

Please cite this article as: Y-S. Lin, P-h. Cheng, K-W. Huang, H-C. Lin, M-J. Chen, Atomic layer deposition of sub-10nm high-K gate dielectrics on top-gated MoS2 transistors without surface functionalization, Applied Surface Science (2018), doi: https://doi.org/10.1016/j.apsusc.2018.02.225

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Atomic layer deposition of sub-10nm high-K gate dielectrics on top-gated MoS2 transistors without surface functionalization Yu-Shu Lin, Po-hsien Cheng, Kuei-Wen Huang, Hsin-Chih Lin, and Miin-Jang Chen* Department of Materials Science and Engineering, National Taiwan University, Taipei 10617, Taiwan * Corresponding author: [email protected]

Abstract Sub-10 nm high-K gate dielectrics are of critical importance in two-dimensional transition metal dichalcogenides (TMDs) transistors. However, the chemical inertness of TMDs gives rise to a lot of pinholes in gate dielectrics, resulting in large gate leakage current. In this study, sub-10nm, uniform and pinhole-free Al2O3 high-K gate dielectrics on MoS2 were achieved by atomic layer deposition without surface functionalization, in which an ultrathin Al2O3 layer prepared with a short purge time at a low temperature of 80°C offers the nucleation cites for the deposition of the overlaying oxide at a higher temperature. Conductive atomic force microscopy reveals the significant suppression of gate leakage current in the sub-10 nm Al2O3 gate dielectrics with the low-temperature nucleation layer. Raman and X-ray photoelectron spectroscopies indicate that no oxidation occurred during the deposition of the low-temperature Al2O3 nucleation layer on MoS2. With the high-quality sub-10nm Al2O3 high-K gate dielectrics, low hysteresis and subthreshold swing were demonstrated on the normally-off top-gated MoS2 transistors.

Keywords: MoS2, two-dimensional materials, field-effect transistors, atomic layer deposition (ALD), high-K gate dielectrics.

Introduction Transition metal dichalcogenides (TMDs) are a family of two dimensional layered materials similar to graphene. MoS2, which is one of the most prevalent TMDs, has been recognized as a promising candidate for channel materials when the scaling of Si field-effect transistors reaches the physical limit [1-5]. In contrast to graphene of zero bandgap, monolayer and bulk MoS2 are semiconductors of direct bandgap (1.8 eV) and indirect bandgap (1.29 eV), respectively [6, 7]. In addition, TMDs transistors are immune to the severe short-channel effects due to its ultrathin feature [8]. These characteristics are highly beneficial to the applications of TMDs on logic devices in the future. It is well known that the interfacial quality between the gate oxide and the channel is critical for the performance of electronic devices. However, the lack of dangling bonds on the surface of TMDs results in the difficulty of preparing high-quality high-K gate dielectrics by atomic layer deposition (ALD), and the island-like oxide clusters were generally formed on pristine MoS2 flakes [9, 10]. The island-like features of high-K oxides on MoS2 give rise to large gate leakage current, resulting in the need of a thick gate oxide (usually greater than 10 nm) on top-gated MoS2 transistors in the previous reports [1, 8, 11-17]. In order to further improve the gate control of the channel, the thickness of high-K gate dielectrics should be below 10 nm to increase the gate capacitance. Therefore, the realization of high-quality, uniform, continuous, and pinhole-free high-K gate dielectrics with a thickness below 10 nm on TMDs is important for continuous scaling down of TMDs transistors. In order to overcome the difficulty caused by chemical inertness of TMDs, a lot of research has reported on the surface functionalization of MoS2 [18]-[19]. Different from the approaches based on the functionalization of MoS2 surface, sub-10nm, uniform, and pinhole-free Al2O3 high-K gate dielectrics were realized without the surface functionalization in this paper. In the ALD process, precursors are adsorbed on

the substrate surface via the physical or chemical adsorption mechanism. Owing to the absence of dangling bonds, chemical adsorption is rarely observed on pristine MoS2 flakes. In this study, an ultrathin Al2O3 nucleation layer (NL) was prepared by ALD at a low temperature via physical adsorption. Based on the short purge times between the two precursor pulses along with a low deposition temperature below 100°C, the excess physisorbed precursors have insufficient time to desorb from the substrate, resulting in chemical vapor deposition (CVD) of Al2O3. This ultrathin Al2O3 layer which provides nucleation cites for the deposition of the overlaying high-K layer at a higher temperature. Thus the low-temperature physical adsorption was intentionally employed to prepare the NL to achieve sub-10nm, uniform, and pinhole-free Al2O3 ALD growth on MoS2. In addition, the top-gated MoS2 field-effect transistors integrated with the sub-10nm, pinhole-free Al2O3 high-K gate dielectrics were fabricated, which exhibited the normally-off operation, low hysteresis and subthreshold swing minimum (88 mV/dec). The result demonstrates the high quality of the sub-10nm ALD high-K gate dielectrics prepared with the low-temperature NL via physical adsorption.

Experimental Preparation of Multilayer MoS2 flakes Multilayer MoS2 flakes were obtained from a single crystal of 2H-MoS2 (SPI, natural molybdenite) using the conventional tape-based mechanical exfoliation technique with the Nitto tape. Then the exfoliated MoS2 flakes were transferred onto a 300 nm SiO2 layer grown thermally on a p-type Si (100) wafer. The thickness of MoS2 flakes was determined by the atomic force microscopy (AFM, Bruker Dimension Icon). Atomic layer deposition of Al2O3 on MoS2 flakes The samples were loaded into the ALD reactor (Ultratech savannah ALD system). The reaction

chamber was pumped down to 1 mTorr. Trimethylaluminum (TMA) and H2O vapor were used as the precursor and reactant for aluminum and oxygen, respectively. For the deposition of the Al2O3 NL based on the low-temperature physical adsorption, the ALD were conducted at 80°C and each ALD cycle consisted of a sequence of TMA pulse → N2 purge (5sec) → H2O pulse → N2 purge (5sec). Afterwards, an Al2O3 main layer was deposited upon the NL at a higher temperature of 180°C with the same sequence of TMA pulse → N2 purge (15sec) → H2O pulse → N2 purge (15sec) in each ALD cycle,. Note that the N2 purge time is longer (15 sec) in the ALD cycle for the deposition of the Al2O3 main layer. The layer structure of the Al2O3 gate oxide is shown in Figure 1 (a). The correlation between the ALD conditions and the Al2O3 surface morphology was examined by the tapping-mode AFM measurement (AFM, Bruker Dimension Icon). The conductive atomic force microscopy (CAFM, Bruker D3100) using metal (PtIr5) coated Si tips was used to characterize the current mapping of the Al2O3 gate oxide with nanoscale resolution. The thickness of Al2O3 gate oxides was checked by the tapping-mode AFM and the spectroscopic ellipsometer (SE, Elli-SE-U). The MoS2 flakes with and without the deposition of the low-temperature Al2O3 NL were probed by the Raman spectroscopy (UniDRON, Uninanotech Co., Ltd.) excited by a diode-pumped solid-state laser at a wavelength of 532 nm. The X-ray photoelectron spectroscopy (XPS) was exploited to characterize the binding energy of MoS2 flakes. The XPS measurement was carried out by using an Al Kα X-ray source (1486.6 eV) with a spot size of 400 µm in diameter. Fabrication of MoS2 transistors Figure 1 (b) plots the schematic structure of the top-gated MoS2 transistors. The source and drain contacts were prepared by thermal evaporation of 15 nm Cr and 75 nm Au. A Pt layer was sputtered upon

the Al2O3 gate dielectrics as the gate metal with a gate length of 3 µm. All the patterns were defined by optical lithography. The electrical characteristics of the top-gated MoS2 transistors were characterized at room temperature in air by using the Keysight B1500A semiconductor device parameter analyzer.

Results and discussion Figure 2 shows the AFM images of the Al2O3 NL prepared with 10 and 50 cycles of ALD on MoS2 at a low temperatures of 80°C with a short N2 purge time of 5 s, revealing the absence of pinholes on the Al2O3 NL. As compared with the similar low-temperature ALD process for the preparation of the Al2O3 NL on graphene terraces as reported by Kwak et.al. [20], the deposition of the Al2O3 NL on MoS2 via low-temperature physical adsorption as shown in Figure 2 is much more uniform than that on graphene terraces. The result might be attributed to the difference between the TMA adsorption energy on MoS2 and graphene. It has been indicated by the Lennard-Jones potential model that the adsorption potential energy of TMA on MoS2 is much greater than that on graphene [21]. A higher adsorption potential energy of TMA on MoS2 is associated with a deeper adsorption potential well. The thermal energy of precursor molecules is small at lower temperatures, so that the precursors are prone to be trapped in the deeper adsorption potential well even with the nitrogen purge [21]. Hence the low-temperature physical adsorption facilitates more uniform growth of the Al2O3 NL on MoS2 than that on graphene. Figure 3 (a) and (b) show the AFM topography of the Al2O3 main layer prepared with 50 and 100 ALD cycles, respectively, upon the 10-cycle Al2O3 NL. It is observed that a continuous, uniform surface and a pinhole-free structure of the Al2O3 main layer prepared upon the low-temperature NL. As a comparison, the surface morphology of the Al2O3 main layer is not continuous and comprises a lot of the pinhole-like

structures if the low-temperature NL was not introduced between the Al2O3 main layer and MoS2, as shown in Figure 3 (c) and (d), where the Al2O3 main layer was directly deposited upon MoS2 at a higher deposition of 180°C. As compared with Figure 3 (b), the Al2O3 main layer also becomes non-uniform and small pinholes appear in Figure 3 (e) if the deposition temperature of the Al2O3 NL increases from 80°C to 180°C. Physical adsorption is the dominant adsorption mechanism of precursors on the pristine TMDs surface because the TMDs are chemically inert due to the lack of dangling bonds [19, 21, 22]. Since the thermal energy of precursor molecules is small at low deposition temperatures, the precursors are prone to be trapped in the potential well of physical adsorption [19, 21-24]. At high deposition temperatures, the thermal energy of precursors may be greater than the depth of the potential well. Hence the precursors might escape from the adsorption potential well, resulting in the undoing of the film deposition [10, 19, 21, 23, 24]. Accordingly, the escape of precursors from the adsorption potential well at a higher deposition temperature may be responsible for the change of the surface morphology from Figure 3 (b) to 3 (e). As the deposition temperature of the Al2O3 NL increases from 80°C to 180°C, the reduced physical adsorption due to the precursor escape results in the rougher surface of Al2O3 [10, 19, 21, 23]. Note that a short N2 purge time (5 sec) was used in the deposition process of the Al2O3 NL in Figure 3 (e). The long N2 purge time (15 sec) used in the Al2O3 deposition leads to a much more rough surface (Figure 3 (d)) than that with a short N2 purge time (Figure 3 (e)). In a comparison between Figure 3 (d) and 3 (e), the surface roughness was significantly reduced (3.53 nm vs. 0.78 nm) when the Al2O3 NL prepared with a short N2 purge time was introduced between the Al2O3 main layer and MoS2. With a short N2 purge time, the precursor and the reactant might remain in the vicinity of the surface due to the incomplete purge of precursors and reactants, which induces the CVD growth mode [21, 25, 26]. Therefore, the Al2O3 NL provides more nucleation sites

to facilitate uniform growth of the Al2O3 main layer. As a result, the surface roughness of Al2O3 decreases with the introduction of the Al2O3 NL prepared with a short N2 purge time. All the results shown in Figure 3 indicate the significance of the low-temperature physical adsorption for the preparation of the uniform Al2O3 NL. The schematic diagram of the CAFM measurement is shown in Figure 4 (a), in which the PtIr5 coated AFM tip is scanned cross the Al2O3 surface using the contact mode, with a DC bias applied to the Si substrate. The electrical uniformity of the Al2O3 gate oxide deposited on MoS2 was examined in terms of the mapping of leakage current (Figure 4 (b), (c), and (d)) along with the surface morphology (Figure 4 (b’), (c’), and (d’)), and the corresponding layer structure/process conditions of the Al2O3 gate oxide is shown in Figure 4 (b’’), (c’’), and (d’’), respectively. As predicted, a large leakage current was observed in Figure 4 (b), which is ascribed to the pinhole-like structure as shown in Figure 4 (b’) in the Al2O3 gate oxide without the low-temperature NL. With the insertion of the 10-cycle low-temperature NL between the Al2O3 main layer and MoS2, the leakage current is significantly reduced and the surface becomes more smooth and uniform as shown in Figure 4 (c) and (c’). Note that the leakage current in Figure 4 (c) is less than that in Figure 4 (b) even though the Al2O3 thickness is smaller as shown in the layer structure Figure 4 (b’’) and (c’’). As the thickness of Al2O3 main layer increases as shown in Figure 4 (d’’), a very low current leakage near the level of instrument noise was observed in Figure 4 (d), indicating high quality of the Al2O3 gate dielectrics with the NL prepared at a low temperature. Figure 5 shows the AFM line scan profiles along the Si and MoS2 surface before and after the deposition of an Al2O3 layer, in which the 10-cycle NL and the 100-cycle Al2O3 main layer were prepared at 80°C and 180°C, respectively. It is seen from Figure 5 (a) that the thickness of MoS2 is ~79.2 nm. The step

height between the Si and MoS2 surface remains almost identical (79.1 nm) after the Al2O3 deposition as shown in Figure 5 (b), indicating that the thickness of the Al2O3 layers deposited on MoS2 and Si are nearly the same. Compared to the chemical inertness of the MoS2 surface, the Si surface is more chemically active due to the presence of a significant amount of dangling bonds and surface defects [27, 28]. Because the ALD of Al2O3 relies on the chemical adsorption on the surface, the Al2O3 growth rate on Si (typically ~0.09 nm/per ALD cycle) is much higher than that on the MoS2 without any surface functionalization [9, 10, 29, 30]. Hence it can be deduced that the low-temperature physical adsorption dominates the NL growth. The low-temperature physical adsorption provides a similar Al2O3 NL on Si and MoS2, regardless of the great difference between the amount of dangling bonds at the Si and MoS2 surface. Because the thickness of the Al2O3 layers deposited on MoS2 and Si are almost identical, the thickness of the Al2O3 layer on MoS2 can be obtained according to that on Si, which can be easily extracted by SE. (Because the area of MoS2 flakes fakes is usually much smaller than the optical spot sizes in the SE, it is very difficult to characterize the films on MoS2 using SE.) The SE characterization gives the Al2O3 growth rates of ~0.12 nm/cycle and ~0.09 nm/cycle at the deposition temperatures of 80 oC and 180oC, respectively. In the ALD process, the precursor adsorption mechanisms can be classified into the chemical and physical adsorption. The Al2O3 growth rate (~0.09 nm/cycle) at 180oC is in good agreement with those reported in the typical ALD process window [31, 32], indicating that the Al2O3 growth at 180oC proceeds via chemical adsorption. The higher Al2O3 growth rate (~0.12 nm/cycle) at a low temperature of 80oC reveals that the low-temperature physical adsorption is the dominant mechanism for the NL growth. Note that the SE characterization gives the Al2O3 thickness on MoS2 as shown in Figure 3 (a) is only 5.8 nm. Together with the AFM topography as shown in Figure 3(a), it can be deduced that a continuous, uniform, and pinhole-free Al2O3 layer with a thickness below 10 nm can

be achieved on MoS2 with the NL prepared by the low-temperature physical adsorption. Figure 6 shows the Raman spectra of the as-exfoliated MoS2 and that covered with a 10-cycle Al2O3 NL. Raman spectroscopy has been widely used to characterize the MoS2 structure since the Raman shift clearly reveals the change in lattice structure. The Raman peaks at ∼383 cm−1 and ∼408 cm−1 are assigned ଵ to the ‫ܧ‬ଶ௚ mode (the in-plane motion) and the A1g mode (the out-of-plane motion) in bulk MoS2,

respectively [33]. These two Raman peaks have been considered as a signature of the MoS2 lattice structure since they shift with the variation in strain, doping, etc. [34, 35]. Figure 6 (a) shows that no detectable change in the Raman peaks can be observed with the deposition of the 10-cycle Al2O3 NL at 80°C on exfoliated MoS2. On the other hand, the Raman shift at ∼820 cm−1 is associated with the formation of MoO3 [36]. The lack of noticeable Raman peak at ∼820 cm−1 as shown in Figure 6 (b) suggests the absence of MoO3 after the deposition of the low-temperature NL. It has been reported that MoS2 is stable in oxygen-rich ambient in the temperature range below 370°C [36]. Thus the deposition of the Al2O3 NL at a low temperature of 80°C does not lead to the chemical reaction between oxygen and MoS2, as expected. The result indicates the preparation of the low-temperature Al2O3 NL would not cause damage in the MoS2 structure, which is highly beneficial to the device performance. To further verify the finding obtained from the Raman spectroscopy, the ex-situ XPS was conducted to probe the binding energies of Mo 3d, S 2s, and S 2p core states of the MoS2 flakes with and without the deposition of the 10-cycle Al2O3 NL at 80°C. It is seen from Figure 7 that the XPS peaks located at ~233.2 and 230.1 eV are associated with the Mo4+ 3d3/2 and Mo4+ 3d5/2 binding energies, and those around 227.3, 162.9, and 164.1 eV corresponds to the S 2s and S 2p 3/2 and S 2p 1/2 states, respectively. Note that there is no peak appearing around 236 eV, indicating that the deposition of the low-temperature Al2O3 NL did not result

in the oxidation of molybdenum [37, 38]. The almost identical XPS spectra of the as-exfoliated MoS2 flake and that covered with the low-temperature NL reveal the absence of chemical reactions. The result demonstrates that the deposition of the NL proceeds via the low-temperature physical adsorption, which is consistent with the outcome deduced from the Raman spectroscopy. The IDS(drain current)-VTG(top gate voltage) and ITG(top gate leakage current)-VTG(top gate voltage) curves of the top-gated MoS2 transistor are shown in Figure 8. In this top-gated MoS2 transistor, the low-temperature Al2O3 NL was introduced underneath the Al2O3 main layer and the total thickness of the Al2O3 gate dielectric was ~9.8 nm. The thickness of the MoS2 channel was 9.1 nm (~14 monolayers of MoS2) as revealed in the AFM line scan profile shown in Figure S1 in the Supplementary Material. As shown in Figure 8 (a), the IDS-VTG characteristics at VDS(drain voltage) = 2V give a low subthreshold swing minimum (SSmin) of 88 mV/decade and an on/off ratio of the current over 105. In addition, a low hysteresis was also observed in the top-gated MoS2 transistor as shown in the forward and backward IDS-VTG curves (Figure 8 (a)), suggesting a low density of charge traps in the Al2O3 gate dielectric [39-41]. Notice that the top-gated MoS2 transistors usually exhibited the typical normally-on characteristics as reported in literatures [1, 8, 11, 14-16, 42, 43], the IDS-VTG characteristics as shown in Figure 8 (a) indicates the normally-off operation in this top-gated MoS2 transistors. The positive threshold voltage might result from the high work function of the Pt metal gate and the low fixed charge density in the Al2O3 gate dielectric [8, 44]. The ITG-VTG curve at VDS = 2V reveals a low level of the gate leakage current with only a few pA as shown in Figure 8 (b), demonstrating the high quality of the sub-10 nm Al2O3 gate dielectric due to the continuous, uniform, and pinhole-free structure. The sub-10nm Al2O3 high-K gate dielectrics prepared with the low-temperature NL shows promising for low hysteresis, low subthreshold swing, and normally-off operation of the top-gated

MoS2 transistors.

Conclusion High-quality, uniform, pinhole-free, and sub-10nm Al2O3 gate dielectrics on MoS2 without surface functionalization were demonstrated in this study. The low-temperature physical adsorption along with a short purge time in the ALD process was exploited to prepare an ultrathin Al2O3 layer on MoS2, which acts as the NL for the onset of uniform deposition of the overlaying Al2O3 main layer at a higher temperature. No detectable MoS2 oxidation states were observed by the XPS and Raman spectra, indicating the physical adsorption is the dominant mechanism in the deposition of the Al2O3 NL at a low temperature. The gate leakage current was remarkably suppressed by the insertion of the low-temperature NL between the Al2O3 main layer and MoS2, as revealed by the CAFM characterization. As a result, the low hysteresis and subthreshold swing, as well as the normally-off operation were achieved in the top-gated MoS2 transistors, indicating the high quality of the sub-10nm high-K gate dielectrics prepared with the NL through the low-temperature physical adsorption on TMDs.

ASSOCIATED CONTENT Supplementary Material. Material Thickness of the MoS2 flake used as the channel material in the top-gated MoS2 transistor

AUTHOR INFORMATION

Corresponding Author * E-mail: [email protected]

ACKNOWLEDGMENT The authors gratefully acknowledge the financial support from Taiwan Semiconductor Manufacturing Company (TSMC) and the Ministry of Science and Technology (MOST 106-2622-8-002 -001), Taiwan.

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Figure Captions Figure 1.

Schematic diagram of (a) the layer structure of the Al2O3 gate oxide including the Al2O3

nucleation layer (NL) and the main layer, and (b) the top-gated MoS2 transistor. Figure 2.

AFM images of the Al2O3 NL prepared with (a) 10 and (b) 50 ALD cycles on MoS2. Each image

is 2×2 µm2 in area with a scale bar of 400 nm. Figure 3.

AFM images of the Al2O3 layer on MoS2 along with the corresponding layer structure and

deposition conditions. Each AFM image is 2×2 µm2 in area with a scale bar of 400 nm. Figure 4.

(a) Schematic diagram of the CAFM measurement on the Al2O3 layer on MoS2. (b, c, d), (b’, c’,

d’), and (b”, c”, d”) are the leakage current maps, surface morphologies, and the corresponding layer

structures/deposition conditions, respectively. The DC bias in the CAFM measurement was -2 V, -7 V, and -7 V, respectively, to get the leakage current map (b, c, d). Each CAFM image is 2×2 µm2 in area with a scale bar of 400 nm. Figure 5.

AFM line scan profiles along the Si and MoS2 surface (a) before and (b) after the deposition of

an Al2O3 layer. Figure 6.

Raman spectra of the as-exfoliated MoS2 (blue) and that covered with a 10-cycle Al2O3 NL

(red). Figure 7.

XPS spectra of the Mo 3d, S 2s, and S 2p core levels in the as-exfoliated MoS2 (blue) and that

covered with a 10-cycle Al2O3 NL (red). Figure 8.

(a) IDS-VTG and (b) IG-VTG characteristics of the top-gated MoS2 transistor measured at a drain

bias VDS = 2V.

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Graphical abstract