Buried-channel MOS transistor with punch-through

Sobd-Stare E/@cfronrcs Printed in Great Bnta~n

Vol.27,

Nos. R/9. pp. 81 I-815,

1984 0

003x-1101/84 $3.00 + .I0 1984 Pergamon Press Ltd.

BURIED-CHANNEL MOS TRANSISTOR WITH PUNCH-THROUGH BOGDANM. WILAMOWSIU ECE Department,

University of Arizona, Tucson, AZ 85721, U.S.A.

RICHARD C. JAEGER EE Department, Auburn University Auburn, AL 36849, U.S.A.

and JAMES N. FORDEMWALT ECE Department University of Arizona Tucson, AZ 85721, U.S.A. (Received

20 December

1982; in revisedform

6 August

1983)

Abstract-The punch-through phenomenon is normally considered as a parasitic mechanism in MOS devices, which is critical for short channel MOS transistors. An MOS transistor operation in the presence of punch-through is studied in this paper. A proper device geometry and additional substrate biasing enable useful voltage gain of the transistor, even if the punch-through is the dominant mechanism. Principle of operation and experimental data of the MOS controlled punch-through transistor is presented.

LNTRODUCrION The semiconductor device with carrier injection over an electrostatically induced potential barrier, named the Static Induction Transistor (SIT), was invented by Nishizawa et al. [ 1). A very similar concept using GaAs Schottky gate is known as the permeable base transistor[2, 31. These types of transistors operate with opposite polarity of gate and drain voltages and, therefore, they have limited applications for digital circuits. Also, their structures are not very suitable for integration in general. However, using the bipolar mode of SIT and 5 pm photolitography rules, the integrated logic with power-delay product of 0.002 pJ is reported[4, 51. This logic structure is very sensitive to the fabrication parameters[6,7]. The concept with the MOS gate controlled SIT structure is also proposed by Nishizawa[8]. The assumption was that the gate threshold voltage can be shifted using, e.g. the ion implantation technique. Charge accumulation under MOS gate is the main problem there, so the electrical field penetration is very shallow. Even for very high gate voltages, it is not possible to turn the device off. Using the tetrode structure with two gates, a MOS and a junction one, it seems possible to overcome this difficulty. The study of such a structure is covered in this paper. Analysis and experiment of a MOS tetrode was already published by Bichman[9], but this device was considered mainly as a MOS transistor with the substrate being the fourth electrode. Also, similar structures were recently described as buried or subsurface MOS transistors[lCLl4]; however, these transistors operate as a junction FET with a long channel. In the case of the device described here, the buried channel transistor operates in the punch-through and the space-charge-limited mode. This device is similar to the planar structure of lateral punch-through transistor published recently [ 151.However, instead of SSE

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the gate made by the impurity diffusion, the gate is formed with the surface region inverted by the voltage applied to the MOS gate. This structure, contrary to the lateral punch through transistor where the gate is shorted to the substrate, is suitable for integration. DEVICE STRUCTURE

The basic device structure is shown in Fig. 1. Two MOS transistors, one with a p-type channel and the other with a n-type one, share a common gate but have perpendicular channels. The n-type surface channel of one of these transistors acts as a gate for the other transistor with the p-type buried channel.

Lb) A-A

ICI 8-B

N-

N-

Fig. 1. The buried punch-through MOS transistor: (a) top view, (b) cross section of the n-channel surface device, (c) cross section of the p-channel buried punch-through device.

B. M. WILAMOWSKI et al

X12

This buried p-type channel transistor operates in a punch-through mode. During normal operation, the source and drain of the n-type surface channel transistor are shorted to n-type substrate and connected to a positive voltage. The source of the p-type buried transistor is grounded, and drain is connected to a negative voltage. The equivalent circuit of this device for the purpose of analysis is shown in Fig. 2. For various voltages of the MOS gate, the device has different modes of operation (Fig. 3). For positive voltage on the MOS gate, the n-type region is induced near the surface (Fig. 3a). This n-type region with positive biasing operates as a gate, similar to the gate of the lateral punch-through transistor [ 151. If a negative voltage is applied to the MOS gate, the surface will be inverted to the p-type and the punch-through current will flow for relatively small voltages between the p-type source and drain. In addition to the punch-through current, the current in the p-type surface channel may also flow (Fig. 3b). The device will operate in the accumulation punch-through mode[l6, 171.

Fig.

2. The

equivalent

circuit of buried MOS structure.

punch-through

EXPERIMENT

First, two buried p-type device structures with different geometry were fabricated. The fabrication facilities limit the size of devices to relatively large ones. Therefore, in order to observe the desired effects, low substrate background impurity concentration with high resistivity (600 Q-cm) was chosen. Device No. 1 had a source-drain spacing equal to 7.5 pm covered by the MOS gate. The source-drain spacing in device No. 2 was 10 pm and only half of this region at the source side was covered by the MOS gate (Fig. 4). The drain current of device No. 2 as a function of drain voltage for various junctions, and MOS-gatebiasing is shown in Figs. 5 and 6 using linear and logarithmic scales, respectively. These characteristics are very similar to those of the lateral punch-through G

S

D

7///////////////// -

P

P

-

i

Fig. 4. The cross section of fabricated devices: (a) device No. I with 7.5 pm source-drain spacing, (b) device No. 2 with 10pm spacing and partly covered channel.

mA

A

ID

(a)

+ G,mitiorl

lb)

Fig. 3. Two modes of operation of a buried transistor: (a) punch-through mode, (b) accumulation and punch-through mode.

Fig. 5. The drain characteristics of device No. 2 with the MOS gate voltages equal to + 15, 0, - 15 V and the n-type junction gate voltages varying from 0 to 10 V (2 V per step). For MOS gate voltage equal to - 15 V, the junction gate biasing has only small effect on the device characteristics.

Buried channel MOS transistor with punch-through

Fig. 6. The drain characteristics of device No. 2 drawn in log-lin scale with the MOS gate voltages equal to + 15, 0, - 15 V and the n-type junction gate voltages varying from 0 to 10 V (2 V per step).

transistor[l5] where the carrier injection over the potential barrier [ 181 and the space.charge-limited current are the dominant mechanisms. The punchthrough voltage for this device is the function of the voltages on both gates. Figure 7 shows the punchthrough voltage (measured at 1 PA drain current) as the function of MOS gate voltage and the junction gate voltages as parameters. If the junction gate has zero biasing, then the MOS gate voltage has little effect on the value of punch-through voltage. The voltage gain is much smaller than unity because the MOS gate action is limited by the charge accumulation of carriers near the surface. Therefore, the standard MOS structure cannot be directly applied as the gate controlled punch-through device. Significant improvement in the current gain is observed when the positive voltage is applied to the additional junction gate (Fig. 7). This effect can be interpreted as the effect of transition to the other

-6

-6

-4

-2

mode of operation. For highly negative voltages on the MOS gate, the p-type channel with hole accumulation exists near the surface, and punch-through voltage between this p-type surface channel and p-type drain is relatively small. Higher values of junction gate potentials have almost no effect on the punch-through voltages. This mode of operation is illustrated in Fig. 3(b). For highly positive voltages applied to the MOS gate, the surface is inverted to the n-type region which is internally connected with the junction gate. Voltages of the junction gate have significant effects on the drain current. The terminal voltages induce a potential barrier whose height is controlled both by the applied voltages to the junction gate and drain and also by the carrier spacecharge, which is proportional to the current density. This mode of operation is illustrated in Fig. 3(a) and is very similar to the one described in [ 151. In the case of device No. 1 where the MOS gate covers the whole region between source and drain, the effect of the junction gate was smaller (Fig. 8). These two modes of transistor action also can be observed on the gate characteristics for fixed drain voltage. Such characteristics of device No. 2 are shown in Fig. 9. For negative voltages on the MOS gate, the drain current is independent on the junction gate voltage when the MOS gate controls the accumulation space-charge-limited drain current (Fig. 3b)[9, 16, 171. In the case where positive voltage is applied to the MOS gate, the n-type region is induced under MOS gate and the device operation is similar to those of the lateral punch-through transistor[ 151. A similar bchaviour was observed by Richman[9], but the induced gate was not mentioned and the results were interpreted as an effect of substrate interaction. In order to investigate this substrate L mA

‘0

Ohms

/ -10

813

2

4

6

e

Fig. 7. The effect of the junction and the MOS gate biasing on the source-drain punch-through voltage.

Fig. 8. The drain characteristics of device No. 1 with the MOS gate voltages equal to + 15, 0, - 15V and the n-type junction gate voltages varying from 0 to 10 V (2 V per step).

B. M. WILAMOWSKI et al.

814 A

(mAI--

t

1~

‘D

71 I 6 .

-_*...v 10 Fig. 9. The MOS gate characteristics of device No. 2 with the n-type junction gate voltages as parameters and the fixed-drain voltage equal 40 V.

,

I

I

,

/

SUBSTRATE

- N-/&--‘*

Fig. 10. The top view of device No. 3.

effect, a special device structure shown in Fig. 10 was fabricated and tested. In this structure, the MOS gate region is surrounded by the drain region, so there is no internal connection between the n-type substrate and the electron accumulated region under MOS gate. The drain characteristics for highly positive MOS gate voltages and various substrate voltages are shown in Fig. 11. The substrate voltage has a very small effect on the drain current in this case. Therefore, the drain current dependence of junction gate (substrate) voltages for devices No. 1 and 2 can be interpreted as the effect of induced gate and not as the direct substrate interaction. DISCUSSION The device speed is generally inversely proportional to the operating voltage. In the case of MOS type devices, the threshold voltage instability and its reproducibility limit the supply voltage lowering. Therefore, a simple size reduction will lead generally to the punch-through phenomenon unless substrate impurity concentration is increased. This, however, increases the value of parasitic capacitances.

20.-------

30

2

40

V

Fig. Il. The drain characteristics of the device No. 3 with the MOS gate voltages equal to + 15, - 15 V and the n-type junction gate voltages varying from 0 to 10 V (2 V per step). The junction gate biasing has minor effect on the drain current.

In this paper, the problem of MOS transistor operation in the presence of punch-through was studied. Special device modifications and additional biasing causes a useful gain, even if the punchthrough phenomenon is present. A small transit time (large electrical field) and small parasitic capacitances (small substrate impurity concentration) are advantages of this device. In measured devices, the voltage gain was relatively small, usually not more than two. However, further device geometry modifications may improve this parameter. One of the disadvantages of this structure is that the additional biasing of the junction gate (substrate) is necessary. However, current requirements for such additional biasing are very small. Also, for high speed applications, the effect of series resistance between junction gate and enhancement region under MOS gate should be studied.

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Buried channel MOS transistor with punch-through

7. 8. 9. 10.

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on 1981 Symp. on VISZ Tech., pp. 40-41 (Sept. 1981); also IEEE Trans. Electron Dev. ED-28, 1354-1363 (1981). J. Nishizawa, T. Ohmi and H. L. Chen, IEEE Trans. Electron Deu. ED-29, 1233-1244 (1982). J. Nishizawa, Semiconductor Technologies 1982, pp. 201-219, by OHM-Tokyo. P. Richman, IEEE Trans. Electron Dez. ED-16,759-766 (1969). E. Z. Hamdy, M. I. Elmasry and Y. El-Mansy, A novel single-device-well MOSFET gate. Proc. IEEE ZEDM, Washington, D.C. 576-580 (Dec. 1979). E. Z. Hamdy and M. I. Elmasry, IEEE J. Solid-St. Circuits W-17, 2-8 (1982). S. D. S. Malhi, C. A. T. Salama, W. R. Donnison and H. D. Barber, IEEE Trans. Electron Dev. ED-28, 1447-1454 (1982).

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13. R. E. Howard, L. D. Jackel, R. G. Swartz, P. Grabbe, V. D. Archer, R. W. Epworth, E. L. Hu, D. M. Tennant and A. M. Voshchenkov, IEEE Electron Dev. Lett. EDG3, 322-324 (1982). 14. K. Nishiuchi, H. Shibayama, T. Nakumura, T. Hisatsugu, H. Ishikawa and Y. Jukukawa, J. Solid-St. Circuits SC-15, 808-816 (1980). 15. B. M. Wilamowski and R. Jaeger, Electron Deu. Mt. EDGJ, 271-280 (1982). 16. P. Ratnam and A. B. Bhattacharyya, Electron Dev. Left. EDL-3, 203-204 (1982). 17. C. Kim and E. S. Yang, Solid-St. Electronics 13, 1577-1589 (1970). 18. P. Plotka and B. M. Wilamowski, Solid-Sr. Electronics 23, 693-694 (1980).