Bus encoder design for reduced crosstalk, power and area in coupled VLSI interconnects

Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎

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Bus encoder design for reduced crosstalk, power and area in coupled VLSI interconnects Brajesh Kumar Kaushik n, Deepika Agarwal, Nagendra G. Babu Department of Electronics and Communication Engineering, Indian Institute of Technology—Roorkee, Roorkee-247667, Uttarakhand, India

art ic l e i nf o

a b s t r a c t

Article history: Received 23 July 2012 Received in revised form 1 April 2013 Accepted 4 April 2013

This research work presents a novel circuit for simultaneous reduction of power, crosstalk and area using bus encoding technique in RC modeled VLSI interconnect. Bus-invert method is used to reduce inter-wire coupling, which is actually responsible for crosstalk, delay and power dissipation in coupled interconnects. The proposed method focuses on simplified and improved encoder circuit for 4, 8 and 16 coupled lines. In past, the researchers developed encoders that usually focused on minimizing power dissipation and/or crosstalk, thereby paying heavy penalty in terms of chip area. However, the proposed encoder and decoder while significantly reducing crosstalk demonstrates an overall reduction of power dissipation by 68.76% through drastically limiting switching activity. Furthermore, while reducing the complexity, chip area and transistor count of the circuit is reduced by more than 57%. & 2013 Elsevier Ltd. All rights reserved.

Keywords: Bus-invert Inter-wire coupling Crosstalk Power dissipation Switching activity

1. Introduction In deep submicron VLSI design, feature size will continue to shrink while the clock frequency will keep on increasing rapidly. In case, the current trend of technology scaling continues, the devices and gates would be much smaller and faster [1,2]. However, the interconnect delay is expected to increase, therefore, interconnect delay will dominate over gate delay [2]. Shrinking feature size implies not only shorter gate lengths but also decreasing interconnects pitch. Hence, minimizing the power consumption and crosstalk delay in interconnects is the most important design criteria in on-chip bus design [3–5]. These effects are dominated by coupling capacitance and load capacitance. Load capacitance is the capacitance between wire and the substrate. The capacitance between the two interconnects which are adjacent is called coupling capacitance. This capacitance causes crosstalk, leads to serious timing and signal integrity problems and results in circuit malfunctioning in the worst case. It affects delay and slew depending on the switching configurations of aggressor and victim lines. There are different methods such as repeater insertion [6], shielding line (V dd /GND) insertion between two adjacent wires [7], optimal spacing between signal lines and lastly the most effective bus encoding method [8–10] for reducing the crosstalk delay.

n Corresponding author. Tel.: +91 1332 285662 (O); +91 1332-285160 (R); Mob.: +91 9412307694; +91 7417352327; fax. +91 1332 273560. E-mail addresses: [email protected], [email protected] (B.K. Kaushik).

A bus encoding method converts or encodes the data bit stream in such a way that the number of transitions of bit stream is minimized. This paper focuses on reducing power dissipation, crosstalk and chip size of the encoder and decoder by using bus-invert method [9]. This method reduces power and crosstalk delay by decreasing switching and coupling activities. The proposed method eliminates the most undesirable crosstalk types in RC coupled interconnects i.e. Type-4, Type-3 and some of the Type-2 couplings. Results show that the power dissipation, crosstalk, delay are reduced and the size of the encoder implemented occupies lesser chip area as compared to Fan et al. [12]. The paper is organized in six sections including the current section pertaining to Section 1. Section 2 describes the classification of crosstalk, whereas, Section 3 comprises of power dissipation expression and their dependence on different parameters. The functioning of proposed encoding method is explained in Section 4. Sections 5 discusses the experimental results of proposed RC encoder. Finally, in Section 6 important outcome of the proposed encoder design is summarized. 2. Classification of crosstalk The parasitic capacitance of a typical interconnect structure shown in Fig. 1 constitutes of three elements, ground capacitance (C G ), fringe or side-wall to substrate capacitance (C F Þ and coupling capacitance or capacitance between the adjacent walls on the same layer (C C Þ. Coupling capacitance becomes dominant when two adjacent lines are switching in the opposite direction, which causes crosstalk

0026-2692/$ - see front matter & 2013 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.mejo.2013.04.001

Please cite this article as: B.K. Kaushik, et al., Bus encoder design for reduced crosstalk, power and area in coupled VLSI interconnects, Microelectron. J (2013), http://dx.doi.org/10.1016/j.mejo.2013.04.001i

B.K. Kaushik et al. / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎

2

¼ ðαcl þ λ  αcc ÞC L  V 2dd  f

ð2Þ

where C L is the load capacitance, V dd is supply voltage, f is the clock frequency, λ is ratio of C C =C L , αcl is average switching factor. The un-coded αcl value is 1. As all other parameters are already optimized, the power dissipation that also depends on the switching activity should be reduced (i.e., proportional to the number of signal transitions). Symbols used throughout this paper are as follows:

     

Fig. 1. Parasitic capacitance model [2].

Table 1 Coupling factor of Line ‘A’ [11]. Line ‘B’

ΔV

C ef f ðAÞ

Miller coupling factor (MCF)

Switching with ‘A’ Constant Switching opposite ‘A’

0 V dd 2V dd

CG CC þ CG 2C C þ C G

0 1 2

d(t): Bus value at the input of encoder. D(t): Encoder output which is transmitted. D(t−1): Encoder output which was latched up. inv(t): Invert line at the input of encoder which is preset to ‘0’. INV(t) : Invert line for the encoded data sent at time t. INV(t−1): Invert line for encoded data sent at time t−1.

4. Implementation of proposed design

resulting in delay penalty which is called crosstalk delay. There are two important effects due to this crosstalk i.e. noise on nonswitching wires and increased delay on switching wires. Assume two lines namely A and B and their associated capacitances as shown in Fig. 1. According to the behavior of neighboring wire, the effective coupling capacitance ðC ef f Þ is defined. Table 1 [11] shows the dependence of effective capacitance of line A ðC ef f ðAÞ Þ on the line B (assume line A is switching). Certain inferences can be drawn from Table 1. First, when both adjacent lines are switching in the same direction then MCF is ‘0’ which indicates that there is no coupling capacitance. Second, if one line is switching and the other is quiet then MCF is ‘1’ whose coupling capacitance is greater as compared to above case. Finally, when two adjacent lines are switching in opposite direction then the coupling capacitance is high (MCF is ‘2’) due to which crosstalk effect becomes dominant [13,14]. In a data bus there will be lines on both sides of the line of interest as shown in Fig. 1. Therefore, various coupling capacitances associated with the 3-bit configuration must be considered. Line ‘B’ is the line of interest and Line ‘A’, Line ‘C’ are the adjacent lines to it. Coupling factors associated with the Line ‘B’ depending on the switching configurations of Line ‘A’ and Line ‘C’ are shown in Table 2. Switching configurations of the type shown in Table 2 are classified as Type-0 that signifies a coupling factor of ‘0’. The switching configurations shown in Table 3 are classified as Type-1 which signifies a coupling factor of ‘1’. The switching configurations shown in Table 4 are classified as Type-2 which signifies a coupling factor of ‘2’. The switching configurations shown in Table 5 are classified as Type-3 which signifies a coupling factor of ‘3’. The switching configurations of the type shown in Table 6 are classified as Type-4 which signifies a coupling factor of ‘4’. Finally, all the possible switching configurations can be classified as Type-0, Type-1, Type-2, Type-3 and Type-4, are summarized in the Table 7. Among all these types, Type-4 and Type-3 results in most severe crosstalk levels. This paper, therefore, focuses on reducing these types of crosstalk.

Inspired by Fan et al. [12] bus encoding method, a new and improved design is proposed which significantly reduces the crosstalk and power dissipation of the RC modeled interconnect. As discussed in Section 3, reducing switching activity is one of the popular methods to decrease the power consumption in interconnects. The proposed method also strives to limit the number of transitions. In this proposed method, the data bus is partitioned into different clusters. Each cluster is of 5-bit width, with four data bit wide and one control bit (INV(t)). Bus invert (BI) method [9] uses a control line called invert pin to differentiate between the transmission of original data and inverted data. As per BI method, if the number of transitions that are being transmitted are more than half of the bus width, then the original data is inverted and the control line INV(t) is set to ‘high’, otherwise, the original data are transmitted and the control line INV(t) is set to ‘low’. Accordingly, the proposed method inverts the original data if there is any crosstalk and sets control bit to logic ‘high’. For this purpose the proposed design must detect the input data which causes crosstalk. The crosstalk condition is detected by comparing the present data with the previous one and depending on type of transition of the data bits a decision is made i.e., whether the input data causes a crosstalk or not. However, the architectures of the encoder and decoder should be of low complexity so that the power and delay overheads due to the codec circuitry can be compensated by the significant reduction of bus delay. The block diagram of proposed encoder is shown in Fig. 2. The proposed encoder consists of four major blocks: transition detector, Type-A detector, Type-B detector and multiplexer [13,14]. The original data (d(t), inv(t)) and the previously latched data (D(t−1), INV(t−1)) are fed as inputs to transition detector. Initially, the value of inv(t) is assumed to be at logic ‘low’. The signal outputs of transition detector are fed to Type-A and Type-B detectors. The outputs of Type-A and Type-B detectors are N_A and N_B which are fed as inputs to an OR gate whose output is INV(t). This INV(t) and the original data (d(t),inv(t)) are given as inputs to XOR stack. The output of XOR stack can be inverted data (if INV(t) is ‘1’) or the original data (if INV(t) is ‘0’). The output of the XOR stack is the encoded data (D(t), INV(t)) which is finally fed to interconnects. This encoded data are stored in latch for one clock cycle (D(t−1), INV(t−1)), after which it is fed back for comparison with (d(t), inv(t)). Finally, at the receiving side, decoder retrieves the original data with the help of INV(t) line.

3. Expression for power dissipation 4.1. Transition detector The power dissipation [12] in VLSI interconnects can be expressed as P ¼ ðαcl  C L þ αcc 

C C ÞV 2dd

f

ð1Þ

Transition detector checks the occurrence of transition by using AND gates. The top 5 AND gates detects the low to high transition (↑) and the bottom 5 AND gates detects the high to low transition

Please cite this article as: B.K. Kaushik, et al., Bus encoder design for reduced crosstalk, power and area in coupled VLSI interconnects, Microelectron. J (2013), http://dx.doi.org/10.1016/j.mejo.2013.04.001i

B.K. Kaushik et al. / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎ Table 7 Classification of crosstalk.

Table 2 Type-0 coupling. Line A

Line B

Line C

MCF

Quiet Switching in same direction of ‘B’

Quiet Switching

Quiet Switching in same direction of ‘B’

0 0

Line A

Line B

Line C

MCF

Quiet Quiet

Quiet Switching

1 1

Switching Switching in same direction of ‘B’

Quiet Switching

Switching Switching in same direction of ‘B’ Quiet Quiet

Type-0

Type-1

Type-2

Type-3

Type-4

––– ↑↑↑ ↓↓↓

– –↑ – ↑↑ ↑– ↑↑ ––↓ – ↓↓ ↓– ↓↓ -

–↑– ↑– ↑ ↑– ↓ ↑↑↓ ↑↓↓ –↓↓- ↓ ↓– ↑ ↓↓↑ ↓↑↑

– ↑↓ – ↓↑ ↑↓ ↓↑ -

–↑↓↑ ↓↑↓

Table 3 Type-1 coupling.

↑: Switching from 0 to 1, ↓: switching from 1 to 0, : no transition.

1 1

5

10 d(t),inv(t) 5

10

Line A

Line B

Line C

Quiet Switching Switching in same direction of ‘B’ Switching in opposite direction of ‘B’

Switching Quiet Quiet Switching Switching Switching in opposite direction of ‘B’ Switching Switching in same direction of B

2 2 2

Line A

Line B

MCF

Quiet

Switching Switching in opposite direction of ‘B’ Switching Quiet

3

Line A

Line B

MCF

Switching in opposite direction of ‘B’

Switching Switching in opposite direction of ‘B’

Table 5 Type-3 coupling. Line C

3

Table 6 Type-4 coupling. Line C

D(t-1),INV(t-1) Latch

1

1 INV(t) 1

Type-B Detector

XOR Stack

5 5

D(t),INV(t)

5

MCF

2

Type-A Detector

Transition Detector

Table 4 Type-2 coupling.

Switching in opposite direction of ‘B’

3

Fig. 2. Block diagram of proposed encoder.

Sb, Sh), (Sb, Sc, Si) and (Sc, Sd, Sj) to high. Similarly, bottom three NAND gates detects first case (–↑↓) of Type-3 and second case (↓↑↓) of Type-4 coupling and sets one or more than one number of three combinations i.e. (Sf, Sg, Sc), (Sg, Sh, Sd) and (Sh, Si, Sg). The output from the final NAND gate i.e., N_A goes ‘high’ if any of switching conditions i.e., {(–↑↓),(–↓↑), (↓↑↓),(↑↓↑)}is detected by Type-A detector. Fig. 5 shows the detector which detects two cases of Type-3 coupling and all the cases of Type-4 coupling. The top three NAND gates detects fourth case (↓↑-) of Type-3 and second case (↓↑↓) of Type-4 coupling. In these cases, the transition detector (Fig. 2) sets one or more than one number of three combinations i.e., (Sa, Sg, Sh), (Sb, Sh, Si) and (Sc, Si, Sj) to high. Similarly, bottom three NAND gates detects third case (↑↓–) of Type-3 and first case (↑↓↑) of Type-4 coupling and sets one or more than one number of three combinations i.e., (Sf, Sb, Sc), (Sg, Sc, Sd) and (Sh, Sd, Se). The output from the final NAND gate i.e., N_B goes ‘high’ if any of switching conditions i.e., {(↓↑–), (↑↓–), (↓↑↓), (↑↓↑)} is detected by Type-B detector. 4.3. XOR stack

4

(↓) as shown in Fig. 3. For this purpose it uses the data which is transmitted previously, it compares the present data with the previous data. If there is any transition the output becomes ‘high’ otherwise it is ‘low’. 4.2. Type-A and Type-B detectors As discussed in Section 2, there are two cases of Type-4 coupling and four cases of Type-3 coupling (Table 2). The circuit diagram of type-A detector is shown in Fig.4. The top three NAND gates detect the second case (–↓↑) of Type-3 and first case (↑↓↑) of Type-4 coupling. In these cases, the transition detector (Fig. 2) sets one or more than one number of three combinations i.e., (Sa,

The truth table of XOR stack is shown in Table 8. When either N_A or N_B is ‘high’, the inverted data must be transmitted otherwise original data bits are transmitted. In this case, the data bit is fed as one of the input for the XOR gate and control line INV (t) is the second input to the 2-input XOR gates as shown in Fig. 6. If the INV(t) line is ‘high’ then it indicates that the inverted data must be transmitted and D(t) must be inverted to avoid the crosstalk and if it is ‘low’ then it indicates that the original data is to be transmitted.

5. Results The proposed design has been validated for 180, 130, 90, 70, 45 nm technology nodes using H-SPICE with pulse stimuli for 1 MHz, 100 MHz, 500 MHz and 1 GHz frequencies. The length,

Please cite this article as: B.K. Kaushik, et al., Bus encoder design for reduced crosstalk, power and area in coupled VLSI interconnects, Microelectron. J (2013), http://dx.doi.org/10.1016/j.mejo.2013.04.001i

B.K. Kaushik et al. / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎

4

INV(t-1) inv(t)

Sa Sg Sh

Sa

D3(t-1) d3(t) D2(t-1) d2(t)

Sb

Sb Sh Si

Sc Sc Si Sj

D1(t-1) d1(t)

Sd

Sf Sb Sc

D0(t-1) d0(t)

Se

INV(t-1) inv(t)

Sg Sc Sd

Sf

D3(t-1) d3(t)

Sh Sd Se

Sg

D2(t-1) d2(t)

N_B

Sh

Fig. 5. Circuit diagram of Type-B dectector.

D1(t-1) d1(t)

Si

Table 8 Truth table of XOR stack

D0(t-1) d0(t)

Sj

Fig. 3. Circuit diagram of transition detector.

Sa Sb Sh

N_A

N_B

MUX OUTPUT

0 1

0 0

(D(t),0)

0

1

ðDðtÞ; 1Þ

1

1

ðDðtÞ; 1Þ

ðDðtÞ; 1Þ

this net-list is simulated in H-SPICE. In coding the designed circuit full-custom design methodology has been employed so as to meet the requirements of high speed of encoders that are placed in data path. Power dissipation and propagation delay of the designed circuit is observed by H-SPICE simulations. All the results for power and delay are measured for only worst case scenario (↑↓↑↓↑) wherein they attain maximum value among all other switchings.

Sb Sc Si Sc Sd Sj

N_A

Sf Sg Sc

5.1. Chip area reduction The proposed design significantly reduces the number of transistors and therefore the overall chip area as well. The reduction in number of transistors is as large as 57% as compared to Fan et al. [12] (Table 9). Table 10 demonstrates the comparison of the area of the chip for different bit size encoders. For 180-nm technology, the approximated chip size of the proposed design is 24.90 μm2 in 4-bit encoder and on increasing the width of the bus, chip area will increase. Similarly, for 130, 90, 70, 45 nm technologies the area of bus codec design is 12.99, 6.22, 3.77, 1.56 μm2, respectively.

Sg Sh Sd Sh Si Se Fig. 4. Circuit diagram of Type-A detector.

width, thickness and spacing of the signal wire are 1300, 0.99, 0.53 and 1.37 μm, respectively. The proposed encoder design demonstrates significant reduction in chip area, crosstalk, power dissipation and propagation delay in comparison to Fan et al. [12]. The design flow which is used to generate results passes through various stages. Initially, the designed gate level circuit is simulated in VHDL for functionality and logical verification. Later, SPICE netlist has been coded for the designed circuit on transistor level and

5.2. Crosstalk reduction The proposed method reduces the worst case crosstalk effect that is introduced between redundant bit and clusters. Fig. 7 shows the use of redundant shielding line to eliminate Type-4 and Type-3 couplings between inter-cluster regions. The encoder used for 4-lines has been extended to 8 and 16 lines by using the shielding method as shown in Fig.7 Reduction in crosstalk can be estimated by considering all the possible switching configurations and the number of switching

Please cite this article as: B.K. Kaushik, et al., Bus encoder design for reduced crosstalk, power and area in coupled VLSI interconnects, Microelectron. J (2013), http://dx.doi.org/10.1016/j.mejo.2013.04.001i

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INV(t)

5

Vdd/GND

Line 1(INV pin)

D3(t)

d3(t)

Data Lines

D2(t)

d2(t)

Vdd/GND Line 6(INV pin)

D1(t)

d1(t)

Data Lines

D0(t)

d0(t)

Vdd/GND

Fig. 6. XOR stack.

Fig. 7. Interconnect routing for an 8-bit bus.

Table 9 Comparison of components with FAN et al. method. Components

Fan et al. [12]

Proposed method

% of saving

AND gate 6-bit adder XOR gate Number of transistors (4-bit encoder) Number of transistors (8-bit encoder) Number of transistors (16-bit encoder)

4-input 2 18 664

2-input 0 8 284

50% — 55% 57%

1196

492

59%

2354

986

58%

Table 10 Variation of chip size of proposed encoder Technology (nm)

180 130 90 70 45

Coding methods

Fan et al. Proposed Fan et al. Proposed Fan et al. Proposed Fan et al. Proposed Fan et al. Proposed

Area (μm2)

% of Area saved (average)

4 (bit)

8 (bit)

16 (bit)

39.12 24.90 20.41 12.99 9.78 6.22 5.92 3.77 2.45 1.56

82.17 172.56 52.29 109.80 44.89 103.25 28.57 62.86 20.54 43.13 14.32 31.49 13.61 31.29 8.28 17.39 5.62 12.93 3.27 7.51

36.35% 35.84% 36.12% 36.84% 36.02%

configurations which cause worst case crosstalk (Type-3 and Type4). In this bus encoding scheme the data which causes crosstalk is inverted and upon inversion it gets converted to a switching configuration whose coupling factor is less than the previous. Table 11 shows all the possible switching configurations and their respective switching configurations to which they are converted after inversion. It is observed that worst cases in RC modeled interconnects, Type-4 and Type-3 are being converted to Type-0 and Type-1 respectively after inversion. It is also noticed that some of the Type-2 cases are converted to Type-2 and the rest of Type-2 to Type-0 upon inversion. All the Type-1 cases and some of the Type-0 are converted to Type-1 and Type-0, respectively. The only limitation of this method is that the

no transition case of Type-0 (– – –) will be converted to Type-4. In such cases, worst case propagation delay is not reduced. In a 4-bit encoder there are five lines (4 bit lines+1 extra Inv line) and so there are three 3-bit combinations such as Line 1, Line 2, Line 3; Line 2, Line 3, Line 4; Line 3, Line 4, Line 5; so, there is a possibility of having combination of these five types of crosstalk for example Type-2 case in the first combination, Type-1 case in second combination and Type-4 in third combination. As there is a worst case, the data should be inverted and upon inversion the conversions will be Type-2 to Type-2, Type-1 to Type-1 and Type-4 to Type-0. Thus, it can be deduced that by inverting the data, there is no possibility of the occurrence of crosstalk except for no transition case (– – –). For a 4-bit encoder there are five lines with each line having three possibilities (– or↑or ↓) and so there are a total of 243 cases (35). Out of these 243 cases there are 110 cases in which the worst case crosstalk is going to occur. By inverting the data which causes crosstalk, cumulative MCF of all the possible switching scenarios of the lines is reduced from 789 to 276 which is a reduction of 65% in crosstalk. There is a probability of having a no transition and a worst case, wherein on inversion Type-0 gets converted to Type-4. Out of 110 cases where such crosstalk occurs, there are only four cases which has these limitations that means a probability of 0.03. Reduction of crosstalk in interconnects finally results in reduction of propagation delay also. 5.3. Total power reduction Total power dissipation of the system includes the power dissipated by encoder, interconnects and the decoderði:e:; P enc þP interconnects þ P dec Þ. Tables 12–16 show power dissipation statistics at 180, 130, 90, 70, 45 nm technologies with associated V dd as 1.8, 1.6, 1.5, 1.2 and 1.0 V, respectively. For a given technology node, as the bit size is increased the power dissipation also increases which is still considerably lesser than the Fan et al. method [12]. Encoders for 4, 8 and 16 bit interconnects are designed and the reductions in power dissipation are also shown in Tables 12–16. Considering the recent frequency range used for bus communications, the codec system design is verified at 1 MHz, 100 MHz, 500 MHz and 1 GHz frequencies. The results obtained shows that as the frequency is increased the percentage power saved also increases. Table 12 shows the power dissipation in 45 nm technology node. Furthermore, for every technology node it is observed that with increase in frequency the amount of power saved also increases. The power saving results for 70, 90, 130 and 180 nm are tabulated in Table 13–16, respectively.

Please cite this article as: B.K. Kaushik, et al., Bus encoder design for reduced crosstalk, power and area in coupled VLSI interconnects, Microelectron. J (2013), http://dx.doi.org/10.1016/j.mejo.2013.04.001i

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6

Table 11 Conversion of switching configurations after inversion Before inversion

After inversion ↑↑↑ ↓↓↓ ––– – –↑ −↑↑ ↑– – ↑↑− – –↓ −↓↓ ↓– ↓↓− – ↑↑↓ ↑↓↓ ↓↓↑ ↓↑↑ −↑− ↑−↑ ↑−↓ −↓− ↓−↓ ↓−↑ −↑↓ −↓↑ ↑↓− ↓↑− ↑↓↑ ↓↑↓

Type-0

Type-1

Type-2

Type-3

Type-4

Table 14 Power dissipation of codec system in 90 nm technology.

––– ––– ↑↓↑ or ↓↑↓ ↑↑− ↑– – −↑↑ – –↑ ↓↓− ↓– – −↓↓ – –↓ ––– ––– ––– ––– ↑−↑ −↑− −↓− ↓−↓ −↓− −↑− ↑– – or ↓– – ↑– – or ↓– – – –↑ or – –↓ −−↑ or – –↓ ––– –––

Frequency Coding methods

Power dissipation (μW) 4 (bit) 8 (bit)

1 MHz 100 MHz 500 MHz 1 GHz

Fan et al. Proposed Fan et al. Proposed Fan et al. Proposed Fan et al. Proposed

1.21 0.45 52.26 14.59 185.9 42.64 351.4 76.04

500 MHz 1 GHz

Type-2

Power dissipation (μW) 4 (bit)

1 MHz 100 MHz 500 MHz 1 GHz

Fan et al. Proposed Fan et al. Proposed Fan et al. Proposed Fan et al. Proposed

8 (bit)

2.69 6.25 9.62 0.78 1.94 3.13 164.4 395.4 572.4 49.58 99.73 158.3 792.1 1938 2737 212 445.9 724.1 1434 3571 5046 355 836.6 1220

Power dissipation (μW) 4 (bit)

Type-1

1 MHz 100 MHz

Type-0

500 MHz 1 GHz

% of power saved (average)

Fan et al. Proposed Fan et al. Proposed Fan et al. Proposed Fan et al. Proposed

69.10% 72.32% 74.59% 75.88%

Frequency Coding methods

61.55%

1 MHz

68.55%

100 MHz

69.85%

500 MHz 1 GHz

% of power saved (average)

69.3% 72.2% 72.5% 75.3%

8 (bit)

3.28 14.29 1.06 2.58 214.1 534 54.09 140 1008 2471 251.2 624.9 1845 3845 493.5 1016

% of power saved (average)

16 (bit) 11.5 7.15 719.2 216.4 3372 1005 6375 1574

62.53% 72.81% 73.33% 74.05%

Table 16 Power dissipation of codec system in 180 nm technology

56.46%

16 (bit)

2.17 5.4 7.34 0.69 1.51 2.35 92.1 231.9 313.6 25.64 55.9 98.45 434.4 1092 1467 110.2 261.4 483.2 776.5 1871 2655 201.3 387.6 725.6

16 (bit)

Table 15 Power dissipation of codec system in 130 nm technology Frequency Coding methods

Table 13 Power dissipation of codec system in 70 nm technology Frequency Coding methods

Fan et al. Proposed Fan et al. Proposed Fan et al. Proposed Fan et al. Proposed

8 (bit)

% of power saved (average)

Type-0

16 (bit)

2.14 5.49 1.09 2.32 106.15 209 28.77 126.1 518.5 744 85.56 408.5 842.2 1408 154.7 710.2

1 MHz 100 MHz

Table 12 Power dissipation of codec system in 45 nm technology. Frequency Coding methods

4 (bit)

Type-0 Type-4 Type-1

Power dissipation (μW)

Fan et al. Proposed Fan et al. Proposed Fan et al. Proposed Fan et al. Proposed

Power dissipation (μW) 4 (bit)

8 (bit)

18.45 12.28 455.8 286.02 1951 969.6 3211 1833

67.4 73.79 29.29 58.87 1336 1829 312.58 1307 5720 7848 2730 4307 8178 13070 3837 4373

% of power saved (average)

16 (bit) 36.73% 47.46% 49.23% 54.18%

there is a reduction in the propagation delay with the reduction of crosstalk, but the overhead delay should be aggressively considered. The proposed encoder has less overhead delay compared to Fan et al. [12]. This 90% propagation delay as tabulated in Table 17 is measured between the signal at the input of the encoder and at the output of the decoder (i.e., delay incurred by encoder, interconnects and the decoder). However, for some exceptional cases such as − − −↑↓, worst case propagation delay does not reduce. It can be clearly interpreted from the results that the proposed encoder adds lesser propagation delay when compared with the Fan et al.[12]. The delay is obtained for different frquencies such as 1 MHz, 100 MHz, 500 MHz, 1 GHz at different technolgy nodes. Encouragingly, it is observed that as the frequency of operation is increased there is almost negligible increase in propagation delay.

5.4. Total propagation delay 5.5. Power consumption with/without encoder The propagation delay is observed for worst case (↑↓↑↓↑) switching only. Propagation delay on a victim line effectively increases due to coupling parasitics. The encoder, which is primarily designed to reduce crosstalk, in fact introduces some delay of its own. This overhead delay, however, should be minimized. Although

Table 18 shows the results of power saved using encoder while simultaneously reducing crosstalk at a typical frequency of 80 MHz. The comparison of power consumption is observed in interconnect lines with and without encoder. The result shows that with the use of

Please cite this article as: B.K. Kaushik, et al., Bus encoder design for reduced crosstalk, power and area in coupled VLSI interconnects, Microelectron. J (2013), http://dx.doi.org/10.1016/j.mejo.2013.04.001i

B.K. Kaushik et al. / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎ Table 17 Comparisons of propagation delay of proposed method with FAN et al. [12] Method Frequency Technology (nm)

1 MHz

100 MHz

500 MHz

1 GHz

45 70 90 130 180 45 70 90 130 180 45 70 90 130 180 45 70 90 130 180

Propagation delay (ps) 8-bit

16-bit

Fan et al.

Proposed Fan et al.

Proposed Fan et al.

Proposed

156.8 279.6 304.7 397.4 569.3 156.6 279.1 303.1 395.7 560.2 155.4 279.1 300.7 164.5 237.7 155.4 258.1 208.7 497.2 442.7

57.5 82.4 102.6 149.5 302.4 56.2 84.7 102.9 150.6 315.9 56.2 83.7 102.6 150.6 290.5 55.7 88.2 102.3 148.0 314.1

77.8 110.5 123.7 242.3 318.6 76.9 114.5 168.6 242.3 345.6 77.6 120.6 168.3 242.3 340.6 77.2 118.7 170.0 235.8 318.7

125.5 145.4 187.0 302.4 324.7 124.7 148.4 182.0 320.6 368.6 123.6 145.4 184.2 314.4 345.3 125.7 145.4 188.7 311.9 315.7

196.5 334.3 382.1 513.1 731.8 196.7 334.3 382.1 523.8 730.2 196.5 334.3 380.6 460.4 580.5 196.5 304.3 317.8 532.9 492.8

Table 18 Comparisons of power dissipations with and without the use of encoder Technology (nm)

180 130 90 70 45

Power dissipation (μW) Without encoder

With encoder

812.80 517.00 418.50 247.90 191.90

109.20 53.73 39.33 22.14 14.69

45 nm technology that makes proposed designs extremely useful in current scenario. 6. Conclusion

4-bit

116.4 366.0 397.1 471.3 666.7 441.5 366.0 397.1 471.3 666.6 190.5 366.0 394.3 423.8 553.1 190.5 340.4 334.5 488.8 604.4

7

% Of power saved (average)

86.56% 89.61% 90.60% 91.07% 92.34%

encoder the worst case crosstalk are reduced which also results in the reduction of power consumption in interconnect as shown in Table 18. The observation from the results is that as the technology is scaled down, signal transmission in interconnects consumes more power. So, power aware encoders are in huge demand that would reduce power consumption drastically. The proposed design shows that up to 92% of power can be saved with encoder in

This paper demonstrated reduction of crosstalk, power dissipation and total propagation delay by using bus-invert method. The proposed design utilizes lesser number of transistors that effectively reduces chip area. The reduction in design size is achieved by logical simplification, without compromising any key performance factor. The results shows a reduction in area, power dissipation and propagation delay by 37.24, 68.76 and 56.78%, respectively compared to recently published encoder design. The coupling factor of the lines is drastically reduced to 276 from 789 that results to 65% reduction in crosstalk. Encouragingly, reductions in dominant Type-4 and Type-3 couplings are 92 and 76.8%, respectively. References [1] J. Cong, L. He, K.Y. Khoo, C.K. Koh, D.Z. Pan, Interconnect design for deep submicron ICs, in Proceedings of the International Conference on Computer-Aided Design, November 1997, pp. 478–485. [2] J.M. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits, second ed., Prentice Hall Publication, 2003. [3] B. Victor, K. Keutzer, Bus encoding to prevent crosstalk delay, in: Proceedings of the International Conference on Computer-Aided Design. 2001, pp. 57–63. [4] L. Benini, G.D. Micheli, E. Macii, D. Sciuto, C. Silviano, Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based system, in: Seventh Great Lakes Symposium on VLSI, Urbana, IL, USA, March 1997, pp. 77–82. [5] C.G. Lyuh, T. Kim, Low-power bus encoding with crosstalk delay elimination,, IET Comput. Digital Tech. 153 (2) (2006) 93–100. [6] R. Chandel, S. Sarkar, R.P. Agarwal, Repeater insertion in global interconnects in VLSI circuits, Microelectron. Int. 22 (1) (2005) 43–50. [7] M. Ghoneima, Y.I. Ismail, M.M. Khellah, J.W. Tschanz, V. De, Formal derivation of optimal active shielding for low-power on-chip buses, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (5) (2006) 821–836. [8] Z. Khan, T. Arslan, A.T. Erdogan, Low power system on chip bus encoding scheme with crosstalk noise reduction capability, IET Proc.—Comput. Digit. Tech. 153 (2) (2006) 101–108. [9] M.R. Stan, W.P. Burleson, Bus-invert coding for low-power I/O, IEEE Trans. VLSI Syst. 3 (1) (1995) 49–58. [10] Y. Shin, S.I. Chae, K. Choi, Partial bus-invert coding for power optimization of application-specific systems, IEEE Trans. VLSI Syst. 9 (2) (2001) 377–383. [11] P. Chen, D.A. Kirkpatrick, K Keutzer, Static Crosstalk-Noise Analysis—For Deep Sub-Micron Digital Designs, Springer Publications, 2004. [12] C.P. Fan, C.H Fang, Efficient RC low-power bus encoding methods for crosstalk reduction, Integr. VLSI J. 44 (1) (2011) 75–86. [13] Deepika Agarwal, Nagendra G, Babu B.K., Kaushik, S.K. Manhas, Design of low complexity encoder for capacitively coupled VLSI interconnects, IJCA Special Issue Evol. Networks Comput.Commun. 2 (2011) 45–49. [14] D. Agarwal, G.N. Babu, B.K. Kaushik, S.K. Manhas, Reduction of crosstalk in RC modeled interconnects with low power encoder,in: Emerging Trends in Networks and Computer Communications (ETNCC), 2011 International Conference on, 22–24 April 2011,pp. 115,120,. doi: 10.1109/ETNCC.2011.5958498.

Please cite this article as: B.K. Kaushik, et al., Bus encoder design for reduced crosstalk, power and area in coupled VLSI interconnects, Microelectron. J (2013), http://dx.doi.org/10.1016/j.mejo.2013.04.001i