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Determination of the stress level for voltage screen of integrated circuits
Microelectronics Reliability 50 (2010) 1210–1214
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Determination of the stress level for voltage screen of integrated circuits R.M. Kho *, A.J. Moonen, V.M. Girault, J. Bisschop, E.H.T. Olthof, S. Nath, Z.N. Liang NXP Semiconductors, Gerstweg 2, 6534 AE Nijmegen, The Netherlands
a r t i c l e
i n f o
Article history: Received 1 July 2010 Accepted 19 July 2010 Available online 21 August 2010
a b s t r a c t Voltage screen is a method to screen out products that suffer from defectivity related issues. A risk associated with voltage screen is that the applied voltage is too severe and damages the product. Most papers dealing with voltage screen determine the stress voltage by a general rule of thumb (focusing on one specific mechanism) without taking into account the particularities and the knowledge of the specific process. This paper describes a general approach to determine a safe level for voltage screening of products. In this approach, the onset of the wearout phase is not allowed to shift more than 1%. All the information needed to determine the voltage value is in general typically available from the process reliability tests performed as part of the process qualification. Ó 2010 Elsevier Ltd. All rights reserved.
1. Introduction Voltage screen (V-screen) is a method to filter out products that suffer from defectivity related issues. These weak products normally fail in the early failure (also known as infant mortality) period of the product’s life (see the bathtub curve; Fig. 1). At the onset of the useful life period, the population is better than at the onset of the early failure period. The idea behind burn-in and voltage screen is to advance the early failure period before products are delivered to the customer. In fact, it is as if the whole bathtub curve has been shifted to the left so that at time zero the useful life period starts. In effect, the weak products are screened out and normal product lifetimes are reduced slightly. An advantage of voltage screen above burn-in is of course that a much shorter stress period is possible. However, a too high level of voltage screen poses a risk of damaging the product. Most papers dealing with voltage screen determine the stress voltage by a general rule of thumb (focusing on one specific mechanism) without taking into account the particularities and the knowledge of the specific process. Some papers [1–3] state that the screen electrical field should not exceed 6 MV/cm on the oxide of the tested technology, without giving a clear reasoning. Sometimes, a screen value of 80% of the circuit breakdown is used [4]. Blish et al. [5] recommended a screen voltage equal to the circuit breakdown minus six times the standard deviation. A disadvantage of all these methods is that the effect of the V-screen on the reliability or remaining lifetime of the product is not known. An additional disadvantage of the 6 MV/cm criterion is that it cannot be used for the advanced technologies. Kuge [6] described how the
* Corresponding author. Tel.: +31 24 3534642; fax: +31 24 3533878. E-mail address: [email protected] (R.M. Kho). 0026-2714/$ - see front matter Ó 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2010.07.103
V-screen value could be determined, based on Time Dependent Dielectric Breakdown (TDDB) and Hot Carrier (HC) failure mechanisms. Under certain assumptions, expressions were derived for maximum V-screen depending on time and stress conditions. All the papers agree on the fact that the V-screen must capture as much as possible the extrinsically defective products, that is to say metal/poly residues shortening the inter-metal dielectric space, or particles increasing local via/contact resistance, particles in gate oxide, all what is relevant of defectivity. It is also understood that no thermally-only activated defect can be captured with this technique. In this paper, a general approach is proposed to determine a maximum allowed stress level for voltage screen. It makes use of the knowledge and lifetime models of various degradation mechanisms of the specific process. The proposed method has been verified for a 0.18 lm-CMOS technology. Two practical cases show the effectiveness of using this method to safely screen out weak products.
2. Method 2.1. Consumed lifetime by V-screen V-screen causes the bathtub curve to be shifted to the left, i.e., the wearout period will start earlier. The stress voltage and stress time determine the magnitude of the shift. Stress voltage and stress time should be: 1. high enough to filter out the weak parts causing early failures, but 2. not so high that the onset of the wearout phase is of concern during the useful life period of the product.
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failure rate λ
Early failure period
According to Eq. (1), the damage reached during V-screen equals:
Wearout period
Ds ¼ r s t s
in which ts is the stress (screen) duration and rs is the average damage rate under stress conditions. Under normal use conditions, this same amount of damage would be reached after a certain (longer) time (tc; Fig. 2):
Useful life period
// 0
//
ð3Þ
Ds ¼ r u t c
Time
Fig. 1. Bathtub curve.
The V-screen value should be as high as possible, as long as it is within the limits of the second requirement. Therefore the focus will be on the second requirement. Wearout is characterized by an increasing failure rate that is caused by an accumulation of damage in time. Because of the accumulation of damage, an increasing part of the population of products will reach the point of critical damage that results in failure. Note that in this concept, lifetime is defined as the time until a certain critical damage has been exceeded. Damage may be any function of time. When a certain damage D has been reached after a certain time t, the average rate of damage, r, is defined as:
r D=t
ð1Þ
If, for a certain degradation mechanism, a lifetime model is available as function of stress conditions, the average rate r as function of the stress condition can be found by substitution of the lifetime model in Eq. (1):
rðVÞ ¼ D=sðVÞ
ð2Þ
where s(V) is the lifetime model. For all degradation mechanisms the lifetime model is a strictly decreasing function of voltage. Time t (as well as modelled lifetime s(V)) is the time at a certain percentile, e.g., 0.1% with TDDB and 50% with hot carrier. As with all device reliability tests, we assume that the lifetime distribution and the shape parameter of this distribution do not change as a result of the stress. Only the scale parameter changes by stress. As a consequence, Eqs. (1) and (2) are valid for any specified percentile of the lifetime distribution. With V-screen, the damage until the critical damage (Dlim) is the sum of (see Fig. 2): 1. Damage (Ds) reached during the V-screen 2. Damage (Dlim Ds) that still can be created during the remaining life
ð4Þ
in which ru is the average damage rate under use conditions and tc is the apparent time to reach this stress damage under normal use conditions. So, it is the lifetime that is consumed by the V-screen. By equating Eqs. (3) and (4) and solving for tc, the time that would be consumed under normal use conditions to reach the damage caused by the V-screen is equal to:
tc ¼ ðrs =r u Þ t s ¼ ðrðV screen Þ=rðV use ÞÞ t s
Substitution of Eq. (2) shows that tc, the lifetime that is consumed by the V-screen, is equal to:
tc ¼ ðsðV use Þ=sðV screen ÞÞ ts
ð6Þ
This time can thus be calculated easily with the lifetime model
s(V) and the screen time ts. Note that the first part of the right-hand side of Eq. (6) is the common way to calculate a voltage acceleration factor: AFvoltage = s(Vuse)/s(Vscreen), so Eq. (6) can be read as: the lifetime that is consumed due to the V-screen equals the voltage acceleration factor multiplied by the screen time. 2.2. Maximum screen voltage A possible criterion for the maximum screen voltage is that the remaining lifetime should be at least the lifetime requirement. A disadvantage of this criterion is that if the lifetime requirement is amply met, a large part of the lifetime would be allowed to be consumed by the V-screen. This means that the properties of the product would be allowed to change significantly by the V-screen. This is not desirable. Our criterion of the maximum voltage for V-screen is that the V-screen is not allowed to consume more than 1% of the total lifetime:
tc =sðV use Þ 6 0:01
ð7Þ
Or, by substitution of Eq. (6) and rearrangement:
V screen 6 s1 ðts =0:01Þ
ð8Þ
Table 1 Degradation mechanisms with example models ([7] unless otherwise stated) and maximum V-screen.a Mechanism
Model s(V)
HC Takeda [8]
s ¼ AðTÞ eV ds LCeff
Maximum V-screen according to Eq. (8)
Damage Dlim
HC Woltjer [9] NBTIb
Ds Ds = rs ⋅ t s
Ds = ru ⋅ tc
NBTI
ts
Time
tc
Lifetime Fig. 2. Damage with and without V-screen (not to scale).
ð5Þ
TDDB E-model V-model TDDB 1/E model TDDB power law
B
pffiffiffiffiffi
B V ds
s ¼ AðTÞ e eC s¼ s¼
h
Dp AðTÞeaV g
h
Dp AðTÞV ag
i1=n
i1=n V
s ¼ AðTÞ ectox Gtox V
s ¼ AðTÞ e
s = A(T) Vn
Leff
B V screen 6 lnðts =0:01ÞlnðAðTÞÞClnðL
V screen 6
eff
Þ
B pffiffiffiffiffi lnðt s =0:01ÞlnðAðTÞÞC Leff
s =0:01Þ V screen 6 lnðDpÞlnðAðTÞÞnlnðt a
V screen 6
h
i1=a
Dp AðTÞðt s =0:01Þ
V screen 6 tcox ½lnðAðTÞÞ lnðts =0:01Þ Gt ox V screen 6 lnðts =0:01ÞlnðAðTÞÞ
V screen 6
t s =0:01 AðTÞ
1=n
a Parameter A(T) is a function of temperature, e.g., the Arrhenius model A(T) = A0 exp(Ea/(kT)). b Negative bias temperature instability.
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with ts is the screen time and s1 is the inverse of the lifetime model (i.e., the equation of the lifetime model solved for voltage resulting in an equation of voltage as function of time, temperature and geometries; Table 1).
not all voltages are well defined and in good designs is always prevented by a protection diode antiparallel to the emitter–base junction. 3.5. Procedure
3. Mechanisms and procedure 3.1. Lifetime models For each technology, a risk assessment will help to identify the important reliability failure mechanisms and consequently the appropriate model to be taken into account. All identified mechanisms should be taken into account; the exception to this approach is for digital circuits stressed under static conditions, in which hot carrier degradation is not of concern. Eq. (8) is then applied to different degradation mechanisms and models; see Table 1. There are other mechanisms that do not have a lifetime model based on voltage acceleration, but define boundary conditions. These are discussed in the next sections. 3.2. Latchup and ESD Except for silicon on insulator technologies, all CMOS processes are susceptible to latchup. The latchup is caused by parasitic bipolar components forming a thyristor. The V-screen should not exceed the voltage at which the low-ohmic state is entered, called the trigger voltage. ESD-protection circuits are placed on chips to prevent damage of an electrostatic discharge to the chip, by draining the charge through a parasitic path instead of through the chip. The voltage used during V-screen should not exceed the holding voltage: if it does, any spike causing the ESD-protection device to trigger will lead to a latched device. In many cases this is not a harmful situation, but the V-screen itself becomes ineffective as a filter to remove weak devices. 3.3. Electromigration
Steps to be followed for determination of the voltage for Vscreen are: 1. Determine the stress vectors for the desired defectivity coverage and determine the devices (kind of capacitors, transistors, etc.) that will be stressed in these vectors 2. Determine the lifetime models from these devices (see Section 3.1). These models should be available from the wafer level reliability qualification program. 3. Determine process variations and worst-case process geometries (e.g., minimum oxide thickness of capacitors, minimum channel lengths of CMOS transistors). 4. Lifetime for oxide breakdown (TDDB) depend on the area. Determine the maximum area of dielectric. 5. Determine the maximum allowed stress time from test throughput considerations. 6. Determine the temperature at which the V-screen will be done. 7. For each failure mechanism (Section 3.1) at worst-case process geometries (steps 3 and 4): determine the maximum allowable voltage according to Eq. (8) (for the stress time determined at step 5 and temperature determined at step 6). 8. Check whether the voltage does not exceed breakdown and latchup trigger voltages. 9. Determine the kind of screen (static or dynamic). With the dynamic screen, overshoot of voltage spikes due to transients should be taken into account. The overshoot depends on the circuit design. Only when the bias on all critical nodes of a product is well controlled, dynamic V-screen can be used safely. The advantage of dynamic stress is that more lines are stressed in current mode. Therefore, it may be expected that dynamic stress has a higher coverage of potential defects. With dynamic screen, the voltages of steps 7 and 8 should be reduced by the overshoot voltage. Static stress does not induce hot carrier degradation in digital circuits, so that hot carrier degradation can be ignored in this case. 10. The minimum of the determined V-screen voltages per failure mechanism (7 and 8) is the maximum stress voltage for V-screen. 11. Since V-screen is meant to be done on 100% of the products, it should be regarded as just another process step, which has to be qualified in the same way as other process steps are qualified. In particular, the regular High Temperature Operating Life (HTOL) stress should be carried out for the required sample size and stress time.
The failure mechanism in electromigration is an increase in resistance (up to the creation of voids) due to the high current densities in interconnect lines, mostly metal lines. During V-screen the voltage is elevated, not necessarily the currents (because electronic circuits are not resistors). Electromigration therefore is not a limiting failure mechanism in the first instance for the determination of the V-screen voltage, only as a secondary effect it comes into play. This is the case when, e.g., a break occurs, causing high currents. With V-screen these currents can be higher, causing secondary damage to the metal lines. If our reservation on non-increasing currents while increasing the supply voltage does not hold—this is strongly circuit dependent—electromigration does become a limiting failure mechanism and should be treated as such.
4. Validation
3.4. Junction breakdown
4.1. Verification of V-screen setting
The normal (diode) junction breakdown in CMOS is much higher than the V-screen voltage, so this causes no problem. Also low values for punch through and gated breakdown are not relevant in view of V-screen, as these leakage currents do not degrade the components. So, in CMOS, junction breakdown is not an issue during V-screen. For bipolar applications however, junction breakdown can become an issue, as these values are much lower. Additional parameter to consider is the reverse bias of the emitter–base junction. This however, can only occur during start-up of a product when
For our 0.18 lm-CMOS technology lifetime models were evaluated resulting in 11 potential V-screen voltages for a 0.1 s duration at 150 °C. The minimum was found for hot carrier beta degradation and was lower than the latchup trigger and ESD holding voltage. To check intrinsic lifetime of samples subjected to V-screen, 120 devices were put on lifetest (step 11 of the procedure): Stressed circuit blocks were digital signal processing (DSP) core (10 vectors), standard cell test block (10 vectors) and SRAM (2 vectors).
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Unit stress time = 100 ms; total time 2.4 s per device for Vscreen Stress sequence: the test program (a direct access test for the SRAM and standard scan test for the other blocks), then the V-screen stress during 0.1 s, and again the test program. This was followed by 2016 h HTOL at 150 °C. Result: all 120 devices survived the V-screen and the subsequent HTOL stress. No parameter shift was seen in the stressed blocks. 4.2. Effectiveness of the V-screen setting Dynamic V-screen was applied to DSP products, processed in the 0.18 lm-CMOS technology. Approximately half of the product area consists of RAM memory blocks. The RAM is the most dense part of the IC and therefore most susceptible to defects. The Dynamic V-screen was applied to these memory blocks by running the builtin self test (BIST) at elevated V-screen voltage. The stress might ‘kill’ or ‘heal’ defective products. Both of these are detected by running the BIST at operation voltage before and after the Vscreen and binned out to a fail bin to avoid shipping to customer. Two cases are presented to show the effectiveness of this voltage screening. 4.2.1. Case 1. Dynamic V-screen on known bad material One of the production batches has been hit by a production incident that was picked up by the standard production control limits. This batch has bad contacts leading to poor connection from metal to the active region inside the IC. The batch was scrapped and was used to show the added value of V-screen in finding defective products. Having the 5941 pass products of this batch retested with V-screen activated in the test program shows additional products failing (Table 2). If the effectiveness of the V-screen is defined as the fraction p of defective products that is filtered out by doing the V-screen once, Appendix A shows that the effectiveness is approximately 0.92. 4.2.2. Case 2. Dynamic V-screen in production Dynamic V-screen has been introduced in production. Line reject and 0 km reject count has been analyzed. The feedback time of these rejects is faster and more predictable (in time) compared to field rejects. Table 3 shows the effectiveness of V-screen in reducing the ppm-level of the memory related rejects. Since the introduction of V-screen, more than five million products have been delivered and no field rejects have been found so far. Based on the Poisson distribution of number of failures [10], zero failures out of 5 million gives 0.18 PPM as the 60% upper confidence bound of the failure fraction. Fig. 3 shows an example of a
Table 2 Number of fails after two successive V-screens. No. V-screen
Volume
# Fails
% Fail
1 2
5941 5854
87 7
1.46 0.12
Fig. 3. Particle at metal 2 shortening two cells found after V-screen.
defect found after V-screen. The field reject statistic is still building-up and will be reported in the near future with more detail. 5. Conclusion A general approach to determine a safe (maximum) voltage value for voltage screening of products has been described. In this approach, the selected screen voltage is the minimum of screen voltages per failure mechanism. Each of these has been determined so that the shift of the onset of the wearout period is not more than 1%. To be sure that in all cases the wearout period does not shift more than 1%, the procedure (steps 3 and 7) takes process variations and worst-case geometries into account. All the information needed to determine the V-screen value is in general already available from the process reliability tests done for the qualification. The approach has been shown to work well in practice. Acknowledgements Part of this work was supported by the Dutch government in the framework of the knowledge workers project ‘‘Resilience for automotive”. Thanks to Bob Brussaard for implementation of the V-screen and to Prof. Dr. F.G. Kuper for comments on an earlier version of the manuscript. Appendix A. Quantification of screen effectiveness A population consists of good and defective products. The numbers are denoted (1 f)N and fN respectively, where f is the initial fraction of defective products and N is the initial volume. The defective products are defined as products that have a defect and will fail within the lifetime of the product. The aim of a screen is to filter all these products. However, generally not all defective products are binned after one screen. At each screen a certain fraction p of the defective products is screened out. The effectiveness of the screen can be defined as this fraction p. If we would subject the whole population several times to a screen, we would get the relations of Table 4. Table 4 Number of fails after subsequent screens.
Table 3 PPM level before and after introduction of V-screen.
Before introduction of V-screen After introduction of V-screen
Volume
# Fails
PPM (60% conf.)
2 107 5 106
8 0
0.47 0.18
No. screen
# Fails
(remaining) Volume
0 1 2 3 n
– p fN p (1 p) fN p (1 p)2 fN p (1 p)n1 fN
(1 f)N + fN (1 f)N + (1 p) fN (1 f)N + (1 p)2 fN (1 f)N + (1 p)3 fN (1 f)N + (1 p)n fN
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The unknown parameters p and f can be found if two or more screens are done. With the data of Table 2 we get two equations with two unknowns:
p f 5941 ¼ 87
ð9aÞ
p ð1 pÞ f 5941 ¼ 7
ð9bÞ
which results in f = 0.01593 and p = 0.92 If more than two screens are done, the parameters can be found by (non-linear) least squares of the equation:
#fails ¼ p ð1 pÞn1 fN
ð10Þ
where the found number of fails is the dependent variable and n, the number of screens, is the independent variable. Screen effectiveness defined in this way can be interpreted as follows: if it is close to one, it indicates that the onset of the useful life period has been reached after the screen. If it is much less than one, the population after the screen still is in the early failure period with steep declining failure rate. In this case, the screen should be reconsidered (stress voltage or screen time are not high enough and a new compromise with higher consumed lifetime should be taken in consideration).
References [1] Chang JTY, McCluskey EJ. SHOrt Voltage Elevation (SHOVE) test for weak CMOS ICs. In: Proceedings 15th IEEE VLSI test symposium; 1997. p. 446–51. [2] Aitken RC. Test generation and fault modeling for stress testing. In: Proceedings of the international symposium on quality electronic design, ISQED; 2002. p. 95–9. [3] Khalil MA, Wey CL. Extreme voltage stress vector generation of analog CMOS ICs for gate oxide reliability enhancement. In: ITC international test conference; 2001. p. 348–57. [4] Bosworth J, Reinhart A. Sector guide for implementing high voltage stress test. Motorola, 68MWS00088B; 2001. [5] Blish RC, Black JC, Hui B, Prince DT. Technique for determining a prudent voltage stress to improve product quality and reliability. Microelectron Reliab 2000;40:1615–8. [6] Kuge HH. Determination of the maximum voltage for a product screening stress based on TDDB and HC measurements. IRW final report; 2003. p. 115–8. [7] JEP122E. Failure mechanisms and models for semiconductor devices. Jedec; 2009. [8] Takeda E, Suzuki N. An empirical model for device degradation due to hotcarrier injection. IEEE Electron Dev Lett 1983;EDL-4:111–3. [9] Woltjer R, Hamada A, Takeda E. Time dependence of p-MOSFET hot carrier degradation measured and interpreted consistently over ten orders of magnitude. IEEE Trans Electron Dev 1993;40:392–401. [10] Tobias PA, Trindade DC. Applied reliability. 2nd ed. Chapman & Hall; 1995.
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Determination of the stress level for voltage screen of integrated circuits R.M. Kho *, A.J. Moonen, V.M. Girault, J. Bisschop, E.H.T. Olthof, S. Nath, Z.N. Liang NXP Semiconductors, Gerstweg 2, 6534 AE Nijmegen, The Netherlands
a r t i c l e
i n f o
Article history: Received 1 July 2010 Accepted 19 July 2010 Available online 21 August 2010
a b s t r a c t Voltage screen is a method to screen out products that suffer from defectivity related issues. A risk associated with voltage screen is that the applied voltage is too severe and damages the product. Most papers dealing with voltage screen determine the stress voltage by a general rule of thumb (focusing on one specific mechanism) without taking into account the particularities and the knowledge of the specific process. This paper describes a general approach to determine a safe level for voltage screening of products. In this approach, the onset of the wearout phase is not allowed to shift more than 1%. All the information needed to determine the voltage value is in general typically available from the process reliability tests performed as part of the process qualification. Ó 2010 Elsevier Ltd. All rights reserved.
1. Introduction Voltage screen (V-screen) is a method to filter out products that suffer from defectivity related issues. These weak products normally fail in the early failure (also known as infant mortality) period of the product’s life (see the bathtub curve; Fig. 1). At the onset of the useful life period, the population is better than at the onset of the early failure period. The idea behind burn-in and voltage screen is to advance the early failure period before products are delivered to the customer. In fact, it is as if the whole bathtub curve has been shifted to the left so that at time zero the useful life period starts. In effect, the weak products are screened out and normal product lifetimes are reduced slightly. An advantage of voltage screen above burn-in is of course that a much shorter stress period is possible. However, a too high level of voltage screen poses a risk of damaging the product. Most papers dealing with voltage screen determine the stress voltage by a general rule of thumb (focusing on one specific mechanism) without taking into account the particularities and the knowledge of the specific process. Some papers [1–3] state that the screen electrical field should not exceed 6 MV/cm on the oxide of the tested technology, without giving a clear reasoning. Sometimes, a screen value of 80% of the circuit breakdown is used [4]. Blish et al. [5] recommended a screen voltage equal to the circuit breakdown minus six times the standard deviation. A disadvantage of all these methods is that the effect of the V-screen on the reliability or remaining lifetime of the product is not known. An additional disadvantage of the 6 MV/cm criterion is that it cannot be used for the advanced technologies. Kuge [6] described how the
* Corresponding author. Tel.: +31 24 3534642; fax: +31 24 3533878. E-mail address: [email protected] (R.M. Kho). 0026-2714/$ - see front matter Ó 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2010.07.103
V-screen value could be determined, based on Time Dependent Dielectric Breakdown (TDDB) and Hot Carrier (HC) failure mechanisms. Under certain assumptions, expressions were derived for maximum V-screen depending on time and stress conditions. All the papers agree on the fact that the V-screen must capture as much as possible the extrinsically defective products, that is to say metal/poly residues shortening the inter-metal dielectric space, or particles increasing local via/contact resistance, particles in gate oxide, all what is relevant of defectivity. It is also understood that no thermally-only activated defect can be captured with this technique. In this paper, a general approach is proposed to determine a maximum allowed stress level for voltage screen. It makes use of the knowledge and lifetime models of various degradation mechanisms of the specific process. The proposed method has been verified for a 0.18 lm-CMOS technology. Two practical cases show the effectiveness of using this method to safely screen out weak products.
2. Method 2.1. Consumed lifetime by V-screen V-screen causes the bathtub curve to be shifted to the left, i.e., the wearout period will start earlier. The stress voltage and stress time determine the magnitude of the shift. Stress voltage and stress time should be: 1. high enough to filter out the weak parts causing early failures, but 2. not so high that the onset of the wearout phase is of concern during the useful life period of the product.
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failure rate λ
Early failure period
According to Eq. (1), the damage reached during V-screen equals:
Wearout period
Ds ¼ r s t s
in which ts is the stress (screen) duration and rs is the average damage rate under stress conditions. Under normal use conditions, this same amount of damage would be reached after a certain (longer) time (tc; Fig. 2):
Useful life period
// 0
//
ð3Þ
Ds ¼ r u t c
Time
Fig. 1. Bathtub curve.
The V-screen value should be as high as possible, as long as it is within the limits of the second requirement. Therefore the focus will be on the second requirement. Wearout is characterized by an increasing failure rate that is caused by an accumulation of damage in time. Because of the accumulation of damage, an increasing part of the population of products will reach the point of critical damage that results in failure. Note that in this concept, lifetime is defined as the time until a certain critical damage has been exceeded. Damage may be any function of time. When a certain damage D has been reached after a certain time t, the average rate of damage, r, is defined as:
r D=t
ð1Þ
If, for a certain degradation mechanism, a lifetime model is available as function of stress conditions, the average rate r as function of the stress condition can be found by substitution of the lifetime model in Eq. (1):
rðVÞ ¼ D=sðVÞ
ð2Þ
where s(V) is the lifetime model. For all degradation mechanisms the lifetime model is a strictly decreasing function of voltage. Time t (as well as modelled lifetime s(V)) is the time at a certain percentile, e.g., 0.1% with TDDB and 50% with hot carrier. As with all device reliability tests, we assume that the lifetime distribution and the shape parameter of this distribution do not change as a result of the stress. Only the scale parameter changes by stress. As a consequence, Eqs. (1) and (2) are valid for any specified percentile of the lifetime distribution. With V-screen, the damage until the critical damage (Dlim) is the sum of (see Fig. 2): 1. Damage (Ds) reached during the V-screen 2. Damage (Dlim Ds) that still can be created during the remaining life
ð4Þ
in which ru is the average damage rate under use conditions and tc is the apparent time to reach this stress damage under normal use conditions. So, it is the lifetime that is consumed by the V-screen. By equating Eqs. (3) and (4) and solving for tc, the time that would be consumed under normal use conditions to reach the damage caused by the V-screen is equal to:
tc ¼ ðrs =r u Þ t s ¼ ðrðV screen Þ=rðV use ÞÞ t s
Substitution of Eq. (2) shows that tc, the lifetime that is consumed by the V-screen, is equal to:
tc ¼ ðsðV use Þ=sðV screen ÞÞ ts
ð6Þ
This time can thus be calculated easily with the lifetime model
s(V) and the screen time ts. Note that the first part of the right-hand side of Eq. (6) is the common way to calculate a voltage acceleration factor: AFvoltage = s(Vuse)/s(Vscreen), so Eq. (6) can be read as: the lifetime that is consumed due to the V-screen equals the voltage acceleration factor multiplied by the screen time. 2.2. Maximum screen voltage A possible criterion for the maximum screen voltage is that the remaining lifetime should be at least the lifetime requirement. A disadvantage of this criterion is that if the lifetime requirement is amply met, a large part of the lifetime would be allowed to be consumed by the V-screen. This means that the properties of the product would be allowed to change significantly by the V-screen. This is not desirable. Our criterion of the maximum voltage for V-screen is that the V-screen is not allowed to consume more than 1% of the total lifetime:
tc =sðV use Þ 6 0:01
ð7Þ
Or, by substitution of Eq. (6) and rearrangement:
V screen 6 s1 ðts =0:01Þ
ð8Þ
Table 1 Degradation mechanisms with example models ([7] unless otherwise stated) and maximum V-screen.a Mechanism
Model s(V)
HC Takeda [8]
s ¼ AðTÞ eV ds LCeff
Maximum V-screen according to Eq. (8)
Damage Dlim
HC Woltjer [9] NBTIb
Ds Ds = rs ⋅ t s
Ds = ru ⋅ tc
NBTI
ts
Time
tc
Lifetime Fig. 2. Damage with and without V-screen (not to scale).
ð5Þ
TDDB E-model V-model TDDB 1/E model TDDB power law
B
pffiffiffiffiffi
B V ds
s ¼ AðTÞ e eC s¼ s¼
h
Dp AðTÞeaV g
h
Dp AðTÞV ag
i1=n
i1=n V
s ¼ AðTÞ ectox Gtox V
s ¼ AðTÞ e
s = A(T) Vn
Leff
B V screen 6 lnðts =0:01ÞlnðAðTÞÞClnðL
V screen 6
eff
Þ
B pffiffiffiffiffi lnðt s =0:01ÞlnðAðTÞÞC Leff
s =0:01Þ V screen 6 lnðDpÞlnðAðTÞÞnlnðt a
V screen 6
h
i1=a
Dp AðTÞðt s =0:01Þ
V screen 6 tcox ½lnðAðTÞÞ lnðts =0:01Þ Gt ox V screen 6 lnðts =0:01ÞlnðAðTÞÞ
V screen 6
t s =0:01 AðTÞ
1=n
a Parameter A(T) is a function of temperature, e.g., the Arrhenius model A(T) = A0 exp(Ea/(kT)). b Negative bias temperature instability.
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with ts is the screen time and s1 is the inverse of the lifetime model (i.e., the equation of the lifetime model solved for voltage resulting in an equation of voltage as function of time, temperature and geometries; Table 1).
not all voltages are well defined and in good designs is always prevented by a protection diode antiparallel to the emitter–base junction. 3.5. Procedure
3. Mechanisms and procedure 3.1. Lifetime models For each technology, a risk assessment will help to identify the important reliability failure mechanisms and consequently the appropriate model to be taken into account. All identified mechanisms should be taken into account; the exception to this approach is for digital circuits stressed under static conditions, in which hot carrier degradation is not of concern. Eq. (8) is then applied to different degradation mechanisms and models; see Table 1. There are other mechanisms that do not have a lifetime model based on voltage acceleration, but define boundary conditions. These are discussed in the next sections. 3.2. Latchup and ESD Except for silicon on insulator technologies, all CMOS processes are susceptible to latchup. The latchup is caused by parasitic bipolar components forming a thyristor. The V-screen should not exceed the voltage at which the low-ohmic state is entered, called the trigger voltage. ESD-protection circuits are placed on chips to prevent damage of an electrostatic discharge to the chip, by draining the charge through a parasitic path instead of through the chip. The voltage used during V-screen should not exceed the holding voltage: if it does, any spike causing the ESD-protection device to trigger will lead to a latched device. In many cases this is not a harmful situation, but the V-screen itself becomes ineffective as a filter to remove weak devices. 3.3. Electromigration
Steps to be followed for determination of the voltage for Vscreen are: 1. Determine the stress vectors for the desired defectivity coverage and determine the devices (kind of capacitors, transistors, etc.) that will be stressed in these vectors 2. Determine the lifetime models from these devices (see Section 3.1). These models should be available from the wafer level reliability qualification program. 3. Determine process variations and worst-case process geometries (e.g., minimum oxide thickness of capacitors, minimum channel lengths of CMOS transistors). 4. Lifetime for oxide breakdown (TDDB) depend on the area. Determine the maximum area of dielectric. 5. Determine the maximum allowed stress time from test throughput considerations. 6. Determine the temperature at which the V-screen will be done. 7. For each failure mechanism (Section 3.1) at worst-case process geometries (steps 3 and 4): determine the maximum allowable voltage according to Eq. (8) (for the stress time determined at step 5 and temperature determined at step 6). 8. Check whether the voltage does not exceed breakdown and latchup trigger voltages. 9. Determine the kind of screen (static or dynamic). With the dynamic screen, overshoot of voltage spikes due to transients should be taken into account. The overshoot depends on the circuit design. Only when the bias on all critical nodes of a product is well controlled, dynamic V-screen can be used safely. The advantage of dynamic stress is that more lines are stressed in current mode. Therefore, it may be expected that dynamic stress has a higher coverage of potential defects. With dynamic screen, the voltages of steps 7 and 8 should be reduced by the overshoot voltage. Static stress does not induce hot carrier degradation in digital circuits, so that hot carrier degradation can be ignored in this case. 10. The minimum of the determined V-screen voltages per failure mechanism (7 and 8) is the maximum stress voltage for V-screen. 11. Since V-screen is meant to be done on 100% of the products, it should be regarded as just another process step, which has to be qualified in the same way as other process steps are qualified. In particular, the regular High Temperature Operating Life (HTOL) stress should be carried out for the required sample size and stress time.
The failure mechanism in electromigration is an increase in resistance (up to the creation of voids) due to the high current densities in interconnect lines, mostly metal lines. During V-screen the voltage is elevated, not necessarily the currents (because electronic circuits are not resistors). Electromigration therefore is not a limiting failure mechanism in the first instance for the determination of the V-screen voltage, only as a secondary effect it comes into play. This is the case when, e.g., a break occurs, causing high currents. With V-screen these currents can be higher, causing secondary damage to the metal lines. If our reservation on non-increasing currents while increasing the supply voltage does not hold—this is strongly circuit dependent—electromigration does become a limiting failure mechanism and should be treated as such.
4. Validation
3.4. Junction breakdown
4.1. Verification of V-screen setting
The normal (diode) junction breakdown in CMOS is much higher than the V-screen voltage, so this causes no problem. Also low values for punch through and gated breakdown are not relevant in view of V-screen, as these leakage currents do not degrade the components. So, in CMOS, junction breakdown is not an issue during V-screen. For bipolar applications however, junction breakdown can become an issue, as these values are much lower. Additional parameter to consider is the reverse bias of the emitter–base junction. This however, can only occur during start-up of a product when
For our 0.18 lm-CMOS technology lifetime models were evaluated resulting in 11 potential V-screen voltages for a 0.1 s duration at 150 °C. The minimum was found for hot carrier beta degradation and was lower than the latchup trigger and ESD holding voltage. To check intrinsic lifetime of samples subjected to V-screen, 120 devices were put on lifetest (step 11 of the procedure): Stressed circuit blocks were digital signal processing (DSP) core (10 vectors), standard cell test block (10 vectors) and SRAM (2 vectors).
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Unit stress time = 100 ms; total time 2.4 s per device for Vscreen Stress sequence: the test program (a direct access test for the SRAM and standard scan test for the other blocks), then the V-screen stress during 0.1 s, and again the test program. This was followed by 2016 h HTOL at 150 °C. Result: all 120 devices survived the V-screen and the subsequent HTOL stress. No parameter shift was seen in the stressed blocks. 4.2. Effectiveness of the V-screen setting Dynamic V-screen was applied to DSP products, processed in the 0.18 lm-CMOS technology. Approximately half of the product area consists of RAM memory blocks. The RAM is the most dense part of the IC and therefore most susceptible to defects. The Dynamic V-screen was applied to these memory blocks by running the builtin self test (BIST) at elevated V-screen voltage. The stress might ‘kill’ or ‘heal’ defective products. Both of these are detected by running the BIST at operation voltage before and after the Vscreen and binned out to a fail bin to avoid shipping to customer. Two cases are presented to show the effectiveness of this voltage screening. 4.2.1. Case 1. Dynamic V-screen on known bad material One of the production batches has been hit by a production incident that was picked up by the standard production control limits. This batch has bad contacts leading to poor connection from metal to the active region inside the IC. The batch was scrapped and was used to show the added value of V-screen in finding defective products. Having the 5941 pass products of this batch retested with V-screen activated in the test program shows additional products failing (Table 2). If the effectiveness of the V-screen is defined as the fraction p of defective products that is filtered out by doing the V-screen once, Appendix A shows that the effectiveness is approximately 0.92. 4.2.2. Case 2. Dynamic V-screen in production Dynamic V-screen has been introduced in production. Line reject and 0 km reject count has been analyzed. The feedback time of these rejects is faster and more predictable (in time) compared to field rejects. Table 3 shows the effectiveness of V-screen in reducing the ppm-level of the memory related rejects. Since the introduction of V-screen, more than five million products have been delivered and no field rejects have been found so far. Based on the Poisson distribution of number of failures [10], zero failures out of 5 million gives 0.18 PPM as the 60% upper confidence bound of the failure fraction. Fig. 3 shows an example of a
Table 2 Number of fails after two successive V-screens. No. V-screen
Volume
# Fails
% Fail
1 2
5941 5854
87 7
1.46 0.12
Fig. 3. Particle at metal 2 shortening two cells found after V-screen.
defect found after V-screen. The field reject statistic is still building-up and will be reported in the near future with more detail. 5. Conclusion A general approach to determine a safe (maximum) voltage value for voltage screening of products has been described. In this approach, the selected screen voltage is the minimum of screen voltages per failure mechanism. Each of these has been determined so that the shift of the onset of the wearout period is not more than 1%. To be sure that in all cases the wearout period does not shift more than 1%, the procedure (steps 3 and 7) takes process variations and worst-case geometries into account. All the information needed to determine the V-screen value is in general already available from the process reliability tests done for the qualification. The approach has been shown to work well in practice. Acknowledgements Part of this work was supported by the Dutch government in the framework of the knowledge workers project ‘‘Resilience for automotive”. Thanks to Bob Brussaard for implementation of the V-screen and to Prof. Dr. F.G. Kuper for comments on an earlier version of the manuscript. Appendix A. Quantification of screen effectiveness A population consists of good and defective products. The numbers are denoted (1 f)N and fN respectively, where f is the initial fraction of defective products and N is the initial volume. The defective products are defined as products that have a defect and will fail within the lifetime of the product. The aim of a screen is to filter all these products. However, generally not all defective products are binned after one screen. At each screen a certain fraction p of the defective products is screened out. The effectiveness of the screen can be defined as this fraction p. If we would subject the whole population several times to a screen, we would get the relations of Table 4. Table 4 Number of fails after subsequent screens.
Table 3 PPM level before and after introduction of V-screen.
Before introduction of V-screen After introduction of V-screen
Volume
# Fails
PPM (60% conf.)
2 107 5 106
8 0
0.47 0.18
No. screen
# Fails
(remaining) Volume
0 1 2 3 n
– p fN p (1 p) fN p (1 p)2 fN p (1 p)n1 fN
(1 f)N + fN (1 f)N + (1 p) fN (1 f)N + (1 p)2 fN (1 f)N + (1 p)3 fN (1 f)N + (1 p)n fN
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The unknown parameters p and f can be found if two or more screens are done. With the data of Table 2 we get two equations with two unknowns:
p f 5941 ¼ 87
ð9aÞ
p ð1 pÞ f 5941 ¼ 7
ð9bÞ
which results in f = 0.01593 and p = 0.92 If more than two screens are done, the parameters can be found by (non-linear) least squares of the equation:
#fails ¼ p ð1 pÞn1 fN
ð10Þ
where the found number of fails is the dependent variable and n, the number of screens, is the independent variable. Screen effectiveness defined in this way can be interpreted as follows: if it is close to one, it indicates that the onset of the useful life period has been reached after the screen. If it is much less than one, the population after the screen still is in the early failure period with steep declining failure rate. In this case, the screen should be reconsidered (stress voltage or screen time are not high enough and a new compromise with higher consumed lifetime should be taken in consideration).
References [1] Chang JTY, McCluskey EJ. SHOrt Voltage Elevation (SHOVE) test for weak CMOS ICs. In: Proceedings 15th IEEE VLSI test symposium; 1997. p. 446–51. [2] Aitken RC. Test generation and fault modeling for stress testing. In: Proceedings of the international symposium on quality electronic design, ISQED; 2002. p. 95–9. [3] Khalil MA, Wey CL. Extreme voltage stress vector generation of analog CMOS ICs for gate oxide reliability enhancement. In: ITC international test conference; 2001. p. 348–57. [4] Bosworth J, Reinhart A. Sector guide for implementing high voltage stress test. Motorola, 68MWS00088B; 2001. [5] Blish RC, Black JC, Hui B, Prince DT. Technique for determining a prudent voltage stress to improve product quality and reliability. Microelectron Reliab 2000;40:1615–8. [6] Kuge HH. Determination of the maximum voltage for a product screening stress based on TDDB and HC measurements. IRW final report; 2003. p. 115–8. [7] JEP122E. Failure mechanisms and models for semiconductor devices. Jedec; 2009. [8] Takeda E, Suzuki N. An empirical model for device degradation due to hotcarrier injection. IEEE Electron Dev Lett 1983;EDL-4:111–3. [9] Woltjer R, Hamada A, Takeda E. Time dependence of p-MOSFET hot carrier degradation measured and interpreted consistently over ten orders of magnitude. IEEE Trans Electron Dev 1993;40:392–401. [10] Tobias PA, Trindade DC. Applied reliability. 2nd ed. Chapman & Hall; 1995.