- Email: [email protected]
Dielectric isolation techniques for integrated circuits
Microelectro~lics and Reliability, Vol. 15. pp, 113 to 122. Pergamon Press, 1976. Printed in Great Britain
DIELECTRIC ISOLATION TECHNIQUES FOR INTEGRATED CIRCUITS J. R. BOSNELL Royal Radar Establishment, Malvern, Worcs, U.K. Abstract--There has been an increasing interest in producing dielectrically isolated integrated circuits over the past five years for both bipolar and MOS. This impetus stems from the potential of such a technique to increase the operational speed of the circuit, particularly CMOS by reduction of the stray capacitance and a need to reduce the susceptibility of monolithic circuits to photocurrents generated by radiation in space and military environments. In general, early methods for producing dielectrically isolated circuits involved relatively costly lapping and polishing techniques which were generally low yield processes or the development of a completely new process e.g. silicon on sapphire. Recently, preferential anisotropic silicon etchants which may eliminate the mechanical process steps have been announced, as well as the possibility of ion implantation of heavy doses of nitrogen or oxygen at relatively high energies to produce the buried dielectric layer. These new processes will be compared with more traditional methods.
!. I N T R O D U C T I O N
One of the major advantages of the monolithic integrated circuit is the increased reliability stemming from the on-chip thin film interconnection system of a large number of building blocks; transistors, diodes, capacitors and resistors. However, the resistivity of the basic silicon, from which these blocks are made, is generally low so that techniques must be devised to electrically isolate adjacent blocks. Traditionally this has been achieved by surrounding each elementary circuit by a reverse biased p-n junction as the sidewall isolation, using the substrate to define the
bottom isolation (Fig. la). Unfortunately, this relatively simple and inexpensive technique introduces unwanted capacitances, which are temperature and voltage sensitive and limit the operational speed of the circuit. Furthermore, care must bctakcn to avoid the formation of four layer, pnpn. parasitic de\ices in the design of the chip. This is especially troublesome in a radiation environment where large photocurrents can be created by transient ionizing radiations [1]. The breakdown voltage is inversely proportional to the doping level of the isolation material and must therefore be carefully controlled to avoid
S. n n
n
n
3.
~J? ~ ÷ j
n-
FIG. I(o)
6.
J~ n
"1" DIFFUSION
[]
OXIDE
[]
POLYSILICON
3 L=,
FIG. I (b)
Fig. ta. Junction isolation process (schematic). lb. Dielectric isolation process using a polysilicon handle (schematic). la. l p- Substrate, n + buried layer, n- epitaxial layer; 2 Isolation pattern defined; 3 p+ isolation deposition; 4 p+ isolation diffusion. lb. 1 Surface preparation; 2n ÷ deposition and masking oxide; 3 isolation pattern and most etch; 4 dielectric oxide grown; 5 polysilicon deposition; 6 blacklap and polish; 7 finished slice. 113
114
J.R. Bosx~u
high leakage currents. From the point of view of bipolar memories an additional problem is the severe reduction in packing density due to lateral diffusion of the isolation walls. Manufacturers, endeavouring t o o v e r c o m e these limitations of junction isolation, Jl, have introduced a variety of schemes loosely termed dielectric isolation, DI. Fig. lb illustrates one of these processes. In this case a polysilicon handle is used to enable a lapping and polishing operation to be performed• The result is that each device "'tub" is completely surrounded by silicon dioxide, hence, dielectrically isolated. This technique [2] is the oldest of the many variants and probably the most widely used until recently. Simplistically, the aim of all the various approaches is to achieve at least the same pertbrmance as an equivalent assembly of discrete components. Clearly, however, there is a delicate balar~ce between the performance advantage gained by dielectric isolation techniques and the additional cost incurred by these processes since most of the variants of DI involve a greater number of process steps than Jl (in some cases as many as 30 more) with the resultant yield loss and cost increase. M a n y of the early dielectric isolation schemes have been abandoned. The early approaches are well illustrated in Christiansen's review [3], and will be listed here only briefly. 1.1 Silicon carhide Added to the oxide growth steps illustrated in Fig. l b is a silicon carbide growth stage. This facilitates the removal of excess n-type silicon and because of its hardness acts as a lap stop during the lapping/" polishing phase. However, the process requires additional forming stages and more lapping to remove the carbide•
1.5 Beam lead This idea exploits the Bell System beam lead technology. The beam leads torm both electrical and mechanical connections between several discrete circuit elements. High frequency operation and a freedom from hermetic sealing are advantages of thc process. However, it is a relatively complex series of steps. 1.6 Air oxide Polysilicon is again used, but this time as a supporting substrate retained in the finished device. Molybdenum gold metallization is used in the interconnection pattern, the gold being built up in certain areas by electroplating. The silicon between devices is selectively etched, leaving air isolation between them, with oxide on the polysilicon, thus air oxide isolation. The metallization and etching steps are relatively complicated. 1.7 Decal [4] Individual devices on the wafer are produced in the normal manner. The metallization, however, has to withstand high temperature processing later and is therefore a refractory metal like titanium. The wafer is bonded metallization side down to glass direct at 800°C. Hence the term decal; to transfer patterns to a surface. Isolation between elemental blocks is then achieved by lapping away excess silicon and selective etching, using the glass as a carrier. If necessary other dielectrics may be used to fill the spaces between devices. The major advantage of this technique is that again there is no need for device protection steps. However, the high temperature bonding phase is a problem.
1.2 Mesa
1.8 Chess board
in this technique, the circuit blocks are diffused etched, and inter-connected in the normal way. A substrate is then joined to the slice using a screen printable or spin-on glass. The back of circuit as selectively etched to provide isolation. Although this isolation technique may make encapsulation unnecessary, lapping as well as etching may be required to remove excess silicon.
Several schemes fall in this category. (i) Form mesa devices, hot press glass between mesas, lap excess silicon from the back and metallize the resultant wafer. However, expansion matched glasses are difficult to obtain which do not act as diffusion sources. (ii) Alternate layers of silicon and insulator are bonded together and sawn into slices. Insulators such as Pyroceram have been postulated for the sandwich. Diffuse and metallize the resultant chess board. Again expansion matching to produce bow-free slices is a problem.
1.3 Handle wal'er The so-called "'handle wafer" technique has many similarities with the mesa approach. Here mesas containing the devices are etched before a glass coated silicon handle is fused to the mesas, the "handle wafer". Lapping then removes excess silicon and the voids between mesas are backfilled with glass. The "handle" is then etched away. 1.4 Ceramic This approach is essentially an amalgam of 1.2 and 1.3. The handle is now a glass carrier which has to be removed at the end of the process. A ceramic cement is used to fill the voids.
2. M A J O R PROCESSES
2.1 Polysilicon The traditional dielectric isolation technique employing polysilicon is illustrated in Fig. lb. An obvious disadvantage of the process can be seen from the figure; the increase in the number of process steps over junction isolation. A technical difficulty not explicit in the figure is the bowing of the slice which
Cubic (diamond) Cubic (diamond) Cubic (zinc blende) Rhombohedral
Cubic
Hexagonal
Hexagonal Cubic Rhombohedral <435°C Cubic > 4 3 5 ° C Tetragonal Cubic
Si Ge GaAs A1203
MgO.XA1203
~-SiO2
BeO ThO2 LaA103
ZrSiO4 MgO
Crystal Structure
Material
a a a a a a
= = = = =
a = 8.11 a = 8.02 a = 7.98 5,39
12.97
2.7, c = 4.39 5.60 3.79, c = 90°5 3.81 5.58, c, - 5.93 4.20
a = 5.431 a = 5.657 a = 5.653 a - 4.7, c = ref. hex. cell MgO.AI20 3 MgO.2A1203 MgO.3A1203 a = 4.9, c =
Lattice P a r a m e t e r (A)
239(~2550 2850
2530 3300 2000 2200
2130 2080 2000 1710
1430 958 1280 2040
Melting Point (°C)
5.5 ((Yl200~C) 14.4 (20-1200'~C)
8.1 (5(~1000°C) 18.0 ((~1000°C) ( ± r to C axis) 9.0 (0-1200°C) 9.4 (0.1200°C) 12.0 (25 65ff'C)
8.8 (2(~1200°C)
3.9 (50 1000 C) 5.658 6.68 9.5 (2(~2000'C)
Coefficient of Linear Expansion ( 1 0 - s / ° C - ~ )
Single crystal platelets Arc-melted single crystals
H y d r o t h e r m a l l y grown single crystal Flux grown crystals Single crystal platelets Single crystal platelets
Flux, Verneuil & Czochralski g r o w n single crystals Flux, Verneuil & Czochralski g r o w n single crystals
Single Crystal Availability
Table 1. Possible single crystal insulators as substrates for epitaxial g r o w t h of semiconductors c o m p a r e d with the physical properties of the m o s t c o m m o n semiconductors
ta~
.E
t~
116
.I.R. Bos,,ll I
ensues from the difference the expansion coefficients of SiO: and polysilicon (see Table I). This can cause a catastrophic yield reduction since the outer areas of the slice will generally lap first. Some teclmologies try to overcome this by alternate SiO_, and polysilicon growth the restlltant sandwich having almost compensated stresses, or the lapping tool is suitably shaped. The technology is capable of extension to produce both p and n-type tubs, sometimes called the complementary dielectric isolation process. Instead of starting with an n-type substrate as in Fig. lb, />type is used, followed by the p diffusions. After oxide growth, the slice is selectively etched and backfilled epitaxially with n-type silicon. Hence complementary n/m and Imp transistors can be manufactured. An example of the use of the technology has been reported recently by Huffman and Daniels [5] for the production of a low power complementary, operational amplifier. Several tradenames cover this process e.g. single poly and double poly used by TI [6]. Excessive leakage currents can arise in the single poly process since the n-type material can be subjected to damage at the backtap and polish stage. The double poly process introduces a second poly-silicon deposition stage protecting the n-type material from mechanical or chemical damage. However, it can mean that during the dielectric isolation production junctions are subjected to high temperatures for long times. This means that concentration prptiles are severely degraded. Polysilicon has recently been employed m either collector current channels [7] or as the actual isolation material [8]. Both sets of workers have built their ideas on Kobayashi's [9] use of polysilicon in the form of a vertical plug to provide a high diffusivity 110 to 20 times single crystal silicon) means of increasing the distribution of dopant to the lower reaches of the p n isolation. However. the largest use of polysilicon in DI processing is rapidly becoming the filling of l'-groove isolation processes to provide a fiat surface for subsequent memllizafion. 2.2 Partial i.solation techniques In 1968 Bell Labs, using thin p-type epitaxial base layers announced a process which achieved isolation by using the collector contact diffusion [10] (Fig. 2a).
CDI FIG. 2 I a )
OXIM FIG. 21b|
Fig. 2a. CDI process transistor compared with the OXIM version Fig. 2b (hatchings as Fig. I).
One disadvantage of this basic ( ' D I scheme is tile low collector-base breakdown \ohage. Oxide isolalion has been used to eliminate this by' replacing that portion of the extrinsic base region between emitter and the isolation with oxide (Fig. 2b). This process has become known as OXIM (Oxide Isolated Monolith [11]. It will be seen that there is a useful reduction in real estate on the chip. Furthermore. lhe smaller collector junction area. as well as the elimination of the sidewall portion of the base-collector junction, means a greatl 3 reduced collector capacitance and collector-substrate capacitance. Powerdehtv products on experimental TTL gates in this process are reported to be about 5 p J. 15 ns delays at I m W ) at least live times less thatl CDI circuits with similar design rules. Similar partial isolation is achieved by variations on thc OXIM theme. 2.2. I Isophmar [I 2] (F~Hrchild). Again. the substrate is not isolated but isoplanar II achieves an area reduction of over 50':, on conventional processing. Furthermore. a maximum Irequenc.,, of operation greater than 5 G H z has been reported compared with less than 3 G H z for more usual technologies. Both TTL and ECL RAMs (up to 1024 bits) have been announced in this technolog3, with the delay-power product of the ECL variety being 23 p J. for a cell size of 10 mil e. It should be emphasized here that the process was originally described by Marandi (SGS ATES. Milan) as a planar M O S technology. Because of the gradual transition [Veto field oxide to gate oxide at the source-drain regions in this process the uniformity of photoresist coverage is increased giving improved yield figures. Accelerated stress tests indicate a failure rate of 0.(X)lY",; per 10(X) hours at I(10 C for the bipolar isoplanar technolog,,. 2.2.2 LOCOS [13] (Philip.s). The acronym LOCOS stands for Local oxidation of .silicon. The process is very similar to those above and will not be described in detail. Keel and Appels [I 3] point out the problem of "'bird head" which lifts the nitride masking especially if lateral oxidation has occurred to lolm a 'bird beak". However, a major part of the beak can bc removcd by etching or b,,. careful manipulation of the nitride stage. L O C O S has been applied to C M O S manulacturc the resultant acronym being LOCMOS, the process steps being shown in Fig. 3 (after Brandt el al [14]). The application of LOCOS to C M O S achieves a saving in lateral dimensions of a factor of two and a speed increase from a factor of at least 3, enabling shift registers to operate at 10MHz clock rates from a 5V supply on half the real estate of a conventional circuit. 2.2.3 Polyl)hmar[15] (ftarris). Thc process steps are illustrated in Fig. 4. Polysilicon is used to fill the etched moats and is then lapped to provide a fiat metallization surlhcc. The most is formed by an anisetropic etch in (100) direction. Wc shall return to anisotropic etchants later. The Itamess of the resultant surface is reported to simplif3, multi-level metalization schemes. A in~.tior advantage of the process is the
Dielectric Isolation Techniques
117
OXIDE
i
N
[
~
NITRIDE
i
~
P -s~
n-
P+-Si POLYCRYSTALL~NE Si
v/1/.
N*- Si
i
N
2
J
gml
Ai
p-
i
i
N
i
3
5
6
7
1
J
Fig. 3. 1 LOCOS oxide is grown, and n-type Si is coated with silicon nitride; 2 Boron diffusions through windows in the Si3N4 are used to form the p-type regions of the N-channel transistors; 3 Remove the Si3N4, from a thin oxide layer and the deposit polysilicon. Gates and interconnections are etched in this layer; 4 Sources and drains, p+ diffusions for the P-channel transitor are formed by boron diffusion on the right hand side (gates and LOCOS oxide serve as masks); 5 Sources and drains, n +, formed by phosphous diffusions in p-type regions (left); 6 SiO2 pyrolitically deposited; 7 A1 interconnections deposited and etched.
absence of the silicon nitride step which can cause reliability problems (see (2.2.2) above) and may also suffer voltage breakdown problems with thicker epitaxial layers. This improved breakdown performance has enabled 2048 PROMS to be made using the Polyplanar technology. 2.2.4 VMOS[16] (StanJord Electronic Lab). VMOS stands for V-groove MOS and is based on the anisotropic etching properties of silicon. Rodgers and Meindl had earlier reported a V-groove bipolar process[17] which required less masks than the CDI process for example. Applied to MOS circuits several advantages appear: (i) A large decrease in cell size so that VMOS density is potentially lower than I2L (integrated injection logic[18]), the most densly packed bipolar technology available. (ii) it competes with double diffused MOS (DMOS)[19] in terms of speed. Devices with an r.f. performance beyond
P-
Fig. 4. The Polylyplanar process (after Saunders and Marcorn[15]. (hatchings as Fig. 1). I Buried n + layer with n epitaxy; 2 Isolation pattern defined and moats etched; 3 Insulation oxide grown; 4 Polysilicon deposited; 5 Excess polysilicon lapped/polished away.
5 G H z have been postulated and up to 2 G H z reported [20], by Westinghouse workers. The structure of the VMOS transistor is shown in Fig. 5. 2.3 Etching techniques 2.3.1 Anisotropic chemical etches. It will be apparent from the above discussion on partial isolation approaches that selective etching of silicon to produce V-grooves is a key feature. The technique is sometimes termed orientation dependent etching, ODE. It is a property of the diamondcubic crystal structure of silicon that close packed planes like (111), (221), (331) and so on etch as much as 100 times slower than the loosely packed planes (100) and (110). Hence if the crystal is orientated with the (100) plane as shown in Fig. 6a and a suitable etch used a V-groove is etched as shown in Fig. 6b, since the (100) planes intersect the (111) at 54.74 °. This determines the groove angle and the etch depth is therefore simply 0.707 times the etch mask opening width. This tech.. nique has been exploited recently by Bean and Lowsan [21] using K O H solutions in the processing of a high packing density silicon diode array target to control charge spreading and thus achieved improved
~
ifa!
Fig. 5. Cut away view of a VMOS transitor (after Rodgers and Meindl [16]).
118
J.R. BOSNJLI, ,, OXIDE MASK I000 J~)
~ 1 i//////j
/ ~'~'~4 ~x
~/'1/' ~/ ,'
|//////// -
- - < I O 0 >
<100> /
FIG 6(a)
i
t ~ x x •
F[G 6(b)
Fig. 6a and b. V-groove etching principles. blooming characteristics. Most etching processes for silicon employ two basic reactions, firstly, oxidize the silicon to some form of hydrated silica and secondly dissolve that silica. Generally, at least 100°C bath temperature and a complexing organic molecule, forming water soluble organo-silicates, are required for this process. This applies to both acidic and alkaline etching solutions, the difference being that the acidic solutions are mostly exothermic and etch isotropically whilst the alkaline ones usually have to be heated and remove silicon anisotropically. Several two component solutions have been reported for anisotropic etching which contain an oxidant such as potassium or sodium hydroxide, ethylene diamine or hydrazine as well as a complexing agent such as iso-2propyl alcohol, n-propanol and butanol. Hydrazine can act in both roles. Many workers have followed Lee's [22] work in this area. In particular Sumitomo et al. [7] have repeated his work and came to the following conclusions: (i) Ethylene diamine had large undercuts on exterior corners (ii) hydrazine hydrate gave a smaller amount of undercut and a lower number of defects were introduced giving a smooth surface on the etched (111) surface, the ratio of undercutting to etching depth being approximately 50%. The temperature used was 90°C. Typical relative etching rates are given by Rodgers and Meindl [17] as used in the V M O S process, for aqueous hydrazine solutions at 100cC; these are 3/~m/min for < 100) compared with 0.4 #m/ min for <111). Similar etching techniques have been used by Bean et al. [6] to produce a new total DI technique they called raised dielectric isolation (RDI) to extend the doublepoly process outlined above and overcome some of the disadvantages of that process. The result is that dielectrically isolated mesas are used in normal single crystal silicon, eliminating mechanical thickness control problems and the lapping and polishing damage introduced in the single-poly process. Furthermore the higher temperature processing steps of the double-poly process are removed, so that the concentration profiles post processing are much closer to the design values. Allison et al. [23] who were among the first to use these techniques claim that the breakdown voltages achieved (170 V in their case) would enable even Nixie tubes to be accommodated. Furthermore, the output power limitations of conventional JI circuits are overcome and the higher yield of the V-groove process should move DI processing out of the military area by eliminating the
lapping and polishing stages. High voltage pinched resistors can also be formed. 2.3.2 Preferential etchim, t teclmiques. It would be sometimes convenient if a particular resistivity silicon could be etched at a faster rate than one of highcr value say. Muraoka et al. [24, 25] have used such an etch to produce a dielectrically isolated semiconductor vidicon target. They used H F / H N O 3 / C H 3 ( ' O O H in the ratio 1.,,'3/8 parts by volume which gave an etch rate of between 0.7 and 3 itm/min for silicon resistivities of less than 1.5 × 10 e {)cm and zero etching for resistivities greater than 6.8 x 10 -' L)cm. 2.3.3 Electrochemical etchin~t. Zwicker and Kurtz[26] have recently reported an anisotropic electrochemical etching technique, which unlike the earlier work of Meek [27] and van Dijk and de Jonge [28], requires no electrical contact to the slice. This technique is based on electrochemical reactions between metal ions in solution and the silicon slice. Etching of the silicon will occur provided that the half-cell potential of the silicon substrate surface, relative to the solution, is greater than required to reduce the metal from the solution. For example, silicon in an aqueous solution of fluorine ions and ions of Co, Cu, Ag or Au, will be etched, such that a complex SiF~ is formed. A typical solution quoted by Zwicker and Kurtz is 1 mole/1, of Cu {NO3) 2 and 7 mole/1, of NH4F. Before the advent of this technique, the need to make electrical contact to each slice was a severe limitation and badly stained slices could result with poor etching uniformity over the slice because of electric field gradient problems. However, Meek [27] proposed a total DI process using electrochemical techniques and Kamins [29] has reported a combination of the isoplanar process (above) with electrochemical etching techniques, particularly for heavily doped substrates to produce a total DI circuit. The electrochemical technique of Zwicker and Kurtz [26] requiring no external source of current looks a much more xiable production process than those involving external contact to the slice being etched. It can be carried out at room temperature and there is very little attack on silicon dioxide so that special masking, which may be required for some chemical etches, is eliminated. 2.4 Ion implalTtation Ion implantation is a tool finding widespread use in the semiconductor device processing field (see, for example, Lee and Mayer [30]). The first hint that the technique may be efficacious in the production of Di circuits came in a paper by Schwuttke and Brack [31] who were initially mainly concerned with high energy (1.5 to 2MeV) ion implantation damage in single crystal silicon. However, they point out that if the concentration of reactive ions is high enough compound formation takes place, and in this case - S i 3 N 4 was formed. Further pioneering work by the Harwell Group, Freeman et al. [32] indicates that at high doses (2 × 10 ~s ions cm e) at low energies ( < 4 0 keV)
Dielectric Isolation Techniques of '60+ and 14N+ produce essentially surface layer insulators. Further work with high energy (3 MeV) nitrogen implants (Stephen et al. [33]) indicates that at 1016ion cm -2, nitrogen implantation could be used to produce pnp structures. After 900°C annealing, however, only 1~o of the buried layer which produced, the n-type material was electrical!y active. At about this time two patents were filed which postulated the use of the ion implantation technique as a means of achieving a total DI circuit. These were Coleman's patent [34] from Motorola and .Brack et al. [35] (IBM), the latter building on their fundamental work. Bracket al. [35] indicate that the concentration must be greater than 1018 ions cm-2 and that an annealing time of at least half an hour at II00°C is required for ion-silicon reactions to take place. The characteristics of N + implanted silicon are very susceptable to ion dose, ion implant energy and annealing cycle. For example, Roughan et al. [36] found that for 40keV implants in the range 3 x 1012 to 5 x 101'~ions cm -2 into (110) p-type silicon, n-type silicon layers could be produced which is consistent with the Harwell data cited above. More recently, the quality of the insulating layers which can be produced by this technique has been investigated by Dexter et al. [37]. Using 150 keV ira-
Elched Si substrate
119
plantation energies in the fluence range 1016 to 5 X 10iv ions cm 2 they have shown that layers with breakdown voltages of 7 x 105 Vcm 1 and refractive indeces comparable to bulk Si3N,~ can be produced. Furthermore, the defect concentration in 2/~m thick epitaxial layers grown on the silicon following the implant was lower than that observed for silicon on spinel layers. Using 1018 N + ions per cm" at 300keV into (111) silicon Bosnell et al. [38] have found that the epitaxial layers are of better quality than for a similar implant dose at 150keV. The technique used to assess the layer quality was the electron channelling (Coates-Kikuchi) effect in the scanning electron microscope (see references[39] and [40]). Fig. 7a shows the surface of the silicon following the above implant and a 3 hr anneal in dry nitrogen at 1200'~C. The implantation was done at a beam current of 3 #Acm-2 with the slice held 7~ off crystal axis to reduce ion channelling effects. The resultant temperature rise during implantation was about 350°C. At implant energies lower than 100keV, the surface damage was such that even long post deposition anneals did not yield a surface on which good epitasial silicon could be produced, only poly silicon. It is clear from the calculated ranges of nitrogen in silicon [41] that at these lower energies the ion damage
EpT-Si N-Si
Fig. 7a. Coates-Kikuchi pattern of N ÷ implanted silicon (t017 cm 2 at 300keV) before epitaxy; b Coates-Kikuchi pattern of (a) following epitaxial growth; c I - V characteristics through the implanted layer compared with an unimplanted area, showing the isolation.
120
J. R. BOSMH
is too near the surface, a fact utilized by Freeman et ul. [32] {see above). Our data is consistent with the measured damage profiles for N" implanted into silicon by Pronko c t a l . [42], Thex indicate that at 81)keV there is an upper limit 0[3 x 10 ~¢ ions cm 2 if cpitaxial growth of silicon is required post implantation. This requirement is incompatible with the dose required for isolation. This conclusion is supported by other high energy implant studies, for example the work of Brack et al [43] on implanting C into silicon at I MeV, no visible surface damage being seen. Using bevel and stain techniques, the damage region is easily highlighted and an examination of this region by electron microscopy yields results similar to those of Brack et a1.[43]. The behaviour of the ion implanted slice during annealing was monitored by four point resistivity probe techniques. After implantation, the resistivity of the implanted damaged region is very tow (0.3 ~cm) and n-type. However, mmealing for 4 hr at 1200C in dry nitrogen produces a high resistance layer which providing the dose is of the order of 1018 ions cm -2 (N ~) yields infra-red absorbtion curves comparable t o Si 3 N4 but broadened. The microscopic study shows that lower temperature anneals only produce some diminution in the damage but no evidence of silicon nitride. Only for anneals of greater than 1000C was compound formation observed and then only at the higher implant doses. This is consistent with the data for C + implants of Bracket al. [43]. However, using oxygen implantation we failed to produce any semblance of an isolation layer. The reason for this is not clear. It appears that out diffusion must have been occurring and there was evidence on the surface for circular stacking faults of the type reported by Dyer and Voltmer [44]. Figure 7(c) shows the isolation achieved by the above treatment compared with the straight silicon resistivity. Mesa diodes were produced in the same material and showed breakdown voltages of 100 V at currents of 1001,A. Obviously. this technique is at a much earlier stage than the anisotropic etching processes and SOS (see next section) but is showing promise. Much more detailed work is required to prove the efficacy of the technique, but the use of ion implantation is becoming widespread in silicon processing and hence it may be a cost effective technique. 2.5 Epitaxial silicon on insulators The most widespread insulating material used as a substrate for heteroepitaxy of silicon is single crystal sapphire, which, although not perfectly matched to the silicon crystal structure, is relatively close, see Table 1. Because of its universal availability the technique became known as SOS (silicon on sapphirel. It is currently making a large impact in the CMOS area where several firms are marketing products, following the pioneering work of Allison et al. [45]. Of the other possibilities listed in Table 1 the spinels MgO XAIzO~ appear to be the most likely candidates
and devices fabricated on this material have been produced particularly by the RCA workers [46]. ('onscquently there has been a tendency recently to rechristen this tield of activity ESFI rather than SOS, standing for epitaxial silicon fihns oll insulators, e.g. Goser ct al. [47]. The technique is not limited to silicon, although there is littlc data on other systcms apart from GaAs [48] and Ge [49]. There are several important electrical advantages of the technique. Firstly by etching through the epitaxial layer good isolation is readily provided (resistivity > 101~ ~cm). Secondly, sapphire in particular hits a low dielectric loss (6 × 10 ~) even at 10 GHz [50]. Thirdly, the stray capacitance effects are eliminated together with the pnpn latch up paths which can be a problem with conventional fabrication techniques. On the processing side, sapphire has good mechanical strength even at normal diffusion and oxidation temperatures and is relatively chemically inert. Some attack does take place at the nucleation stage of the epitaxial growth, probably associated with the production of hydrogen chloride during the deposition reaction. This can lead to aluminium contamination of the deposited tilm, so that a compromise has to be effected between this contamination and the crystalline perfection. In any particular system this is usually done by experimenting with growth temperatures and so on, subsequently measuring the Hall mobility and carrier lifetime (see Allison et al. [45]). Spinel has advantages as a substrate in this respect yielding films with a lower contamination level even to the extent that Seiter and Zaminer[51] have grown films on spinal using silicon tetrachloride sources as opposed to the more usual silane. The reader is referred to Zaininger and Wang [46] for more detailed references in this area. In general, as a production process SOS hits been limited to MOS because of the relatively low carrier lifetimes measured in the films. Even at film thicknesses of 20 l,m, the measured lifetimes are only about 20ns [52] which is marginal for the production of high speed bipolar logic structures. However, recent data by McGreivy and Viswanathan [52] indicate that the lifetime of n-type films is significantly increased by the presence of an n ' sublayer beneath the n-type film using As at 10 ~* c'm 3 concentration. Values in the I/~s region are thus possible. This could make bipolar circuits in SOS a much more viable process possibility. Furthermore, ion implantation. already used to help reduce the switching time for ESFIMOS devices [54], could well reduce the epitaxial layer thicknesses required to achieve these longer lifetimes, shown in Fig. 8. 2.6 Glass substrates Aside from the usual crystalline silicon approaches the thin film transistor on silica glass substrates offers a possible isolated circuit technique for some applications. For example, Westinghouse have recently shown a 6 inch square prototype display Izinc sul-
121
Dielectric Isolation Techniques
8,u.m
,-'-
,os~
~,"f/////I
~'~ 106
#
~ ~o7
A
/
I
I
I
Fig. 10. Schematic drawing of the post 1975 time scale bipolar transistor (hatchings as Fig. 1).
I
I
*
*
*
|
2 4 6 8 I0 12 14 16 18 20 EPITAXIALSILICON FILM THICKNESS(,urn) Fig. 8. Carrier lifetime as a function of film thickness for normal n-type SOS films (curve B) and n/n + SOS films (curve A). No (n-type) = 5 × 1016 cm ?', n* = 10:8 cm -3.
phide electroluminescent panel) addressed by thin film transistors, TFT, of the CdSe type [55]. The T F T has been developed for many years but has been rather overshadowed by the silicon integrated circuit. However, for large area requirements it may find a new lease of life. A general introduction to the earlier work in this field is given by Sze [56]. In general the II-VI Compounds have been used, however, recently Feldman and Plachy [57] have reported p-n junction manufacture in polycrystalline silicon films on glass, crystallized from amorphous silicon. This technique is at an early stage so that it appears that the I L V I will be general in this area for some time. At the moment it is unlikely that the T F T will be used in areas other than where a large area capability is necessary. 3. CONCLUSIONS Beyen and Cecil [58] have shown the impact of dielectric isolation techniques on packing density, reproduced in Fig. 9. Their concept of the post 1975 bipolar transistor is shown in Fig. 10, being a partial DI process like LOCOS. However, I believe that the ..a ~- 7
36 S 4 3
,y,z m
%
I
I
I
1966
1968
I / / / / ' / / /
P SUBSTRATE
i0 I0 I
I./////I
I\\\\\\\\Xl
B
1
I/'/4
I ~ t 1970
1972
1974
Fig. 9. Impact of DI techniques on device packing density.
technology may well be forced further than this and that total DI systems will become the vogue, replacing the buried n + layer in Fig. 10, not because of military radiation protection requirements but because of the performance advantages especially when applied to C M O S and the potential increase in packing density implied with higher power capability in the bipolar case. In that sense, the emergence of C M O S / S O S as a commercial product has set the trend and recent developments may point the way to an increased market for SOS isolated devices. Many processes have been omitted in this review, e.g. VATE and VIP, because of their essential similarity to those outlined above. The choice has been arbitrary. Some techniques like anodization of aluminium have similarly no been reviewed. Acknowledgements--My thanks are due to S. J. Widdows (RRE) and S. Thompson (Mullards) for many discussions on these topics. This paper is published with permission of Director RRE and was originally given at Semiconductor International 75 Wiesbaden. Copyright HBMSO.
REFERENCES 1. L. W. Ricketts, Fundamentals of Nuclear Hardening of Electronic Equipment, Wiley, New York (1972). 2. D. McWilliams, C. Fa, G. Larchian and O. Maxwell J. electrochem. Soc. 111, 153C (1964). 3. D. Christiansen, Electronics 91--96 March 20 (1967). 4. A. I. Stoller, J. A. Amick and N. E. Wolff, ibid., 97-105. 5. T. L. Huffman and R. G. Daniels, Semiconductor Silicon 1973 (Eds. H. R. Huff and R. R. Burgess) pp. 769 778. The Electrochemical Soc. (1973). 6. K. E. Bean, J. S. Crabbe, J. G. Hoffman and F. D. Malone, ibid.. 880-892. 7. Y. Sumitomo, K. Niwa, H. Sawazaki and K. Sakai, ibid., 893 904. 8. Lincoln Labs Advances in Electronic Technology, Quarterly Tech. Summary 15 p. 2 3, Nov 1973. 9. I. Kobayashi, IEEE ED-20, 399 (1973), ibid. 18, 45, 1971. 10. B. T. Murphy and V. J. Glinski, ISSCC Digest p. 38 (1968). 11. R. Edwards, R. S. Payne, C. F. Gibbon, M. L. Olmstead, R. A. Molino, D. L. Kushler, G. R. Weber and R. T. Kraetsch, Semiconductor Silicon 1973 (Eds. H. R. Huff and R. R. Burgess) pp. 905 912. The Electrochemical Soc. (1973). 12. W. D. Baker, W. H. Herndon, T. A. Longo and D. L. Pelzer, Electronics 65-70, March 29 (1973). (See also the earlier report on isoplanar ibid. p. 52). March 1 (1971).
122
J.R. Bos",li.I
13, I:i. Keel and J. A. Appels, Semiconductor Silicon 1973 iEds. H. R. Huff and R. R. Burgess) pp. 860 869. The 1 lectrochcmical Soc.(1973), 14. B. B. M. Brandt. W. Steinmaier and A. ,1. Strachan Philips. Tech. Rec. 34. 19 (19741. 15. T. J. Sanders and W:. R. Marcom. Eleetronies 117 120, April 12 (1973). 16. T. ,I. Rodgcrs and ,1. D. Meindl IEtgE SC-9. 239 250 (19741. 17. T. J. Rodgers and J. D. Meindl, IEEE ED-20, 226 232 (1973), 18. K. Harl and A. Slob. IEEE SC-7, 346 (1972). 19. H. J. Sigg, (7. D. Vendelin. T. P. Cauge and J. Kocsis IF, EE ED-19. 45 (1972). 20. T. M. S. Heng and H. ('. Nathanson, Eh'etronies Letters 10. 490 (19741. 21. K. E. Bean and J. R. Law'son. IEEE SC-9, I 11 (1974). 22. D. B. Lee, J. appl. Phys. 40, 4569 (1969). 23. D. E. Allison. A. P. Youmans and T. H. Wong, Eleetronies 112, May 12 (1969). 24. H. Muraoka. T. Ohashi, T. Yasui and A. Fuji. British Patent lJ14n4
~7.
?S.
39. 40. 41.
42. 43. 44. 45. 46. 47. 48. 49. 50, 51. 52,
53. 54. 55. 56,
57. 58.
Manchester and E. W. Anderson. J. eleetroehum. Soe. Page 74C, March (19681. R. J. Dexter, S. B. Watelski and S. T. Picraux. :ll,p/. Phys. Left. 23, 455 (1973). J. R. Bosnelk S. Thompsoil. and P. Goode, Paper A4.6. 4th Eul'opeal7 Solid Slaw Devices Research C(m[ercnee, Nottingham Sept 1974. D. G. Coates. Phil. Ma~l. 16. 1179 (1967). S. M. Davidson and G. R. Booker, Radiation Ef[i'ets 6. 33 (1970). W. S. Johnson and J. F. Gibbons, Projected Range Statistics in Semiconductors (distributed by Stanford University Bookstore 1969). P. P, Pronko, J. B. Mitchell, J. Shewchun and J. A. Davies. Radiation Effects 20, 257 (1973). K. Brack. E. Gorey and G. H. Schwuttke, Crystal Lutlice D(!l~'(llS 4. 109 11973). L. D. Dyer and F. W. Voltmer. d. eleetrochem. Soe. 120. 812 (1973). J. F. Allison, F. P. Heiman and J. R Burns. IEEE SC-2, 21)8 119671. K. H. Zainingcr and C. C. Wang. Solid State Eh, etron. 13. 943 (1970). K. Goser. M. Pomper and J. Tihanyi. IEEE SC-9. 234 (1974). H. M. Mansevit, R. L. Nolder and L. A. Moudy. Trans. Met. See. ,4IME 242. 465 (1968). R. F'. Tamposch, J. eh, etroehem. Soc. 116, 654 (1969). J. R, Bosnell, Mieroeleeu'onies 3, 33 (1971). H. Seiter and Ch. Zaminer Z. Agnew, Phys 20. 158 (19651. D. J. Dumin and R. S. Silver, Solid State Electron. I i , 353 (1968). D. J. McGreivy and C. R. Viswanathan, Appl. Phys. Lett. 25. 505 (1974). M. Pomper and J. Tihanyi, IEEE SC-9. 250 (1974). New Seientisl p. 418, 7 Nov' 1974. S, M. Sze, Physics Of Semiconductor Detices, Chapter 11, Particularly' pages 567 586. Wiley-lnterscience, New York (1969). (7. Feldman and R. Plachy. Eleetronies p. 34, May 10, 1973. W. ,1. Beyen and O. B. Cecil, Semiconduetor Silieo< I973 (Eds. H. R, Huff and R. R. Burgess) pp. I 16. The Electrochemical Soc. (1973).
DIELECTRIC ISOLATION TECHNIQUES FOR INTEGRATED CIRCUITS J. R. BOSNELL Royal Radar Establishment, Malvern, Worcs, U.K. Abstract--There has been an increasing interest in producing dielectrically isolated integrated circuits over the past five years for both bipolar and MOS. This impetus stems from the potential of such a technique to increase the operational speed of the circuit, particularly CMOS by reduction of the stray capacitance and a need to reduce the susceptibility of monolithic circuits to photocurrents generated by radiation in space and military environments. In general, early methods for producing dielectrically isolated circuits involved relatively costly lapping and polishing techniques which were generally low yield processes or the development of a completely new process e.g. silicon on sapphire. Recently, preferential anisotropic silicon etchants which may eliminate the mechanical process steps have been announced, as well as the possibility of ion implantation of heavy doses of nitrogen or oxygen at relatively high energies to produce the buried dielectric layer. These new processes will be compared with more traditional methods.
!. I N T R O D U C T I O N
One of the major advantages of the monolithic integrated circuit is the increased reliability stemming from the on-chip thin film interconnection system of a large number of building blocks; transistors, diodes, capacitors and resistors. However, the resistivity of the basic silicon, from which these blocks are made, is generally low so that techniques must be devised to electrically isolate adjacent blocks. Traditionally this has been achieved by surrounding each elementary circuit by a reverse biased p-n junction as the sidewall isolation, using the substrate to define the
bottom isolation (Fig. la). Unfortunately, this relatively simple and inexpensive technique introduces unwanted capacitances, which are temperature and voltage sensitive and limit the operational speed of the circuit. Furthermore, care must bctakcn to avoid the formation of four layer, pnpn. parasitic de\ices in the design of the chip. This is especially troublesome in a radiation environment where large photocurrents can be created by transient ionizing radiations [1]. The breakdown voltage is inversely proportional to the doping level of the isolation material and must therefore be carefully controlled to avoid
S. n n
n
n
3.
~J? ~ ÷ j
n-
FIG. I(o)
6.
J~ n
"1" DIFFUSION
[]
OXIDE
[]
POLYSILICON
3 L=,
FIG. I (b)
Fig. ta. Junction isolation process (schematic). lb. Dielectric isolation process using a polysilicon handle (schematic). la. l p- Substrate, n + buried layer, n- epitaxial layer; 2 Isolation pattern defined; 3 p+ isolation deposition; 4 p+ isolation diffusion. lb. 1 Surface preparation; 2n ÷ deposition and masking oxide; 3 isolation pattern and most etch; 4 dielectric oxide grown; 5 polysilicon deposition; 6 blacklap and polish; 7 finished slice. 113
114
J.R. Bosx~u
high leakage currents. From the point of view of bipolar memories an additional problem is the severe reduction in packing density due to lateral diffusion of the isolation walls. Manufacturers, endeavouring t o o v e r c o m e these limitations of junction isolation, Jl, have introduced a variety of schemes loosely termed dielectric isolation, DI. Fig. lb illustrates one of these processes. In this case a polysilicon handle is used to enable a lapping and polishing operation to be performed• The result is that each device "'tub" is completely surrounded by silicon dioxide, hence, dielectrically isolated. This technique [2] is the oldest of the many variants and probably the most widely used until recently. Simplistically, the aim of all the various approaches is to achieve at least the same pertbrmance as an equivalent assembly of discrete components. Clearly, however, there is a delicate balar~ce between the performance advantage gained by dielectric isolation techniques and the additional cost incurred by these processes since most of the variants of DI involve a greater number of process steps than Jl (in some cases as many as 30 more) with the resultant yield loss and cost increase. M a n y of the early dielectric isolation schemes have been abandoned. The early approaches are well illustrated in Christiansen's review [3], and will be listed here only briefly. 1.1 Silicon carhide Added to the oxide growth steps illustrated in Fig. l b is a silicon carbide growth stage. This facilitates the removal of excess n-type silicon and because of its hardness acts as a lap stop during the lapping/" polishing phase. However, the process requires additional forming stages and more lapping to remove the carbide•
1.5 Beam lead This idea exploits the Bell System beam lead technology. The beam leads torm both electrical and mechanical connections between several discrete circuit elements. High frequency operation and a freedom from hermetic sealing are advantages of thc process. However, it is a relatively complex series of steps. 1.6 Air oxide Polysilicon is again used, but this time as a supporting substrate retained in the finished device. Molybdenum gold metallization is used in the interconnection pattern, the gold being built up in certain areas by electroplating. The silicon between devices is selectively etched, leaving air isolation between them, with oxide on the polysilicon, thus air oxide isolation. The metallization and etching steps are relatively complicated. 1.7 Decal [4] Individual devices on the wafer are produced in the normal manner. The metallization, however, has to withstand high temperature processing later and is therefore a refractory metal like titanium. The wafer is bonded metallization side down to glass direct at 800°C. Hence the term decal; to transfer patterns to a surface. Isolation between elemental blocks is then achieved by lapping away excess silicon and selective etching, using the glass as a carrier. If necessary other dielectrics may be used to fill the spaces between devices. The major advantage of this technique is that again there is no need for device protection steps. However, the high temperature bonding phase is a problem.
1.2 Mesa
1.8 Chess board
in this technique, the circuit blocks are diffused etched, and inter-connected in the normal way. A substrate is then joined to the slice using a screen printable or spin-on glass. The back of circuit as selectively etched to provide isolation. Although this isolation technique may make encapsulation unnecessary, lapping as well as etching may be required to remove excess silicon.
Several schemes fall in this category. (i) Form mesa devices, hot press glass between mesas, lap excess silicon from the back and metallize the resultant wafer. However, expansion matched glasses are difficult to obtain which do not act as diffusion sources. (ii) Alternate layers of silicon and insulator are bonded together and sawn into slices. Insulators such as Pyroceram have been postulated for the sandwich. Diffuse and metallize the resultant chess board. Again expansion matching to produce bow-free slices is a problem.
1.3 Handle wal'er The so-called "'handle wafer" technique has many similarities with the mesa approach. Here mesas containing the devices are etched before a glass coated silicon handle is fused to the mesas, the "handle wafer". Lapping then removes excess silicon and the voids between mesas are backfilled with glass. The "handle" is then etched away. 1.4 Ceramic This approach is essentially an amalgam of 1.2 and 1.3. The handle is now a glass carrier which has to be removed at the end of the process. A ceramic cement is used to fill the voids.
2. M A J O R PROCESSES
2.1 Polysilicon The traditional dielectric isolation technique employing polysilicon is illustrated in Fig. lb. An obvious disadvantage of the process can be seen from the figure; the increase in the number of process steps over junction isolation. A technical difficulty not explicit in the figure is the bowing of the slice which
Cubic (diamond) Cubic (diamond) Cubic (zinc blende) Rhombohedral
Cubic
Hexagonal
Hexagonal Cubic Rhombohedral <435°C Cubic > 4 3 5 ° C Tetragonal Cubic
Si Ge GaAs A1203
MgO.XA1203
~-SiO2
BeO ThO2 LaA103
ZrSiO4 MgO
Crystal Structure
Material
a a a a a a
= = = = =
a = 8.11 a = 8.02 a = 7.98 5,39
12.97
2.7, c = 4.39 5.60 3.79, c = 90°5 3.81 5.58, c, - 5.93 4.20
a = 5.431 a = 5.657 a = 5.653 a - 4.7, c = ref. hex. cell MgO.AI20 3 MgO.2A1203 MgO.3A1203 a = 4.9, c =
Lattice P a r a m e t e r (A)
239(~2550 2850
2530 3300 2000 2200
2130 2080 2000 1710
1430 958 1280 2040
Melting Point (°C)
5.5 ((Yl200~C) 14.4 (20-1200'~C)
8.1 (5(~1000°C) 18.0 ((~1000°C) ( ± r to C axis) 9.0 (0-1200°C) 9.4 (0.1200°C) 12.0 (25 65ff'C)
8.8 (2(~1200°C)
3.9 (50 1000 C) 5.658 6.68 9.5 (2(~2000'C)
Coefficient of Linear Expansion ( 1 0 - s / ° C - ~ )
Single crystal platelets Arc-melted single crystals
H y d r o t h e r m a l l y grown single crystal Flux grown crystals Single crystal platelets Single crystal platelets
Flux, Verneuil & Czochralski g r o w n single crystals Flux, Verneuil & Czochralski g r o w n single crystals
Single Crystal Availability
Table 1. Possible single crystal insulators as substrates for epitaxial g r o w t h of semiconductors c o m p a r e d with the physical properties of the m o s t c o m m o n semiconductors
ta~
.E
t~
116
.I.R. Bos,,ll I
ensues from the difference the expansion coefficients of SiO: and polysilicon (see Table I). This can cause a catastrophic yield reduction since the outer areas of the slice will generally lap first. Some teclmologies try to overcome this by alternate SiO_, and polysilicon growth the restlltant sandwich having almost compensated stresses, or the lapping tool is suitably shaped. The technology is capable of extension to produce both p and n-type tubs, sometimes called the complementary dielectric isolation process. Instead of starting with an n-type substrate as in Fig. lb, />type is used, followed by the p diffusions. After oxide growth, the slice is selectively etched and backfilled epitaxially with n-type silicon. Hence complementary n/m and Imp transistors can be manufactured. An example of the use of the technology has been reported recently by Huffman and Daniels [5] for the production of a low power complementary, operational amplifier. Several tradenames cover this process e.g. single poly and double poly used by TI [6]. Excessive leakage currents can arise in the single poly process since the n-type material can be subjected to damage at the backtap and polish stage. The double poly process introduces a second poly-silicon deposition stage protecting the n-type material from mechanical or chemical damage. However, it can mean that during the dielectric isolation production junctions are subjected to high temperatures for long times. This means that concentration prptiles are severely degraded. Polysilicon has recently been employed m either collector current channels [7] or as the actual isolation material [8]. Both sets of workers have built their ideas on Kobayashi's [9] use of polysilicon in the form of a vertical plug to provide a high diffusivity 110 to 20 times single crystal silicon) means of increasing the distribution of dopant to the lower reaches of the p n isolation. However. the largest use of polysilicon in DI processing is rapidly becoming the filling of l'-groove isolation processes to provide a fiat surface for subsequent memllizafion. 2.2 Partial i.solation techniques In 1968 Bell Labs, using thin p-type epitaxial base layers announced a process which achieved isolation by using the collector contact diffusion [10] (Fig. 2a).
CDI FIG. 2 I a )
OXIM FIG. 21b|
Fig. 2a. CDI process transistor compared with the OXIM version Fig. 2b (hatchings as Fig. I).
One disadvantage of this basic ( ' D I scheme is tile low collector-base breakdown \ohage. Oxide isolalion has been used to eliminate this by' replacing that portion of the extrinsic base region between emitter and the isolation with oxide (Fig. 2b). This process has become known as OXIM (Oxide Isolated Monolith [11]. It will be seen that there is a useful reduction in real estate on the chip. Furthermore. lhe smaller collector junction area. as well as the elimination of the sidewall portion of the base-collector junction, means a greatl 3 reduced collector capacitance and collector-substrate capacitance. Powerdehtv products on experimental TTL gates in this process are reported to be about 5 p J. 15 ns delays at I m W ) at least live times less thatl CDI circuits with similar design rules. Similar partial isolation is achieved by variations on thc OXIM theme. 2.2. I Isophmar [I 2] (F~Hrchild). Again. the substrate is not isolated but isoplanar II achieves an area reduction of over 50':, on conventional processing. Furthermore. a maximum Irequenc.,, of operation greater than 5 G H z has been reported compared with less than 3 G H z for more usual technologies. Both TTL and ECL RAMs (up to 1024 bits) have been announced in this technolog3, with the delay-power product of the ECL variety being 23 p J. for a cell size of 10 mil e. It should be emphasized here that the process was originally described by Marandi (SGS ATES. Milan) as a planar M O S technology. Because of the gradual transition [Veto field oxide to gate oxide at the source-drain regions in this process the uniformity of photoresist coverage is increased giving improved yield figures. Accelerated stress tests indicate a failure rate of 0.(X)lY",; per 10(X) hours at I(10 C for the bipolar isoplanar technolog,,. 2.2.2 LOCOS [13] (Philip.s). The acronym LOCOS stands for Local oxidation of .silicon. The process is very similar to those above and will not be described in detail. Keel and Appels [I 3] point out the problem of "'bird head" which lifts the nitride masking especially if lateral oxidation has occurred to lolm a 'bird beak". However, a major part of the beak can bc removcd by etching or b,,. careful manipulation of the nitride stage. L O C O S has been applied to C M O S manulacturc the resultant acronym being LOCMOS, the process steps being shown in Fig. 3 (after Brandt el al [14]). The application of LOCOS to C M O S achieves a saving in lateral dimensions of a factor of two and a speed increase from a factor of at least 3, enabling shift registers to operate at 10MHz clock rates from a 5V supply on half the real estate of a conventional circuit. 2.2.3 Polyl)hmar[15] (ftarris). Thc process steps are illustrated in Fig. 4. Polysilicon is used to fill the etched moats and is then lapped to provide a fiat metallization surlhcc. The most is formed by an anisetropic etch in (100) direction. Wc shall return to anisotropic etchants later. The Itamess of the resultant surface is reported to simplif3, multi-level metalization schemes. A in~.tior advantage of the process is the
Dielectric Isolation Techniques
117
OXIDE
i
N
[
~
NITRIDE
i
~
P -s~
n-
P+-Si POLYCRYSTALL~NE Si
v/1/.
N*- Si
i
N
2
J
gml
Ai
p-
i
i
N
i
3
5
6
7
1
J
Fig. 3. 1 LOCOS oxide is grown, and n-type Si is coated with silicon nitride; 2 Boron diffusions through windows in the Si3N4 are used to form the p-type regions of the N-channel transistors; 3 Remove the Si3N4, from a thin oxide layer and the deposit polysilicon. Gates and interconnections are etched in this layer; 4 Sources and drains, p+ diffusions for the P-channel transitor are formed by boron diffusion on the right hand side (gates and LOCOS oxide serve as masks); 5 Sources and drains, n +, formed by phosphous diffusions in p-type regions (left); 6 SiO2 pyrolitically deposited; 7 A1 interconnections deposited and etched.
absence of the silicon nitride step which can cause reliability problems (see (2.2.2) above) and may also suffer voltage breakdown problems with thicker epitaxial layers. This improved breakdown performance has enabled 2048 PROMS to be made using the Polyplanar technology. 2.2.4 VMOS[16] (StanJord Electronic Lab). VMOS stands for V-groove MOS and is based on the anisotropic etching properties of silicon. Rodgers and Meindl had earlier reported a V-groove bipolar process[17] which required less masks than the CDI process for example. Applied to MOS circuits several advantages appear: (i) A large decrease in cell size so that VMOS density is potentially lower than I2L (integrated injection logic[18]), the most densly packed bipolar technology available. (ii) it competes with double diffused MOS (DMOS)[19] in terms of speed. Devices with an r.f. performance beyond
P-
Fig. 4. The Polylyplanar process (after Saunders and Marcorn[15]. (hatchings as Fig. 1). I Buried n + layer with n epitaxy; 2 Isolation pattern defined and moats etched; 3 Insulation oxide grown; 4 Polysilicon deposited; 5 Excess polysilicon lapped/polished away.
5 G H z have been postulated and up to 2 G H z reported [20], by Westinghouse workers. The structure of the VMOS transistor is shown in Fig. 5. 2.3 Etching techniques 2.3.1 Anisotropic chemical etches. It will be apparent from the above discussion on partial isolation approaches that selective etching of silicon to produce V-grooves is a key feature. The technique is sometimes termed orientation dependent etching, ODE. It is a property of the diamondcubic crystal structure of silicon that close packed planes like (111), (221), (331) and so on etch as much as 100 times slower than the loosely packed planes (100) and (110). Hence if the crystal is orientated with the (100) plane as shown in Fig. 6a and a suitable etch used a V-groove is etched as shown in Fig. 6b, since the (100) planes intersect the (111) at 54.74 °. This determines the groove angle and the etch depth is therefore simply 0.707 times the etch mask opening width. This tech.. nique has been exploited recently by Bean and Lowsan [21] using K O H solutions in the processing of a high packing density silicon diode array target to control charge spreading and thus achieved improved
~
ifa!
Fig. 5. Cut away view of a VMOS transitor (after Rodgers and Meindl [16]).
118
J.R. BOSNJLI, ,, OXIDE MASK I000 J~)
~ 1 i//////j
/ ~'~'~4 ~x
~/'1/' ~/ ,'
|//////// -
- - < I O 0 >
<100> /
FIG 6(a)
i
t ~ x x •
F[G 6(b)
Fig. 6a and b. V-groove etching principles. blooming characteristics. Most etching processes for silicon employ two basic reactions, firstly, oxidize the silicon to some form of hydrated silica and secondly dissolve that silica. Generally, at least 100°C bath temperature and a complexing organic molecule, forming water soluble organo-silicates, are required for this process. This applies to both acidic and alkaline etching solutions, the difference being that the acidic solutions are mostly exothermic and etch isotropically whilst the alkaline ones usually have to be heated and remove silicon anisotropically. Several two component solutions have been reported for anisotropic etching which contain an oxidant such as potassium or sodium hydroxide, ethylene diamine or hydrazine as well as a complexing agent such as iso-2propyl alcohol, n-propanol and butanol. Hydrazine can act in both roles. Many workers have followed Lee's [22] work in this area. In particular Sumitomo et al. [7] have repeated his work and came to the following conclusions: (i) Ethylene diamine had large undercuts on exterior corners (ii) hydrazine hydrate gave a smaller amount of undercut and a lower number of defects were introduced giving a smooth surface on the etched (111) surface, the ratio of undercutting to etching depth being approximately 50%. The temperature used was 90°C. Typical relative etching rates are given by Rodgers and Meindl [17] as used in the V M O S process, for aqueous hydrazine solutions at 100cC; these are 3/~m/min for < 100) compared with 0.4 #m/ min for <111). Similar etching techniques have been used by Bean et al. [6] to produce a new total DI technique they called raised dielectric isolation (RDI) to extend the doublepoly process outlined above and overcome some of the disadvantages of that process. The result is that dielectrically isolated mesas are used in normal single crystal silicon, eliminating mechanical thickness control problems and the lapping and polishing damage introduced in the single-poly process. Furthermore the higher temperature processing steps of the double-poly process are removed, so that the concentration profiles post processing are much closer to the design values. Allison et al. [23] who were among the first to use these techniques claim that the breakdown voltages achieved (170 V in their case) would enable even Nixie tubes to be accommodated. Furthermore, the output power limitations of conventional JI circuits are overcome and the higher yield of the V-groove process should move DI processing out of the military area by eliminating the
lapping and polishing stages. High voltage pinched resistors can also be formed. 2.3.2 Preferential etchim, t teclmiques. It would be sometimes convenient if a particular resistivity silicon could be etched at a faster rate than one of highcr value say. Muraoka et al. [24, 25] have used such an etch to produce a dielectrically isolated semiconductor vidicon target. They used H F / H N O 3 / C H 3 ( ' O O H in the ratio 1.,,'3/8 parts by volume which gave an etch rate of between 0.7 and 3 itm/min for silicon resistivities of less than 1.5 × 10 e {)cm and zero etching for resistivities greater than 6.8 x 10 -' L)cm. 2.3.3 Electrochemical etchin~t. Zwicker and Kurtz[26] have recently reported an anisotropic electrochemical etching technique, which unlike the earlier work of Meek [27] and van Dijk and de Jonge [28], requires no electrical contact to the slice. This technique is based on electrochemical reactions between metal ions in solution and the silicon slice. Etching of the silicon will occur provided that the half-cell potential of the silicon substrate surface, relative to the solution, is greater than required to reduce the metal from the solution. For example, silicon in an aqueous solution of fluorine ions and ions of Co, Cu, Ag or Au, will be etched, such that a complex SiF~ is formed. A typical solution quoted by Zwicker and Kurtz is 1 mole/1, of Cu {NO3) 2 and 7 mole/1, of NH4F. Before the advent of this technique, the need to make electrical contact to each slice was a severe limitation and badly stained slices could result with poor etching uniformity over the slice because of electric field gradient problems. However, Meek [27] proposed a total DI process using electrochemical techniques and Kamins [29] has reported a combination of the isoplanar process (above) with electrochemical etching techniques, particularly for heavily doped substrates to produce a total DI circuit. The electrochemical technique of Zwicker and Kurtz [26] requiring no external source of current looks a much more xiable production process than those involving external contact to the slice being etched. It can be carried out at room temperature and there is very little attack on silicon dioxide so that special masking, which may be required for some chemical etches, is eliminated. 2.4 Ion implalTtation Ion implantation is a tool finding widespread use in the semiconductor device processing field (see, for example, Lee and Mayer [30]). The first hint that the technique may be efficacious in the production of Di circuits came in a paper by Schwuttke and Brack [31] who were initially mainly concerned with high energy (1.5 to 2MeV) ion implantation damage in single crystal silicon. However, they point out that if the concentration of reactive ions is high enough compound formation takes place, and in this case - S i 3 N 4 was formed. Further pioneering work by the Harwell Group, Freeman et al. [32] indicates that at high doses (2 × 10 ~s ions cm e) at low energies ( < 4 0 keV)
Dielectric Isolation Techniques of '60+ and 14N+ produce essentially surface layer insulators. Further work with high energy (3 MeV) nitrogen implants (Stephen et al. [33]) indicates that at 1016ion cm -2, nitrogen implantation could be used to produce pnp structures. After 900°C annealing, however, only 1~o of the buried layer which produced, the n-type material was electrical!y active. At about this time two patents were filed which postulated the use of the ion implantation technique as a means of achieving a total DI circuit. These were Coleman's patent [34] from Motorola and .Brack et al. [35] (IBM), the latter building on their fundamental work. Bracket al. [35] indicate that the concentration must be greater than 1018 ions cm-2 and that an annealing time of at least half an hour at II00°C is required for ion-silicon reactions to take place. The characteristics of N + implanted silicon are very susceptable to ion dose, ion implant energy and annealing cycle. For example, Roughan et al. [36] found that for 40keV implants in the range 3 x 1012 to 5 x 101'~ions cm -2 into (110) p-type silicon, n-type silicon layers could be produced which is consistent with the Harwell data cited above. More recently, the quality of the insulating layers which can be produced by this technique has been investigated by Dexter et al. [37]. Using 150 keV ira-
Elched Si substrate
119
plantation energies in the fluence range 1016 to 5 X 10iv ions cm 2 they have shown that layers with breakdown voltages of 7 x 105 Vcm 1 and refractive indeces comparable to bulk Si3N,~ can be produced. Furthermore, the defect concentration in 2/~m thick epitaxial layers grown on the silicon following the implant was lower than that observed for silicon on spinel layers. Using 1018 N + ions per cm" at 300keV into (111) silicon Bosnell et al. [38] have found that the epitaxial layers are of better quality than for a similar implant dose at 150keV. The technique used to assess the layer quality was the electron channelling (Coates-Kikuchi) effect in the scanning electron microscope (see references[39] and [40]). Fig. 7a shows the surface of the silicon following the above implant and a 3 hr anneal in dry nitrogen at 1200'~C. The implantation was done at a beam current of 3 #Acm-2 with the slice held 7~ off crystal axis to reduce ion channelling effects. The resultant temperature rise during implantation was about 350°C. At implant energies lower than 100keV, the surface damage was such that even long post deposition anneals did not yield a surface on which good epitasial silicon could be produced, only poly silicon. It is clear from the calculated ranges of nitrogen in silicon [41] that at these lower energies the ion damage
EpT-Si N-Si
Fig. 7a. Coates-Kikuchi pattern of N ÷ implanted silicon (t017 cm 2 at 300keV) before epitaxy; b Coates-Kikuchi pattern of (a) following epitaxial growth; c I - V characteristics through the implanted layer compared with an unimplanted area, showing the isolation.
120
J. R. BOSMH
is too near the surface, a fact utilized by Freeman et ul. [32] {see above). Our data is consistent with the measured damage profiles for N" implanted into silicon by Pronko c t a l . [42], Thex indicate that at 81)keV there is an upper limit 0[3 x 10 ~¢ ions cm 2 if cpitaxial growth of silicon is required post implantation. This requirement is incompatible with the dose required for isolation. This conclusion is supported by other high energy implant studies, for example the work of Brack et al [43] on implanting C into silicon at I MeV, no visible surface damage being seen. Using bevel and stain techniques, the damage region is easily highlighted and an examination of this region by electron microscopy yields results similar to those of Brack et a1.[43]. The behaviour of the ion implanted slice during annealing was monitored by four point resistivity probe techniques. After implantation, the resistivity of the implanted damaged region is very tow (0.3 ~cm) and n-type. However, mmealing for 4 hr at 1200C in dry nitrogen produces a high resistance layer which providing the dose is of the order of 1018 ions cm -2 (N ~) yields infra-red absorbtion curves comparable t o Si 3 N4 but broadened. The microscopic study shows that lower temperature anneals only produce some diminution in the damage but no evidence of silicon nitride. Only for anneals of greater than 1000C was compound formation observed and then only at the higher implant doses. This is consistent with the data for C + implants of Bracket al. [43]. However, using oxygen implantation we failed to produce any semblance of an isolation layer. The reason for this is not clear. It appears that out diffusion must have been occurring and there was evidence on the surface for circular stacking faults of the type reported by Dyer and Voltmer [44]. Figure 7(c) shows the isolation achieved by the above treatment compared with the straight silicon resistivity. Mesa diodes were produced in the same material and showed breakdown voltages of 100 V at currents of 1001,A. Obviously. this technique is at a much earlier stage than the anisotropic etching processes and SOS (see next section) but is showing promise. Much more detailed work is required to prove the efficacy of the technique, but the use of ion implantation is becoming widespread in silicon processing and hence it may be a cost effective technique. 2.5 Epitaxial silicon on insulators The most widespread insulating material used as a substrate for heteroepitaxy of silicon is single crystal sapphire, which, although not perfectly matched to the silicon crystal structure, is relatively close, see Table 1. Because of its universal availability the technique became known as SOS (silicon on sapphirel. It is currently making a large impact in the CMOS area where several firms are marketing products, following the pioneering work of Allison et al. [45]. Of the other possibilities listed in Table 1 the spinels MgO XAIzO~ appear to be the most likely candidates
and devices fabricated on this material have been produced particularly by the RCA workers [46]. ('onscquently there has been a tendency recently to rechristen this tield of activity ESFI rather than SOS, standing for epitaxial silicon fihns oll insulators, e.g. Goser ct al. [47]. The technique is not limited to silicon, although there is littlc data on other systcms apart from GaAs [48] and Ge [49]. There are several important electrical advantages of the technique. Firstly by etching through the epitaxial layer good isolation is readily provided (resistivity > 101~ ~cm). Secondly, sapphire in particular hits a low dielectric loss (6 × 10 ~) even at 10 GHz [50]. Thirdly, the stray capacitance effects are eliminated together with the pnpn latch up paths which can be a problem with conventional fabrication techniques. On the processing side, sapphire has good mechanical strength even at normal diffusion and oxidation temperatures and is relatively chemically inert. Some attack does take place at the nucleation stage of the epitaxial growth, probably associated with the production of hydrogen chloride during the deposition reaction. This can lead to aluminium contamination of the deposited tilm, so that a compromise has to be effected between this contamination and the crystalline perfection. In any particular system this is usually done by experimenting with growth temperatures and so on, subsequently measuring the Hall mobility and carrier lifetime (see Allison et al. [45]). Spinel has advantages as a substrate in this respect yielding films with a lower contamination level even to the extent that Seiter and Zaminer[51] have grown films on spinal using silicon tetrachloride sources as opposed to the more usual silane. The reader is referred to Zaininger and Wang [46] for more detailed references in this area. In general, as a production process SOS hits been limited to MOS because of the relatively low carrier lifetimes measured in the films. Even at film thicknesses of 20 l,m, the measured lifetimes are only about 20ns [52] which is marginal for the production of high speed bipolar logic structures. However, recent data by McGreivy and Viswanathan [52] indicate that the lifetime of n-type films is significantly increased by the presence of an n ' sublayer beneath the n-type film using As at 10 ~* c'm 3 concentration. Values in the I/~s region are thus possible. This could make bipolar circuits in SOS a much more viable process possibility. Furthermore, ion implantation. already used to help reduce the switching time for ESFIMOS devices [54], could well reduce the epitaxial layer thicknesses required to achieve these longer lifetimes, shown in Fig. 8. 2.6 Glass substrates Aside from the usual crystalline silicon approaches the thin film transistor on silica glass substrates offers a possible isolated circuit technique for some applications. For example, Westinghouse have recently shown a 6 inch square prototype display Izinc sul-
121
Dielectric Isolation Techniques
8,u.m
,-'-
,os~
~,"f/////I
~'~ 106
#
~ ~o7
A
/
I
I
I
Fig. 10. Schematic drawing of the post 1975 time scale bipolar transistor (hatchings as Fig. 1).
I
I
*
*
*
|
2 4 6 8 I0 12 14 16 18 20 EPITAXIALSILICON FILM THICKNESS(,urn) Fig. 8. Carrier lifetime as a function of film thickness for normal n-type SOS films (curve B) and n/n + SOS films (curve A). No (n-type) = 5 × 1016 cm ?', n* = 10:8 cm -3.
phide electroluminescent panel) addressed by thin film transistors, TFT, of the CdSe type [55]. The T F T has been developed for many years but has been rather overshadowed by the silicon integrated circuit. However, for large area requirements it may find a new lease of life. A general introduction to the earlier work in this field is given by Sze [56]. In general the II-VI Compounds have been used, however, recently Feldman and Plachy [57] have reported p-n junction manufacture in polycrystalline silicon films on glass, crystallized from amorphous silicon. This technique is at an early stage so that it appears that the I L V I will be general in this area for some time. At the moment it is unlikely that the T F T will be used in areas other than where a large area capability is necessary. 3. CONCLUSIONS Beyen and Cecil [58] have shown the impact of dielectric isolation techniques on packing density, reproduced in Fig. 9. Their concept of the post 1975 bipolar transistor is shown in Fig. 10, being a partial DI process like LOCOS. However, I believe that the ..a ~- 7
36 S 4 3
,y,z m
%
I
I
I
1966
1968
I / / / / ' / / /
P SUBSTRATE
i0 I0 I
I./////I
I\\\\\\\\Xl
B
1
I/'/4
I ~ t 1970
1972
1974
Fig. 9. Impact of DI techniques on device packing density.
technology may well be forced further than this and that total DI systems will become the vogue, replacing the buried n + layer in Fig. 10, not because of military radiation protection requirements but because of the performance advantages especially when applied to C M O S and the potential increase in packing density implied with higher power capability in the bipolar case. In that sense, the emergence of C M O S / S O S as a commercial product has set the trend and recent developments may point the way to an increased market for SOS isolated devices. Many processes have been omitted in this review, e.g. VATE and VIP, because of their essential similarity to those outlined above. The choice has been arbitrary. Some techniques like anodization of aluminium have similarly no been reviewed. Acknowledgements--My thanks are due to S. J. Widdows (RRE) and S. Thompson (Mullards) for many discussions on these topics. This paper is published with permission of Director RRE and was originally given at Semiconductor International 75 Wiesbaden. Copyright HBMSO.
REFERENCES 1. L. W. Ricketts, Fundamentals of Nuclear Hardening of Electronic Equipment, Wiley, New York (1972). 2. D. McWilliams, C. Fa, G. Larchian and O. Maxwell J. electrochem. Soc. 111, 153C (1964). 3. D. Christiansen, Electronics 91--96 March 20 (1967). 4. A. I. Stoller, J. A. Amick and N. E. Wolff, ibid., 97-105. 5. T. L. Huffman and R. G. Daniels, Semiconductor Silicon 1973 (Eds. H. R. Huff and R. R. Burgess) pp. 769 778. The Electrochemical Soc. (1973). 6. K. E. Bean, J. S. Crabbe, J. G. Hoffman and F. D. Malone, ibid.. 880-892. 7. Y. Sumitomo, K. Niwa, H. Sawazaki and K. Sakai, ibid., 893 904. 8. Lincoln Labs Advances in Electronic Technology, Quarterly Tech. Summary 15 p. 2 3, Nov 1973. 9. I. Kobayashi, IEEE ED-20, 399 (1973), ibid. 18, 45, 1971. 10. B. T. Murphy and V. J. Glinski, ISSCC Digest p. 38 (1968). 11. R. Edwards, R. S. Payne, C. F. Gibbon, M. L. Olmstead, R. A. Molino, D. L. Kushler, G. R. Weber and R. T. Kraetsch, Semiconductor Silicon 1973 (Eds. H. R. Huff and R. R. Burgess) pp. 905 912. The Electrochemical Soc. (1973). 12. W. D. Baker, W. H. Herndon, T. A. Longo and D. L. Pelzer, Electronics 65-70, March 29 (1973). (See also the earlier report on isoplanar ibid. p. 52). March 1 (1971).
122
J.R. Bos",li.I
13, I:i. Keel and J. A. Appels, Semiconductor Silicon 1973 iEds. H. R. Huff and R. R. Burgess) pp. 860 869. The 1 lectrochcmical Soc.(1973), 14. B. B. M. Brandt. W. Steinmaier and A. ,1. Strachan Philips. Tech. Rec. 34. 19 (19741. 15. T. J. Sanders and W:. R. Marcom. Eleetronies 117 120, April 12 (1973). 16. T. ,I. Rodgcrs and ,1. D. Meindl IEtgE SC-9. 239 250 (19741. 17. T. J. Rodgers and J. D. Meindl, IEEE ED-20, 226 232 (1973), 18. K. Harl and A. Slob. IEEE SC-7, 346 (1972). 19. H. J. Sigg, (7. D. Vendelin. T. P. Cauge and J. Kocsis IF, EE ED-19. 45 (1972). 20. T. M. S. Heng and H. ('. Nathanson, Eh'etronies Letters 10. 490 (19741. 21. K. E. Bean and J. R. Law'son. IEEE SC-9, I 11 (1974). 22. D. B. Lee, J. appl. Phys. 40, 4569 (1969). 23. D. E. Allison. A. P. Youmans and T. H. Wong, Eleetronies 112, May 12 (1969). 24. H. Muraoka. T. Ohashi, T. Yasui and A. Fuji. British Patent lJ14n4
~7.
?S.
39. 40. 41.
42. 43. 44. 45. 46. 47. 48. 49. 50, 51. 52,
53. 54. 55. 56,
57. 58.
Manchester and E. W. Anderson. J. eleetroehum. Soe. Page 74C, March (19681. R. J. Dexter, S. B. Watelski and S. T. Picraux. :ll,p/. Phys. Left. 23, 455 (1973). J. R. Bosnelk S. Thompsoil. and P. Goode, Paper A4.6. 4th Eul'opeal7 Solid Slaw Devices Research C(m[ercnee, Nottingham Sept 1974. D. G. Coates. Phil. Ma~l. 16. 1179 (1967). S. M. Davidson and G. R. Booker, Radiation Ef[i'ets 6. 33 (1970). W. S. Johnson and J. F. Gibbons, Projected Range Statistics in Semiconductors (distributed by Stanford University Bookstore 1969). P. P, Pronko, J. B. Mitchell, J. Shewchun and J. A. Davies. Radiation Effects 20, 257 (1973). K. Brack. E. Gorey and G. H. Schwuttke, Crystal Lutlice D(!l~'(llS 4. 109 11973). L. D. Dyer and F. W. Voltmer. d. eleetrochem. Soe. 120. 812 (1973). J. F. Allison, F. P. Heiman and J. R Burns. IEEE SC-2, 21)8 119671. K. H. Zainingcr and C. C. Wang. Solid State Eh, etron. 13. 943 (1970). K. Goser. M. Pomper and J. Tihanyi. IEEE SC-9. 234 (1974). H. M. Mansevit, R. L. Nolder and L. A. Moudy. Trans. Met. See. ,4IME 242. 465 (1968). R. F'. Tamposch, J. eh, etroehem. Soc. 116, 654 (1969). J. R, Bosnell, Mieroeleeu'onies 3, 33 (1971). H. Seiter and Ch. Zaminer Z. Agnew, Phys 20. 158 (19651. D. J. Dumin and R. S. Silver, Solid State Electron. I i , 353 (1968). D. J. McGreivy and C. R. Viswanathan, Appl. Phys. Lett. 25. 505 (1974). M. Pomper and J. Tihanyi, IEEE SC-9. 250 (1974). New Seientisl p. 418, 7 Nov' 1974. S, M. Sze, Physics Of Semiconductor Detices, Chapter 11, Particularly' pages 567 586. Wiley-lnterscience, New York (1969). (7. Feldman and R. Plachy. Eleetronies p. 34, May 10, 1973. W. ,1. Beyen and O. B. Cecil, Semiconduetor Silieo< I973 (Eds. H. R, Huff and R. R. Burgess) pp. I 16. The Electrochemical Soc. (1973).