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Dopingless ferroelectric tunnel FET architecture for the improvement of performance of dopingless n-channel tunnel FETs
Superlattices and Microstructures 96 (2016) 16e25
Contents lists available at ScienceDirect
Superlattices and Microstructures journal homepage: www.elsevier.com/locate/superlattices
Dopingless ferroelectric tunnel FET architecture for the improvement of performance of dopingless n-channel tunnel FETs Avinash Lahgere*, Meena Panchore, Jawar Singh Department of Electronics and Communication Engineering, PDPM Indian Institute of Information Technology Design and Manufacturing, Jabalpur, MP, 482005 India
a r t i c l e i n f o
a b s t r a c t
Article history: Received 15 February 2016 Received in revised form 14 April 2016 Accepted 3 May 2016 Available online 6 May 2016
In this paper, we propose a novel tunnel field-effect transistor (TFET) based on charge plasma (CP) and negative capacitance (NC) for enhanced ON-current and steep subthreshold swing (SS). It is shown that the replacement of standard insulator for gate stack with ferroelectric (Fe) insulator yields NC and high electric field at the tunneling junction. Similarly, use of dopingless silicon nanowire with CP has a genuine advantage in process engineering. Therefore, combination of both technology boosters (CP and NC) in the proposed device enable low thermal budget, process variation immunity, and excellent electrical characteristics in contrast with its counterpart dopingless (DL) TFET (DL-TFET). An optimized device accomplishes an impressive 10 improvement in on-current, 100 reduced leakage current, 3 more transconductance (gm), and on-off current ratio of ~1011 as compared to DL-TFET. © 2016 Elsevier Ltd. All rights reserved.
Index terms: TFET BTBT Dopingless RDF
1. Introduction Tunnel field-effect transistors (TFETs) represent the most promising steep subthreshold swing (SS) devices, captivating broad attention having potential to operate well below 0.5 Vdd, thereby, offer significant reduction in leakage current and power dissipation per switching activity [1,2]. However, TFETs have a major problem of lower on-current than conventional metal-oxide-semiconductor FETs (MOSFETs), so our proposal is to achieve high on-current as well as steep SS with reduced process variations and fabrication complexity. In this pursuit, many researchers have extensively explored different technology boosters, such as, lower bandgap materials, high-k insulators, ferroelectric (Fe) insulator, nanowires, and strain technology [3e8]. However, they have limitations of either higher leakage current, higher sensitivity towards process parameters, fabrication process complexity, or random dopant fluctuations (RDFs) [9]. In our proposal, two technology boosters have combined for the targeted objectives: (a) charge-plasma (CP) [10], and (b) negative capacitance (NC) [11e16]. For the proposed device structure, we have considered an ultrathin intrinsic (dopingless) silicon nanowire, as a result, sensitivity towards process parameters mainly arises from random dopant fluctuations (RDFs) can be suppressed [17e20]. However, pþ source (S) and nþ drain (D) regions are induced in the silicon film with the help of appropriate workfunction of metal electrodes for S/D region, referred as CP. Therefore, CP significantly reduces the thermal
* Corresponding author. E-mail addresses: [email protected] (A. Lahgere), [email protected] (M. Panchore), [email protected] (J. Singh). http://dx.doi.org/10.1016/j.spmi.2016.05.004 0749-6036/© 2016 Elsevier Ltd. All rights reserved.
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17
budget requirements (ion implantation and complex annealing process or thermal diffusions process), fabrication cost, and complexity [17,18,21]. For enhanced on-current and steep SS, the tunneling efficiency or electric field at tunnel junction needs to be improved. There are several ways by which tunneling efficiency can be improved [3e7], a simplest one is higher operating voltage, however, it degrades subthreshold swing (SS) and low-power applicability in TFETs. Therefore, to preserve the inherent advantages of a TFET the tunneling efficiency under lower bias conditions need to be improved. The introduction of negative gate stack capacitance significantly enhances the electric field at tunnel junction. The application of ferroelectric (Fe) insulator as a standard insulator for gate-stack yields NC and acts as a step-up voltage transformer that provides very good on-current and steep SS [7]. The SS of a conventional TFET can be expressed as [22]:
" SS ¼ ln10
1 dVeff F þ b dF þ 2 Veff dVgs dVgs F
#1 (1)
pffiffiffiffiffiffiffi 3=2 where, Veff is tunneling junction effective bias, F is an electric field, ‘b’ is a material coefficient ð4 m EG =3qZÞ, where m* stands for effective carrier mass, EG is energy gap and Z is the modified Planck constant. From Eq. (1), it is clear that SS of a TFET has no thermal constraint. From Fig. 1 (b) equivalent capacitance model, Vgs and Veff are related by a capacitive voltage divider, and term dVgs/dVeff is given by:
dVgs Cs ¼1þ dVeff Cins
(2)
where, 1/Cins ¼ 1/Coxþ1/Cferro is an equivalent gate-stack insulator capacitance, Cox is gate oxide capacitance, Cferro is negative capacitance offered by ferroelectric insulator. An ordinary capacitance Cs in series with Cox stabilizes the NC offered by ferroelectric insulator Cferro. Owing to NC, the ferroelectric layer acts as a step-up transformer, and thus, Veff > Vgs is achieved. Moreover, this internal voltage amplification in DL-FeTFET that enhances the electric field at tunnel junction can be understood by positive feedback action on the capacitor charge Q due to NC. Imagine a (positive) capacitor Cg (per unit area) that sees a terminal voltage equal to the applied voltage Vgs plus a feedback voltage bFQ proportional to a charge on the capacitor Q (per unit area), such that
Q ¼ Cg
Vgs Veff þ bF Q
(3)
and Cins becomes:
Cins ¼
Q Vgs Veff
¼
Cg 1 bF Cg
Fig. 1. Cross sectional view of (a) conventional DL-TFET [23], and (b) the proposed DL-FeTFET along with its equivalent capacitance model.
(4)
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From Eq. (4), the negative gate-stack capacitance (Cins) can only be established when the feedback voltage (bFCg) is greater than one (i.e. (bFCg > 1)). In other words, for NC there must be a positive feedback that will step-up the internal voltage at tunnel junction, from Eqs. (2) and (4):
dVgs Cs ¼1 b Cg 1 dVeff Cg F
(5)
From Eq. (5), dVgs/dVeff decreases due to positive feedback voltage (bFCg > 1), which is directly related to SS, as evident from Eq. (1), hence, SS reduces significantly. Further, from Eq. (5) a positive feedback voltage allows internal voltage amplification (i.e. Veff > Vgs) that accomplishes the step-up voltage transformer action that exaggerates the electric field at tunnel junction, results, higher on-current in the device. 2. Device geometry and simulation setup Fig. 1(a) and (b) show the cross-sectional view of the conventional dopingless-TFET (DL-TFET) and the proposed dopingless-ferroelectric TFET (DL-FeTFET) along with its simplified capacitance model, respectively. The simulation parameters for DL-TFET are [23]: (a) Si film thickness (TSi) ¼ 10 nm, (b) uniform lightly p-type doped Si film is considered from drain to source (NA) ¼ 1 1015 cm3, (c) effective gate oxide (SiO2) thickness (Tox) ¼ 0.8 nm, (d) channel length (LG) ¼ 50 nm, (e) gate work function ¼ 4.3 eV, and (f) the spacer thickness at source (SGAP,S) and drain (SGAP,D) sides are kept 5 nm and 15 nm, respectively. The spacer thickness at the drain side (SGAP,D) is approximately equal to the depletion region width on the drainchannel side in a conventional doped TFET [23]. Moreover, for inducing the pþ source and nþ drain regions, platinum (workfunction ¼ 5.93 eV) and hafnium (workfunction ¼ 3.9 eV), respectively, were employed as S/D metal electrodes, as shown in Fig. 1. The simulation parameters for the proposed DL-FeTFET are same as above except two differences: (1) ferroelectric layer of lead zirconium titanate (PbZrTiO3) or (PZT) gate stack having thickness (Tfe) ¼ 3 nm is deposited over gate oxide and (2) the S/D contacts are used at both sides (top and bottom). In the proposed DL-FeTFET, S/D contacts are employed at both sides (top and bottom) that make uniform carrier concentration in silicon film along with y-direction. However, in DLTFET, the source and drain regions are non-uniformly doped in the y-direction across the thickness of the silicon film due presence of metal electrode on top side of S/D contact. Hence, in order to obtain uniform carrier concentrations in the ydirection we have used the S/D contacts at both sides [23,24]. Moreover, To fulfill the CP requirements, Si film thickness must qffiffiffiffiffiffiffi si Vt be less than the Debye length [10], i.e., LD ¼ εqN , where εSi is a dielectric constant of Si, Vt is a thermal voltage, and NA is a A carrier concentration in the body. The computer-aided design (TCAD) tool ATLAS is used to verify the behavior of the proposed device [25]. The non-local band-to-band tunneling (BTBT) model is enabled to account tunneling mechanism [23]. To calculate the tunneling probability using the electron-hole wave vector throughout the tunneling path, the non-local model uses Wentzel-KramerBrillouin (WKB) approximation. In addition, to incorporate the Fe properties of gate stack that leads to NC, we have enabled Ferro model in our simulation. Since, ferroelectric materials exhibit high dielectric constants, polarization and hysteresis, hence, to simulate these effects, a modified version of the ferroelectric model from Miller [26] has been implemented. Also to enable this model its remnant polarization Pr is taken as 4 107 C/cm2, saturation polarization Ps as 5 107 C/cm2 and critical electrical field Fc as 1 105 V/cm, were considered for simulation [25,27]. In addition, Choi et al. [28] have shown that the quantum confinement effect (QCE) is not significant for film greater than 7 nm; hence, QCE is not incorporated in our simulations. Further, trap assisted tunneling (TAT) model given by Schenk is also considered [25]. The results of the work reported in [23] are first reproduced to calibrate the model parameters. 3. Simulation results and discussion 3.1. Carrier concentration plot In the proposed DL-FeTFET, a thin dopingless Si film is transformed to an nþeiepþ like structure using charge plasma (CP) concept, where metal electrodes of appropriate work function (platinum and hafnium) are employed at S/D region, as a result, we get abrupt electron and hole carrier concentration underneath S/D region, as shown in Fig. 2. It is worth mention that in on-state, depletion region underneath of gate electrode vanishes and induces exactly nþ-type region in channel, which is identical to the conventional DL-TFET, as shown in Fig. 2(b). One can observed that the proposed device exhibits much sharper doping profile (carrier concentration) under off- and on-states as compared to conventional DL-TFET. Hence, proposed approach ensures an abrupt p-n junction for tunneling of electron carriers from valence band (VB) of pþ to conduction band (CB) of intrinsic region (i). 3.2. Energy band diagram The CB and the VB energies in off- and on-states are shown in Fig. 3. In off-state, probability of electron tunneling from VB of pþ to CB of i is very low because of high tunneling energy barrier width at gate-source junction. However, in on-state CB and
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Fig. 2. Electron and hole carrier concentration under (a) off-state (Vgs ¼ 0 V, Vds ¼ 1 V), and (b) on-state (Vgs ¼ 1 V, Vds ¼ 1 V).
VB energies in i region get aligned with CB and VB energies of nþ region, as a result, tunneling energy barrier width is reduced significantly, which makes higher probability of electron tunneling from VB of pþ into CB of i region. In addition, an inset in Fig. 3(b) provides a closer look of tunneling energy barrier width for both devices. One can observe that at gate-source junction the tunneling energy barrier width for Fe gate stack (Wt,Fe) is much smaller than the non-Fe gate stack (Wt). The negative capacitance (NC) amplifies the internal voltage in on-state, which consequently, intensifies the electric field at the tunneling junction and reduces the tunneling energy barrier width (i.e. Wt,Fe < Wt), as a result, enhanced on-state current. Furthermore, it is worth mention that in off-state the Fe gate stack in the DL-FeTFET enhances the depletion region underneath the gate electrode, thereby, drastically reduces the off-state current. 3.3. Electric field and hysteresis characteristics The electric field at tunnel junction for both the conventional DL-TFET and the proposed DL-FeTFET devices is shown in Fig. 4. One can observe that for the proposed DL-FeTFET electric field at tunnel junction is 20% higher than the conventional DL-TFET under same bias conditions. The higher electric field at tunnel junction lowers the tunneling energy barrier width, as shown in Fig. 3(b), consequently, an enhanced on-current and the steep SS. This happens due to the negative capacitance behavior, which is stabilized by the depolarization field of the series capacitor (Cs) and results internal voltage amplification [7,8]. In addition, ferroelectric material exhibits hysteresis characteristic, hence, we have incorporated transfer characteristic of the proposed DL-FeTFET under forward and reverse voltage sweeps, as shown in Fig. 5. This shows that the proposed device has a unique hysteresis property. 3.4. Comparison of the transfer characteristics and transconductance For quantitative comparison, transfer characteristics of both devices are extracted, as shown in Fig. 6(a). One can observe that the DL-FeTFET yields almost 10 improvement in Ion and 100 reduced leakage current (Ioff) as compared to its counterpart DL-TFET under same bias. This happens because Fe gate stack acts as a step-up voltage transformer, and thus intensifies the electric field at the tunneling junction. One can also observe that the relative independence of Ids on Vds at low
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Fig. 3. Energy band diagram for both DL-TFET and DL-FeTFET under (a) off-state (Vgs ¼ 0 V, Vds ¼ 1 V), and (b) on-state (Vgs ¼ 1 V, Vds ¼ 1 V).
Vgs (i.e. Vgs<0.6 V) is apparent and can be observed due to the Vds effect on ‘tunneling barrier width narrowing’ that saturates below 0.6 V. However, barrier tunneling (high Vgs>0.6 V) experiences a modulation, which is consistent with the past reported results [29]. In addition, we have investigated the impact of NC on transconductance (gm) of the proposed DL-FeTFET and compared with the conventional DL-TFET for different Vds, as it is an important parameter for analog applications, as shown in Fig. 6(b). For Vds ¼ 1.0 V, the gm of DL-FeTFET is about 3 more than the DL-TFET. This happens due to higher tunneling rate because of internal voltage amplification. 3.5. Impact of the gate length scaling and trap assisted tunneling (TAT) Fig. 7 shows the effect of gate-length scaling on the transfer characteristics of the DL-TFET and the proposed DL-FeTFET. For scaling of gate length, we have kept both the spacer thicknesses and the overall device length constant. One can observe that
Fig. 4. (a) Electric field for the DL-TFET and the proposed DL-FeTFET at Vcg ¼ 1.0 V and Vds ¼ 1.2 V.
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Fig. 5. Transfer characteristic of DL-FeTFET under forward and reverse sweep at Vds ¼ 1.0 V.
the scaling of the gate length causes an increment in Ioff and reduction in Ion. This is because of decrement in the tunneling barrier width at the channel-source junction, which is consistent with the previously reported results [19]. Moreover, the proposed DL-FeTFET exhibits an enhancement in Ion as compared to the DL-TFET at 20 nm gate length regime. Hence, the proposed DL-FeTFET could be a possible candidate for the 20 nm gate length regime. In addition, Fig. 7(b) shows the transfer characteristics for the proposed DL-FeTFET and the conventional DL-TFET with the same device parameters with or without inclusion of trap assisted tunneling (TAT) model. It can be observed that the inclusion of TAT model increases the Ioff as compared to the case without the use of TAT model for both devices.
Fig. 6. Transfer characteristic comparison (a) DL-TEFT and DL-FeTFET at Vds ¼ 1.0 V and 0.5 V, (b) transconductance comparison between DLTFET and DL-FeTFET at Vds ¼ 1.0 V and 0.8 V.
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(a)
(b) Fig. 7. Impact of (a) the gate-length scaling and (b) the TAT model, on transfer characteristics of the DL-TFET and the proposed DL-FeTFET.
Fig. 8. Output characteristics of (a) DL-TFET and (b) DL-FeTFET for different gate voltages.
3.6. Comparison of the output characteristics Fig. 8 shows the output characteristics of the DL-TFET and the proposed DL-FeTFET for different values of gate voltages. In the triode region, as we increase drain voltage, the higher number of carriers tunnels’ and establishes an exponential relationship with Ids due to drain-induced barrier thinning. A very good saturation region is also observed due to less reliant tunneling width with Vds.
3.7. Impact of the source side spacer thickness The impact of source side spacer thickness (SGAP,S) on SSavg, and SSpoint is observed in Fig. 9. An increment in SGAP,S, causes increment in SSavg and SSpoint due to enhanced energy barrier width and reduced tunneling probability of electrons. In
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23
Fig. 9. Impact of SGAP,S on (a) SSavg, and (b) SSpoint.
addition, SGAP,S scaling (20 nme5 nm) in the proposed device yields better SSavg and SSpoint, for example, SSpoint for the proposed DL-FeTFET is approximately 2 smaller than the conventional DL-TFET for SGAP,S ¼ 5 nm, as shown in Fig. 9(b).
3.8. Impact of the zero field relative permittivity To further substantiate the NC mechanism for the proposed DL-FeTFET device, impact of zero field relative permittivity (ferro.eps) is considered in Fig. 10(a) and (b). One can observe that with higher zero field relative permittivity there is a significant improvement in the Ion and Ion/Ioff ratio, mainly due to higher gate coupling and reduced energy barrier width which is coherent with past reported results. Moreover, inset in Fig. 10(b) shows the dependence of the energy barrier width on the gate voltage for different zero field relative permittivity.
Fig. 10. Impact of zero field relative permittivity on (a) transfer characteristic, (b) Ion/Ioff.
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Fig. 11. Tfe impact on (a) SSpoint, (b) Ion, (c) Vth, (d) Ion/Ioff.
3.9. Impact of the ferroelectric material thickness Furthermore, thickness of ferroelectric material (Tfe) also influences the NC, hence, device characteristics, such as Ion/Ioff ratio, SSpoint, and Vth. Fig. 11(a) and (b) show the impact of Tfe over SSpoint and Ion for the DL-FeTFET, it can be infer that higher Tfe causes increment in SSpoint and decrement in Ion. These results are consistent with NC mechanism and cuts down the Veff with Tfe scaling from 3 nm to 23 nm. Similarly, Fig. 11(c) and (d) show decrement in Vth and increment in Ion/Ioff ratio with Tfe scaling which is similar to the past reported results. 4. Conclusion The combination of CP (for process variation immunity) and NC (for step-up voltage action) has significantly improved the electrical properties, such as Ion, Ioff, SS and gm of the DL-FeTFET. The SSpoint and gm of the DL-FeTFET are approximately 2 and 3 higher than the DL-TFET, respectively. Hence, the DL-FeTFET is a potential candidate for ultralow power applications. The paper also highlighted advantages of DL-FeTFET towards immunity to RDFs and short channel effects. Further, it is free from ion-implantation and thermal annealing process. Hence, proposed results may provide incentives and guidelines for further research and experimental exploration of the DL-FeTFET for circuit and system level.
References [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
International Technology Roadmaps for Semiconductor, ITRS, 2012. A.M. Ionescu, H. Riel, Tunnel field-effect transistors as energy efficient electronic switches, Nature 479 (Nov. 2011) 329e337. K. Boucart, A.M. Ionescu, Double gate tunnel FET with high-k gate dielectric, IEEE Trans. Electron Devices 54 (7) (Jul. 2007) 1725e1733. A.S. Verhulst, et al., Complementary silicon-based hetero-structure tunnel-FETs with high tunnel rates, IEEE Electron Device Lett. 29 (12) (Dec. 2008) 1398e1401. T. Krishnamohan, et al., High-mobility low band-to-band tunneling strained-germanium double-gate heterostructure FETs: simulations, IEEE Trans. Electron Devices 53 (5) (May 2006) 1000e1009. Z.X. Chen, et al., Demonstration of tunneling FETs based on highly scalable vertical silicon nanowires, IEEE Electron Device Lett. 30 (7) (July 2009) 754e756. S. Salahuddin, Use of negative capacitance to provide voltage amplification for low power nanoscale devices, Nano Lett. 8 (2) (2008) 405e410. S. Salahuddin, S. Datta, Can the Subthreshold Swing in a Classical FET Be Lowered below 60 mV/decade?, IEDM Tech. Dig., San Francisco, CA, USA, 2008, pp. 693e696. N. Damrongplasit, S.H. Kim, T.J.K. Liu, Study of random dopant fluctuation induced variability in the raised-Ge-source TFET, IEEE Electron Device Lett. 34 (2) (Feb. 2013) 184e186. R.J.E. Hueting, et al., Charge plasma P-N diode, IEEE Electron Device Lett. 29 (12) (Dec. 2008) 1367e1368. G.A. Salvatore, D. Bouvet, A.M. Ionescu, in: Demonstration of Subthrehold Swing Smaller than 60 mV/decade in Fe-FET with P(VDF-TrFE)/SiO2 Gate Stack, IEEE International Electron Devices Meeting, San Francisco, USA, Dec. 2008, pp. 15e17.
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25
[12] M.H. Lee, et al., Ferroelectric Negative Capacitance Hetero-tunnel Field-effect-transistors with Internal Voltage Amplification, IEDM Tech. Dig., Washington, DC, USA, 2013, pp. 104e107. [13] A. Rusu, G.A. Salvatore, D. Jimenez, A.M. Ionescu, Metal-ferroelectric-metal-oxide-semiconductor Field Effect Transistor with Sub-60mV/decade Subthreshold Swing and Internal Voltage Amplification, IEDM Tech. Dig., San Francisco, CA, USA, 2010, pp. 395e398. [14] C.H. Cheng, A. Chin, Low-voltage steep turn-on p-MOSFET using ferroelectric high-k gate dielectric, IEEE Electron Device Lett. 35 (2) (Feb. 2014) 274e276. [15] M.H. Lee, et al., Ferroelectric gate tunnel field-effect transistors with low-power steep turn-On, AIP Adv. 4 (10) (2014) 107117. [16] M. Kumar, S. Jit, A novel four-terminal ferroelectric tunnel fet for quasi-ideal switch, IEEE Trans. Nanotechnol. 14 (4) (July 2015) 600e602. [17] C. Sahu, J. Singh, Charge-plasma based process variation immune junctionless transistor, IEEE Electron Device Lett. 35 (3) (March 2014) 411e413. [18] C. Sahu, J. Singh, Potential benefits and sensitivity analysis of dopingless transistor for low power applications, IEEE Trans. Electron Devices 62 (3) (March 2015) 729e735. [19] A. Lahgere, C. Sahu, J. Singh, PVT-aware design of dopingless dynamically configurable tunnel FET, IEEE Trans. Electron Devices 62 (8) (Aug. 2015) 2404e2409. [20] A. Lahgere, C. Sahu, J. Singh, Electrically doped dynamically configurable field-effect transistor for low-power and high-performance applications, IET Electron. Lett. 51 (16) (June 2015) 1284e1286. [21] W.H. Teh, A. Trigg, C.H. Tung, R. Kumar, N. Balasubramanian, D.L. Kwong, 200 mm wafer-scale epitaxial transfer of single crystal Si on glass by anodic bonding of silicon-on-insulator wafers, Appl. Phys. Lett. 87 (2005) article no. 073107. [22] Q. Zhang, W. Zhao, A. Seabaugh, Low-subthreshold-swing tunnel transistors, IEEE Electron. Device Lett. (2006) 27. [23] M.J. Kumar, S. Janardhanan, Doping-less tunnel field effect transistor: design and investigation, IEEE Trans. Electron. Devices 60 (10) (Oct. 2013) 3285e3290. [24] S. Ramaswamy, M.J. Kumar, Junctionless impact ionization MOS: proposal and investigation, IEEE Trans. Electron Devices 61 (12) (Dec. 2014) 4295e4298. [25] ATLAS Device Simulation Software, Silvaco Int., Santa Clara, CA, USA, 2015. [26] S.L. Miller, et al., Device modeling of ferroelectric capacitors, J. Appl. Phys. 68 (12) (Dec. 1990) 15. [27] S.L. Miller, P.J. McWhorter, Physic of the ferroelectric non-volitile memory field effect transistor, J. Appl. Phys. 72 (12) (Dec. 1992) 5999e6010, 15. [28] S.-J. Choi, D.-I. Moon, S. Kim, J.P. Duarte, Y.-K. Choi, Sensitivity of threshold voltage to nanowire width variation in junctionless transistors, IEEE Electron Device Lett. 32 (2) (Feb. 2011) 125e127. [29] L. Lattanzio, L. De Michielis, A. Biswas, A.M. Ionescu, Abrupt switch based on internally combined Band-To-Band and Barrier Tunneling mechanisms, in: European Solid State Device Research Conference, 2010, pp. 353e356.
Contents lists available at ScienceDirect
Superlattices and Microstructures journal homepage: www.elsevier.com/locate/superlattices
Dopingless ferroelectric tunnel FET architecture for the improvement of performance of dopingless n-channel tunnel FETs Avinash Lahgere*, Meena Panchore, Jawar Singh Department of Electronics and Communication Engineering, PDPM Indian Institute of Information Technology Design and Manufacturing, Jabalpur, MP, 482005 India
a r t i c l e i n f o
a b s t r a c t
Article history: Received 15 February 2016 Received in revised form 14 April 2016 Accepted 3 May 2016 Available online 6 May 2016
In this paper, we propose a novel tunnel field-effect transistor (TFET) based on charge plasma (CP) and negative capacitance (NC) for enhanced ON-current and steep subthreshold swing (SS). It is shown that the replacement of standard insulator for gate stack with ferroelectric (Fe) insulator yields NC and high electric field at the tunneling junction. Similarly, use of dopingless silicon nanowire with CP has a genuine advantage in process engineering. Therefore, combination of both technology boosters (CP and NC) in the proposed device enable low thermal budget, process variation immunity, and excellent electrical characteristics in contrast with its counterpart dopingless (DL) TFET (DL-TFET). An optimized device accomplishes an impressive 10 improvement in on-current, 100 reduced leakage current, 3 more transconductance (gm), and on-off current ratio of ~1011 as compared to DL-TFET. © 2016 Elsevier Ltd. All rights reserved.
Index terms: TFET BTBT Dopingless RDF
1. Introduction Tunnel field-effect transistors (TFETs) represent the most promising steep subthreshold swing (SS) devices, captivating broad attention having potential to operate well below 0.5 Vdd, thereby, offer significant reduction in leakage current and power dissipation per switching activity [1,2]. However, TFETs have a major problem of lower on-current than conventional metal-oxide-semiconductor FETs (MOSFETs), so our proposal is to achieve high on-current as well as steep SS with reduced process variations and fabrication complexity. In this pursuit, many researchers have extensively explored different technology boosters, such as, lower bandgap materials, high-k insulators, ferroelectric (Fe) insulator, nanowires, and strain technology [3e8]. However, they have limitations of either higher leakage current, higher sensitivity towards process parameters, fabrication process complexity, or random dopant fluctuations (RDFs) [9]. In our proposal, two technology boosters have combined for the targeted objectives: (a) charge-plasma (CP) [10], and (b) negative capacitance (NC) [11e16]. For the proposed device structure, we have considered an ultrathin intrinsic (dopingless) silicon nanowire, as a result, sensitivity towards process parameters mainly arises from random dopant fluctuations (RDFs) can be suppressed [17e20]. However, pþ source (S) and nþ drain (D) regions are induced in the silicon film with the help of appropriate workfunction of metal electrodes for S/D region, referred as CP. Therefore, CP significantly reduces the thermal
* Corresponding author. E-mail addresses: [email protected] (A. Lahgere), [email protected] (M. Panchore), [email protected] (J. Singh). http://dx.doi.org/10.1016/j.spmi.2016.05.004 0749-6036/© 2016 Elsevier Ltd. All rights reserved.
A. Lahgere et al. / Superlattices and Microstructures 96 (2016) 16e25
17
budget requirements (ion implantation and complex annealing process or thermal diffusions process), fabrication cost, and complexity [17,18,21]. For enhanced on-current and steep SS, the tunneling efficiency or electric field at tunnel junction needs to be improved. There are several ways by which tunneling efficiency can be improved [3e7], a simplest one is higher operating voltage, however, it degrades subthreshold swing (SS) and low-power applicability in TFETs. Therefore, to preserve the inherent advantages of a TFET the tunneling efficiency under lower bias conditions need to be improved. The introduction of negative gate stack capacitance significantly enhances the electric field at tunnel junction. The application of ferroelectric (Fe) insulator as a standard insulator for gate-stack yields NC and acts as a step-up voltage transformer that provides very good on-current and steep SS [7]. The SS of a conventional TFET can be expressed as [22]:
" SS ¼ ln10
1 dVeff F þ b dF þ 2 Veff dVgs dVgs F
#1 (1)
pffiffiffiffiffiffiffi 3=2 where, Veff is tunneling junction effective bias, F is an electric field, ‘b’ is a material coefficient ð4 m EG =3qZÞ, where m* stands for effective carrier mass, EG is energy gap and Z is the modified Planck constant. From Eq. (1), it is clear that SS of a TFET has no thermal constraint. From Fig. 1 (b) equivalent capacitance model, Vgs and Veff are related by a capacitive voltage divider, and term dVgs/dVeff is given by:
dVgs Cs ¼1þ dVeff Cins
(2)
where, 1/Cins ¼ 1/Coxþ1/Cferro is an equivalent gate-stack insulator capacitance, Cox is gate oxide capacitance, Cferro is negative capacitance offered by ferroelectric insulator. An ordinary capacitance Cs in series with Cox stabilizes the NC offered by ferroelectric insulator Cferro. Owing to NC, the ferroelectric layer acts as a step-up transformer, and thus, Veff > Vgs is achieved. Moreover, this internal voltage amplification in DL-FeTFET that enhances the electric field at tunnel junction can be understood by positive feedback action on the capacitor charge Q due to NC. Imagine a (positive) capacitor Cg (per unit area) that sees a terminal voltage equal to the applied voltage Vgs plus a feedback voltage bFQ proportional to a charge on the capacitor Q (per unit area), such that
Q ¼ Cg
Vgs Veff þ bF Q
(3)
and Cins becomes:
Cins ¼
Q Vgs Veff
¼
Cg 1 bF Cg
Fig. 1. Cross sectional view of (a) conventional DL-TFET [23], and (b) the proposed DL-FeTFET along with its equivalent capacitance model.
(4)
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From Eq. (4), the negative gate-stack capacitance (Cins) can only be established when the feedback voltage (bFCg) is greater than one (i.e. (bFCg > 1)). In other words, for NC there must be a positive feedback that will step-up the internal voltage at tunnel junction, from Eqs. (2) and (4):
dVgs Cs ¼1 b Cg 1 dVeff Cg F
(5)
From Eq. (5), dVgs/dVeff decreases due to positive feedback voltage (bFCg > 1), which is directly related to SS, as evident from Eq. (1), hence, SS reduces significantly. Further, from Eq. (5) a positive feedback voltage allows internal voltage amplification (i.e. Veff > Vgs) that accomplishes the step-up voltage transformer action that exaggerates the electric field at tunnel junction, results, higher on-current in the device. 2. Device geometry and simulation setup Fig. 1(a) and (b) show the cross-sectional view of the conventional dopingless-TFET (DL-TFET) and the proposed dopingless-ferroelectric TFET (DL-FeTFET) along with its simplified capacitance model, respectively. The simulation parameters for DL-TFET are [23]: (a) Si film thickness (TSi) ¼ 10 nm, (b) uniform lightly p-type doped Si film is considered from drain to source (NA) ¼ 1 1015 cm3, (c) effective gate oxide (SiO2) thickness (Tox) ¼ 0.8 nm, (d) channel length (LG) ¼ 50 nm, (e) gate work function ¼ 4.3 eV, and (f) the spacer thickness at source (SGAP,S) and drain (SGAP,D) sides are kept 5 nm and 15 nm, respectively. The spacer thickness at the drain side (SGAP,D) is approximately equal to the depletion region width on the drainchannel side in a conventional doped TFET [23]. Moreover, for inducing the pþ source and nþ drain regions, platinum (workfunction ¼ 5.93 eV) and hafnium (workfunction ¼ 3.9 eV), respectively, were employed as S/D metal electrodes, as shown in Fig. 1. The simulation parameters for the proposed DL-FeTFET are same as above except two differences: (1) ferroelectric layer of lead zirconium titanate (PbZrTiO3) or (PZT) gate stack having thickness (Tfe) ¼ 3 nm is deposited over gate oxide and (2) the S/D contacts are used at both sides (top and bottom). In the proposed DL-FeTFET, S/D contacts are employed at both sides (top and bottom) that make uniform carrier concentration in silicon film along with y-direction. However, in DLTFET, the source and drain regions are non-uniformly doped in the y-direction across the thickness of the silicon film due presence of metal electrode on top side of S/D contact. Hence, in order to obtain uniform carrier concentrations in the ydirection we have used the S/D contacts at both sides [23,24]. Moreover, To fulfill the CP requirements, Si film thickness must qffiffiffiffiffiffiffi si Vt be less than the Debye length [10], i.e., LD ¼ εqN , where εSi is a dielectric constant of Si, Vt is a thermal voltage, and NA is a A carrier concentration in the body. The computer-aided design (TCAD) tool ATLAS is used to verify the behavior of the proposed device [25]. The non-local band-to-band tunneling (BTBT) model is enabled to account tunneling mechanism [23]. To calculate the tunneling probability using the electron-hole wave vector throughout the tunneling path, the non-local model uses Wentzel-KramerBrillouin (WKB) approximation. In addition, to incorporate the Fe properties of gate stack that leads to NC, we have enabled Ferro model in our simulation. Since, ferroelectric materials exhibit high dielectric constants, polarization and hysteresis, hence, to simulate these effects, a modified version of the ferroelectric model from Miller [26] has been implemented. Also to enable this model its remnant polarization Pr is taken as 4 107 C/cm2, saturation polarization Ps as 5 107 C/cm2 and critical electrical field Fc as 1 105 V/cm, were considered for simulation [25,27]. In addition, Choi et al. [28] have shown that the quantum confinement effect (QCE) is not significant for film greater than 7 nm; hence, QCE is not incorporated in our simulations. Further, trap assisted tunneling (TAT) model given by Schenk is also considered [25]. The results of the work reported in [23] are first reproduced to calibrate the model parameters. 3. Simulation results and discussion 3.1. Carrier concentration plot In the proposed DL-FeTFET, a thin dopingless Si film is transformed to an nþeiepþ like structure using charge plasma (CP) concept, where metal electrodes of appropriate work function (platinum and hafnium) are employed at S/D region, as a result, we get abrupt electron and hole carrier concentration underneath S/D region, as shown in Fig. 2. It is worth mention that in on-state, depletion region underneath of gate electrode vanishes and induces exactly nþ-type region in channel, which is identical to the conventional DL-TFET, as shown in Fig. 2(b). One can observed that the proposed device exhibits much sharper doping profile (carrier concentration) under off- and on-states as compared to conventional DL-TFET. Hence, proposed approach ensures an abrupt p-n junction for tunneling of electron carriers from valence band (VB) of pþ to conduction band (CB) of intrinsic region (i). 3.2. Energy band diagram The CB and the VB energies in off- and on-states are shown in Fig. 3. In off-state, probability of electron tunneling from VB of pþ to CB of i is very low because of high tunneling energy barrier width at gate-source junction. However, in on-state CB and
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Fig. 2. Electron and hole carrier concentration under (a) off-state (Vgs ¼ 0 V, Vds ¼ 1 V), and (b) on-state (Vgs ¼ 1 V, Vds ¼ 1 V).
VB energies in i region get aligned with CB and VB energies of nþ region, as a result, tunneling energy barrier width is reduced significantly, which makes higher probability of electron tunneling from VB of pþ into CB of i region. In addition, an inset in Fig. 3(b) provides a closer look of tunneling energy barrier width for both devices. One can observe that at gate-source junction the tunneling energy barrier width for Fe gate stack (Wt,Fe) is much smaller than the non-Fe gate stack (Wt). The negative capacitance (NC) amplifies the internal voltage in on-state, which consequently, intensifies the electric field at the tunneling junction and reduces the tunneling energy barrier width (i.e. Wt,Fe < Wt), as a result, enhanced on-state current. Furthermore, it is worth mention that in off-state the Fe gate stack in the DL-FeTFET enhances the depletion region underneath the gate electrode, thereby, drastically reduces the off-state current. 3.3. Electric field and hysteresis characteristics The electric field at tunnel junction for both the conventional DL-TFET and the proposed DL-FeTFET devices is shown in Fig. 4. One can observe that for the proposed DL-FeTFET electric field at tunnel junction is 20% higher than the conventional DL-TFET under same bias conditions. The higher electric field at tunnel junction lowers the tunneling energy barrier width, as shown in Fig. 3(b), consequently, an enhanced on-current and the steep SS. This happens due to the negative capacitance behavior, which is stabilized by the depolarization field of the series capacitor (Cs) and results internal voltage amplification [7,8]. In addition, ferroelectric material exhibits hysteresis characteristic, hence, we have incorporated transfer characteristic of the proposed DL-FeTFET under forward and reverse voltage sweeps, as shown in Fig. 5. This shows that the proposed device has a unique hysteresis property. 3.4. Comparison of the transfer characteristics and transconductance For quantitative comparison, transfer characteristics of both devices are extracted, as shown in Fig. 6(a). One can observe that the DL-FeTFET yields almost 10 improvement in Ion and 100 reduced leakage current (Ioff) as compared to its counterpart DL-TFET under same bias. This happens because Fe gate stack acts as a step-up voltage transformer, and thus intensifies the electric field at the tunneling junction. One can also observe that the relative independence of Ids on Vds at low
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Fig. 3. Energy band diagram for both DL-TFET and DL-FeTFET under (a) off-state (Vgs ¼ 0 V, Vds ¼ 1 V), and (b) on-state (Vgs ¼ 1 V, Vds ¼ 1 V).
Vgs (i.e. Vgs<0.6 V) is apparent and can be observed due to the Vds effect on ‘tunneling barrier width narrowing’ that saturates below 0.6 V. However, barrier tunneling (high Vgs>0.6 V) experiences a modulation, which is consistent with the past reported results [29]. In addition, we have investigated the impact of NC on transconductance (gm) of the proposed DL-FeTFET and compared with the conventional DL-TFET for different Vds, as it is an important parameter for analog applications, as shown in Fig. 6(b). For Vds ¼ 1.0 V, the gm of DL-FeTFET is about 3 more than the DL-TFET. This happens due to higher tunneling rate because of internal voltage amplification. 3.5. Impact of the gate length scaling and trap assisted tunneling (TAT) Fig. 7 shows the effect of gate-length scaling on the transfer characteristics of the DL-TFET and the proposed DL-FeTFET. For scaling of gate length, we have kept both the spacer thicknesses and the overall device length constant. One can observe that
Fig. 4. (a) Electric field for the DL-TFET and the proposed DL-FeTFET at Vcg ¼ 1.0 V and Vds ¼ 1.2 V.
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Fig. 5. Transfer characteristic of DL-FeTFET under forward and reverse sweep at Vds ¼ 1.0 V.
the scaling of the gate length causes an increment in Ioff and reduction in Ion. This is because of decrement in the tunneling barrier width at the channel-source junction, which is consistent with the previously reported results [19]. Moreover, the proposed DL-FeTFET exhibits an enhancement in Ion as compared to the DL-TFET at 20 nm gate length regime. Hence, the proposed DL-FeTFET could be a possible candidate for the 20 nm gate length regime. In addition, Fig. 7(b) shows the transfer characteristics for the proposed DL-FeTFET and the conventional DL-TFET with the same device parameters with or without inclusion of trap assisted tunneling (TAT) model. It can be observed that the inclusion of TAT model increases the Ioff as compared to the case without the use of TAT model for both devices.
Fig. 6. Transfer characteristic comparison (a) DL-TEFT and DL-FeTFET at Vds ¼ 1.0 V and 0.5 V, (b) transconductance comparison between DLTFET and DL-FeTFET at Vds ¼ 1.0 V and 0.8 V.
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(a)
(b) Fig. 7. Impact of (a) the gate-length scaling and (b) the TAT model, on transfer characteristics of the DL-TFET and the proposed DL-FeTFET.
Fig. 8. Output characteristics of (a) DL-TFET and (b) DL-FeTFET for different gate voltages.
3.6. Comparison of the output characteristics Fig. 8 shows the output characteristics of the DL-TFET and the proposed DL-FeTFET for different values of gate voltages. In the triode region, as we increase drain voltage, the higher number of carriers tunnels’ and establishes an exponential relationship with Ids due to drain-induced barrier thinning. A very good saturation region is also observed due to less reliant tunneling width with Vds.
3.7. Impact of the source side spacer thickness The impact of source side spacer thickness (SGAP,S) on SSavg, and SSpoint is observed in Fig. 9. An increment in SGAP,S, causes increment in SSavg and SSpoint due to enhanced energy barrier width and reduced tunneling probability of electrons. In
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Fig. 9. Impact of SGAP,S on (a) SSavg, and (b) SSpoint.
addition, SGAP,S scaling (20 nme5 nm) in the proposed device yields better SSavg and SSpoint, for example, SSpoint for the proposed DL-FeTFET is approximately 2 smaller than the conventional DL-TFET for SGAP,S ¼ 5 nm, as shown in Fig. 9(b).
3.8. Impact of the zero field relative permittivity To further substantiate the NC mechanism for the proposed DL-FeTFET device, impact of zero field relative permittivity (ferro.eps) is considered in Fig. 10(a) and (b). One can observe that with higher zero field relative permittivity there is a significant improvement in the Ion and Ion/Ioff ratio, mainly due to higher gate coupling and reduced energy barrier width which is coherent with past reported results. Moreover, inset in Fig. 10(b) shows the dependence of the energy barrier width on the gate voltage for different zero field relative permittivity.
Fig. 10. Impact of zero field relative permittivity on (a) transfer characteristic, (b) Ion/Ioff.
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Fig. 11. Tfe impact on (a) SSpoint, (b) Ion, (c) Vth, (d) Ion/Ioff.
3.9. Impact of the ferroelectric material thickness Furthermore, thickness of ferroelectric material (Tfe) also influences the NC, hence, device characteristics, such as Ion/Ioff ratio, SSpoint, and Vth. Fig. 11(a) and (b) show the impact of Tfe over SSpoint and Ion for the DL-FeTFET, it can be infer that higher Tfe causes increment in SSpoint and decrement in Ion. These results are consistent with NC mechanism and cuts down the Veff with Tfe scaling from 3 nm to 23 nm. Similarly, Fig. 11(c) and (d) show decrement in Vth and increment in Ion/Ioff ratio with Tfe scaling which is similar to the past reported results. 4. Conclusion The combination of CP (for process variation immunity) and NC (for step-up voltage action) has significantly improved the electrical properties, such as Ion, Ioff, SS and gm of the DL-FeTFET. The SSpoint and gm of the DL-FeTFET are approximately 2 and 3 higher than the DL-TFET, respectively. Hence, the DL-FeTFET is a potential candidate for ultralow power applications. The paper also highlighted advantages of DL-FeTFET towards immunity to RDFs and short channel effects. Further, it is free from ion-implantation and thermal annealing process. Hence, proposed results may provide incentives and guidelines for further research and experimental exploration of the DL-FeTFET for circuit and system level.
References [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
International Technology Roadmaps for Semiconductor, ITRS, 2012. A.M. Ionescu, H. Riel, Tunnel field-effect transistors as energy efficient electronic switches, Nature 479 (Nov. 2011) 329e337. K. Boucart, A.M. Ionescu, Double gate tunnel FET with high-k gate dielectric, IEEE Trans. Electron Devices 54 (7) (Jul. 2007) 1725e1733. A.S. Verhulst, et al., Complementary silicon-based hetero-structure tunnel-FETs with high tunnel rates, IEEE Electron Device Lett. 29 (12) (Dec. 2008) 1398e1401. T. Krishnamohan, et al., High-mobility low band-to-band tunneling strained-germanium double-gate heterostructure FETs: simulations, IEEE Trans. Electron Devices 53 (5) (May 2006) 1000e1009. Z.X. Chen, et al., Demonstration of tunneling FETs based on highly scalable vertical silicon nanowires, IEEE Electron Device Lett. 30 (7) (July 2009) 754e756. S. Salahuddin, Use of negative capacitance to provide voltage amplification for low power nanoscale devices, Nano Lett. 8 (2) (2008) 405e410. S. Salahuddin, S. Datta, Can the Subthreshold Swing in a Classical FET Be Lowered below 60 mV/decade?, IEDM Tech. Dig., San Francisco, CA, USA, 2008, pp. 693e696. N. Damrongplasit, S.H. Kim, T.J.K. Liu, Study of random dopant fluctuation induced variability in the raised-Ge-source TFET, IEEE Electron Device Lett. 34 (2) (Feb. 2013) 184e186. R.J.E. Hueting, et al., Charge plasma P-N diode, IEEE Electron Device Lett. 29 (12) (Dec. 2008) 1367e1368. G.A. Salvatore, D. Bouvet, A.M. Ionescu, in: Demonstration of Subthrehold Swing Smaller than 60 mV/decade in Fe-FET with P(VDF-TrFE)/SiO2 Gate Stack, IEEE International Electron Devices Meeting, San Francisco, USA, Dec. 2008, pp. 15e17.
A. Lahgere et al. / Superlattices and Microstructures 96 (2016) 16e25
25
[12] M.H. Lee, et al., Ferroelectric Negative Capacitance Hetero-tunnel Field-effect-transistors with Internal Voltage Amplification, IEDM Tech. Dig., Washington, DC, USA, 2013, pp. 104e107. [13] A. Rusu, G.A. Salvatore, D. Jimenez, A.M. Ionescu, Metal-ferroelectric-metal-oxide-semiconductor Field Effect Transistor with Sub-60mV/decade Subthreshold Swing and Internal Voltage Amplification, IEDM Tech. Dig., San Francisco, CA, USA, 2010, pp. 395e398. [14] C.H. Cheng, A. Chin, Low-voltage steep turn-on p-MOSFET using ferroelectric high-k gate dielectric, IEEE Electron Device Lett. 35 (2) (Feb. 2014) 274e276. [15] M.H. Lee, et al., Ferroelectric gate tunnel field-effect transistors with low-power steep turn-On, AIP Adv. 4 (10) (2014) 107117. [16] M. Kumar, S. Jit, A novel four-terminal ferroelectric tunnel fet for quasi-ideal switch, IEEE Trans. Nanotechnol. 14 (4) (July 2015) 600e602. [17] C. Sahu, J. Singh, Charge-plasma based process variation immune junctionless transistor, IEEE Electron Device Lett. 35 (3) (March 2014) 411e413. [18] C. Sahu, J. Singh, Potential benefits and sensitivity analysis of dopingless transistor for low power applications, IEEE Trans. Electron Devices 62 (3) (March 2015) 729e735. [19] A. Lahgere, C. Sahu, J. Singh, PVT-aware design of dopingless dynamically configurable tunnel FET, IEEE Trans. Electron Devices 62 (8) (Aug. 2015) 2404e2409. [20] A. Lahgere, C. Sahu, J. Singh, Electrically doped dynamically configurable field-effect transistor for low-power and high-performance applications, IET Electron. Lett. 51 (16) (June 2015) 1284e1286. [21] W.H. Teh, A. Trigg, C.H. Tung, R. Kumar, N. Balasubramanian, D.L. Kwong, 200 mm wafer-scale epitaxial transfer of single crystal Si on glass by anodic bonding of silicon-on-insulator wafers, Appl. Phys. Lett. 87 (2005) article no. 073107. [22] Q. Zhang, W. Zhao, A. Seabaugh, Low-subthreshold-swing tunnel transistors, IEEE Electron. Device Lett. (2006) 27. [23] M.J. Kumar, S. Janardhanan, Doping-less tunnel field effect transistor: design and investigation, IEEE Trans. Electron. Devices 60 (10) (Oct. 2013) 3285e3290. [24] S. Ramaswamy, M.J. Kumar, Junctionless impact ionization MOS: proposal and investigation, IEEE Trans. Electron Devices 61 (12) (Dec. 2014) 4295e4298. [25] ATLAS Device Simulation Software, Silvaco Int., Santa Clara, CA, USA, 2015. [26] S.L. Miller, et al., Device modeling of ferroelectric capacitors, J. Appl. Phys. 68 (12) (Dec. 1990) 15. [27] S.L. Miller, P.J. McWhorter, Physic of the ferroelectric non-volitile memory field effect transistor, J. Appl. Phys. 72 (12) (Dec. 1992) 5999e6010, 15. [28] S.-J. Choi, D.-I. Moon, S. Kim, J.P. Duarte, Y.-K. Choi, Sensitivity of threshold voltage to nanowire width variation in junctionless transistors, IEEE Electron Device Lett. 32 (2) (Feb. 2011) 125e127. [29] L. Lattanzio, L. De Michielis, A. Biswas, A.M. Ionescu, Abrupt switch based on internally combined Band-To-Band and Barrier Tunneling mechanisms, in: European Solid State Device Research Conference, 2010, pp. 353e356.