- Email: [email protected]
Effects of radiation on microelectronics and techniques for hardening
Nuclear Instruments and Methods in Physics Research B40/41 North-Holland, Amsterdam
EFFECTS
OF RADIATION
1291
(1989) 1291-1294
ON MICROELECTRONICS
AND TECHNIQUES
FOR HARDENING
*
Paul V. DRESSENDORFER Sandia National Laboratories,
Albuquerque,
NM,
USA
Total dose damage, displacement damage, and single particle events can cause microelectronic circuits to cease to function properly. The tolerance of an integrated circuit to radiation damage can be affected by a large number of factors, including the irradiation conditions, postirradiation conditions, transistor characteristics, and circuit design. Improvements in hardness can be achieved by proper fabrication techniques (including minimization of gate oxide thickness, processing temperatures, and the use of hydrogen for MOS devices) and appropriate design considerations.
1. Intruduction Radiation can cause significant damage to the materials of which microelectronic circuits are composed. As a result, circuits exposed to radiation environments can experience detrimental changes in their operational characteristics. This paper will provide a brief overview of the mechanisms for radiation damage, the effects this damage has on microelectronic devices, and the techniques which may be utilized to maximize the amount of radiation which a circuit can tolerate before suffering unacceptable degradation in its properties. The radiation environments considered will be those most likely to be experienced by complex electronics associated with research or industrial accelerators. The discussions deal with silicon-based integrated circuits, with a focus on MOS structures.
2. Radiation effects There are four categories of radiation damage which in general can be of concern to the operation of microelectronics. They are total dose effects, displacement damage effects, single event effects, and dose rate (or transient) effects. High dose rates (> lo6 rad (Si)/s) can cause temporary upset of operation or of data stored in a circuit, or can trigger latchup (the condition where a parasitic semiconductor-controlled rectifier (SCR) is driven into its low impedance state) and subsequent catastrophic failure of the circuit. This environment is of concern primarily for strategic systems and will not be considered further here.
* This work performed at Sandia National Laboratories was supported by the US Department of Energy through contract DE-ACO4-76DPOO789
0168-583X/89/$03.50 0 Elsevier Science publishers B.V. (North-Holland Physics publishing Division)
2.1. Total dose effects In both MOS and bipolar circuits, the material of concern for damage from total ionizing dose is silicon dioxide. Under the influence of an electric field, the electron/hole pairs created by the radiation separate, with the electrons being rapidly swept out of the oxide and the holes undergoing a slow, stochastic trap-hopping process [ 11. Some portion of these holes are trapped near the silicon/silicon dioxide interface, and some undergo a reaction which results in the creation of electronic trap levels at this interface. This results in two components of charge in the oxide/silicon structure, that due to the trapped holes (oxide-trapped charge) and that due to the interface traps (interfacetrapped charge). These charges in turn result in shifts in the characteristics of both active and parasitic MOS devices. The hardness or tolerance of an integrated circuit to a dose of ionizing radiation can be affected by a number of factors. These include the irradiation conditions (energy of the radiation [2], dose rate [3], circuit bias [4], and temperature [1,5]), the postirradiation conditions [6] (bias, time and temperature), the transistor characteristics (geometry [7], type [4], and fabrication method [S]), and the circuit design [9] (logic type, logic implementation, and layout). Only a few of these factors will be illustrated below, but all of them must be considered when assessing the appropriateness of a circuit for a particular environment. Fig. 1 illustrates (for relatively radiation-tolerant transistors) the types of shifts which can be observed as a function of the static bias applied to the transistor during irradiation. Marked differences are seen between transistors biased ON or OFF during irradiation. “Turnaround” in the n-channel threshold voltage shift occurs as the charge in interface traps begins to dominate the oxide-trapped charge. Transistors in which the bias XI. DETECTORS/CALIBRATION
1292
THRESHOLD VOLTAGE (VOLTS)
P. V. Dressendorfer / Effecis of radiation on microelectronics
0 10’ -,
105
DOSE (RIDS)
106
p-cll
ON
-2 \
OFF
Fig. 1. Threshold voltage of n- and p-channel MOS transistors as a function of radiation dose for different static biases applied during irradiation.
100
100
10’0
10”
10’2
10’3
IO”
,a
l5
NEUTRON FLUENCE (“led)
is changed during the irradiation time show qualitatively similar behavior, but the resultant threshold need not fall between the ON and OFF bias cases [4]. The threshold voltage of MOS transistors is typically not stable with time after an irradiation. There is often a long term buildup of interface traps [5], and compensation via electron tunneling or annealing of the oxide trapped charge can also occur [lo]. Both of these processes are affected by the electric field and temperature [5,10]. As a result, the dose rate at which the radiation is received can also have a significant effect on the threshold voltage shift observed, as illustrated in fig. 2 [3]. At the lower dose rates it takes more time to accumulate the same total dose, and the threshold shift is more positive as the dose rate is lowered. These types of changes in MOS transistor characteristics with irradiation are reflected in the response of an integrated circuit. In an ionizing radiation environment, a circuit may show complete loss of functionality; large shifts can occur in power supply current, input currents, timing delays for various signal paths, input and output voltage levels, output drive capability, minimum and
THRESHOLOVOLTAGE SHIFT A VU,(V)
Fig. 3. Relative sensitivity of lifetime, carrier concentration, and carrier mobility to neutron bombardment. Effects for two values of preirradiation lifetime are shown. (After Srour et al., ref. [ll].)
maximum functional frequencies, minimum power supply voltage, and noise margins. However, with appropriate care in design and fabrication, advanced CMOS technologies have demonstrated total dose hardness levels in excess of 10’ rad (Si). 2.2. Displacement
damage
Energetic particles incident on silicon circuits can cause displacement of atoms from their lattice sites. The resultant defect centers decrease the generation and minority carrier recombination lifetimes, the majority carrier concentration (carrier removal), and the carrier mobility [ll]. These effects are illustrated in fig. 3 for neutron bombardment of 2 D cm silicon [ll]. Lifetime is much more sensitive to displacement damage than the other properties, so that the gain of bipolar transistors (which depends upon recombination lifetime) is affected more than that of MOS transistors. However, advanced bipolar technologies with narrow basewidths are much less susceptible to displacement damage than older technologies; hardness levels of 10’3-10’4 neutrons/cm2 can be routinely attained in digital circuits. One other important effect from displacement damage is the increase in leakage currents in the circuit. This can cause reduced sensitivity in charge coupled devices and reduced resolution in analog-to-digital converters. 2.3. Single event upset
IO’
105
106
OOSE (rmd (SW
Fig. 2. Threshold voltage shifts for n-channel transistors as a function of radiation dose for varying dose rates. (After Winokur et al., ref. [3].)
Single event upset can occur when a single highly energetic ion creates enough charge locally within an integrated circuit to alter information or generate erroneous signals [12]. Susceptibility to SEU becomes greater as the feature sizes of individual circuit elements are reduced (to achieve larger scale integration or higher
1293
P. V. Dressendorfer / Effects of radiation on microelectronics
speed), since the amount of charge stored at circuit nodes to represent information becomes less [13]. Although passage of a single ion may induce latchup and subsequent circuit failure [14], more typically the effect is to change the data stored in memory elements or create false signals.
A
Vit
2.0 I.6 1.6
-
1.4
-
;.f
-“‘=
r = vp =
100 krad
.49
4.0 3.5 3.0
Integrated circuits can be made more tolerant of radiation damage by altering the processes utilized in their fabrication, by appropriate design practices, and by system-level techniques. Some of the approaches applicable to hardening MOS circuits to total dose damage are described below.
-
r =
100 kr4d
lox
INCREASING
-5
-2
.l
SHIFT(V)
-0.2
-0.1
I”
GATE OXIDE
ll&tt4E&nm)
Fig. 4. Dependence of the flatband voltage shift of MOS devices on the oxide thickness for oxides grown under three condition and for two values of applied field during irradiation. (After Shiono et al., ref. [20].)
B
C
b HYDROGEN IN PROCESS
Fig. 5. Voltage shift due to radiation-induced traps (Vi,) and oxide-trapped charge (V,,) for MOS capacitors processed with different amounts of hydrogen ((A) with the least amount and (C) with the most.) (After Schwank et al., ref. [22].)
applied electric field that the radiation induced threshold voltage shift can be reduced markedly by making the gate oxide thinner. Depending on the particular process used to grow the gate oxide, a factor of 2 decrease in oxide thickness can cause a factor of 3 to 8 decrease in the threshold voltage shift for a given radiation dose. The temperature and time of annealing processes after the gate oxide is grown are critical to maintaining the hardness of the oxide [21]. Generally process temperatures should be kept below 900 o C to prevent degradation in the hardness characteristics. Hydrogen has been shown to be correlated with increased radiation sensitivity, as illustrated in fig. 5 [22]. As the amount of hydrogen used in various steps of the process was increased, the density of both oxidetrapped charge and interface trap charge increased. 3.2. Design
-0.5
2.92
= lolnm
A
Hundreds of individual process steps must be performed to create an integrated circuit from a silicon wafer, and a large number of these can have a significant impact upon the sensitivity of the MOS device structure to ionizing radiation. Some of the steps which have been demonstrated to be important include the cleaning of the wafer before gate oxidation [15], the gate oxidation process itself [8] (growth temperature, ambient, and anneals), the use of refractory electrode materials [16], the energy and species for source/drain implants [17], ambients and temperatures of activation/ densification cycles [18], metal deposition techniques [8], and the final passivation layer [19]. A key item in minimizing the changes in MOS device characteristics is the thickness of the gate oxide. Fig. 4 [20] shows for different growth ambients and values of
@IO,)
vg = 10 volts
3.1. Fabrication
VFS
1.15
“lnm
:6 .6 -
3. Hardening techniques
(5102)
10 volt4
considerations
A number of factors can be utilized during the design of a circuit to improve the radiation tolerance. Full CMOS logic is preferrable to NMOS, static circuitry is better than dynamic, and in general synchronous circuitry is easier to harden than asynchronous circuitry [9]. Layout can be used to minimize leakage paths such as might occur with parasitic field oxide devices [23]. Simulations can be used to optimize the design to handle parameter shifts in the transistors, balance offset currents, account for possible radiationinduced leakage, etc. XI. DETECTORS/CALIBRATION
I294 3.3. System
P. V. Dressendorfer / Effects of radiation on microelectronics hardening
Although generally not an attractive alternative, it is possible to harden against total dose effects to some degree at the system level. For example, shielding of critical parts may be provided, power supplies may be made more robust to provide for increased current, and interface protocols may be relaxed to allow for degradation in chip input and output voltage levels.
4. sllnlmary Total dose damage in integrated circuits results primarily from the buildup of oxide-trapped and interface trap charge in the oxide layers. High energy particles can create displacement damage or cause single event upset. These forms of radiation damage can cause major changes in the characteristics of microelectronic devices. The overall radiation hardness of integrated circuits depends on the details of the radiation and use environments. To improve the radiation hardness of circuits requires the consideration of both the fabrication techniques and the design methodology. Important factors to consider for hardening MOS devices to total dose damage include the gate oxide thickness, processing temperatures after gate oxide growth, and the use of hydrogen in the processing ambients.
References [l] F.B. McLean, H.E. Boesch, Jr., and J.M. McGarrity, The Physics of SiO, and its Interfaces, ed. S.T. Panteleides, (Pergamon Press, Elmsford, NY, 1978) p. 19. [2] C.M. Dozier and D.B. Brown, IEEE Trans. Nucl. Sci. NS-27 (1980) 1694. [3] P.S. Winokur, F.W. Sexton, J.R. Schwank, D.M. Fleetwood, P.V. Dressendorfer, T.F. Wrobel, and D.C. Turpin, IEEE Trans. Nucl. Sci. NS-33 (1986) 1343. [4] P.V. Dressendorfer, J.M. Soden, J.J. Harrington, and T.V. Nordstrom, IEEE Trans. Nucl. Sci. NS-28 (1981) 4281.
[S] P.S. Winokur, H.E. Boesch, Jr., J.M. McGarrity, and F.B. McLean, IEEE Trans. Nucl. Sci. NS-24 (1977) 2113. [6] D.M. Fleetwood, P.V. Dressendorfer, and D.C. Turpin, IEEE Trans. Nucl. Sci. NS-34 (1987) 1178. [7] J.W. S&rankler, R.K. Reich, M.S. Holt, D.H. Ju, J.S.T. Huang, G.D. Kirchner, and H.L. Hughes, IEEE Trans. Nucl. Sci. NS-32 (1985) 3988. (81 G.F. Derbenwick and B.L. Gregory, IEEE Trans. Nucl. Sci. NS-22 (1975) 2151. [9] W.S. Kim, T.M. Mnich, W.T. Corbett, R.K. Treece, A.E. Giddings, and J.L. Jorgensen, IEEE Trans. Nucl. Sci. NS-30 (1983) 4229. [lo] J.R. Schwa& P.S. Winokur, P.J. McWhorter, F.W. Sexton, P.V. Dressendorfer, and D.C. Turpin, IEEE Trans. Nucl. Sci. NS-31 (1984) 1434. [ll] J.R. Srour, D.M. Long, D.G. Millward, R.L. Fitzwilson, and W.L. Chadsey, Radiation Effects on and Dose Enhancement of Electronic Materials (Noyes Publication, Park Ridge, NJ, 1984). [12] T.C. May and M.H. Woods, IEEE Trans. Electron. Dev. ED-26 (1979) 2. [13] E.L. Petersen, P. Shapiro, J.H. Adams, Jr., and E.A. Burke, IEEE Trans. Nucl. Sci. NS-29 (1982) 2055. [14] K. Soliman and D.K. Nichols, IEEE Trans. Nucl. Sci. NS-30 (1983) 4514. [15] E.F. daSilva, T.P. Ma, and Y. Nishioka, IEEE Trans. Nucl. Sci. NS-34 (1987) 1190. [16] K. Kasama, F. Toyokawa, M. Tsukiji, M. Sakamoto, and K. Kobayashi, IEEE Trans. Nucl. Sci. NS-33 (1986) 1210. [17] R.K. Smeltzer, IEEE Trans. Nucl. Sci. NS-27 (1980) 1745. [18] P.S. Winokur, E.B. Errett, D.M. Fleetwood, P.V. Dressendorfer, and D.C. Turpin, IEEE Trans. Nucl. Sci. NS-32 (1985) 3954. 1191 R.E. Anderson, IEEE Trans. Nucl. Sci. NS-26 (1979) 5180. [20] N. Shiono, M. Shimaya, and K. Sano, Jpn. J. Appl. Phys. 22 (1983) 1430. [21] H. Borkan, IEEE Trans. Nucl. Sci. NS-24 (1977) 2043. [22] J.R. Schwank, D.M. Fleetwood, P.S. Winokur, P.V. Dressendorfer, D.C. Turpin, and D.T. Sanders, IEEE Trans. Nucl. Sci. NS-34 (1987) 1152. [23] J.R. Adams and F.N. Coppage, IEEE Trans. Nucl. Sci. NS-23 (1976) 1604.
EFFECTS
OF RADIATION
1291
(1989) 1291-1294
ON MICROELECTRONICS
AND TECHNIQUES
FOR HARDENING
*
Paul V. DRESSENDORFER Sandia National Laboratories,
Albuquerque,
NM,
USA
Total dose damage, displacement damage, and single particle events can cause microelectronic circuits to cease to function properly. The tolerance of an integrated circuit to radiation damage can be affected by a large number of factors, including the irradiation conditions, postirradiation conditions, transistor characteristics, and circuit design. Improvements in hardness can be achieved by proper fabrication techniques (including minimization of gate oxide thickness, processing temperatures, and the use of hydrogen for MOS devices) and appropriate design considerations.
1. Intruduction Radiation can cause significant damage to the materials of which microelectronic circuits are composed. As a result, circuits exposed to radiation environments can experience detrimental changes in their operational characteristics. This paper will provide a brief overview of the mechanisms for radiation damage, the effects this damage has on microelectronic devices, and the techniques which may be utilized to maximize the amount of radiation which a circuit can tolerate before suffering unacceptable degradation in its properties. The radiation environments considered will be those most likely to be experienced by complex electronics associated with research or industrial accelerators. The discussions deal with silicon-based integrated circuits, with a focus on MOS structures.
2. Radiation effects There are four categories of radiation damage which in general can be of concern to the operation of microelectronics. They are total dose effects, displacement damage effects, single event effects, and dose rate (or transient) effects. High dose rates (> lo6 rad (Si)/s) can cause temporary upset of operation or of data stored in a circuit, or can trigger latchup (the condition where a parasitic semiconductor-controlled rectifier (SCR) is driven into its low impedance state) and subsequent catastrophic failure of the circuit. This environment is of concern primarily for strategic systems and will not be considered further here.
* This work performed at Sandia National Laboratories was supported by the US Department of Energy through contract DE-ACO4-76DPOO789
0168-583X/89/$03.50 0 Elsevier Science publishers B.V. (North-Holland Physics publishing Division)
2.1. Total dose effects In both MOS and bipolar circuits, the material of concern for damage from total ionizing dose is silicon dioxide. Under the influence of an electric field, the electron/hole pairs created by the radiation separate, with the electrons being rapidly swept out of the oxide and the holes undergoing a slow, stochastic trap-hopping process [ 11. Some portion of these holes are trapped near the silicon/silicon dioxide interface, and some undergo a reaction which results in the creation of electronic trap levels at this interface. This results in two components of charge in the oxide/silicon structure, that due to the trapped holes (oxide-trapped charge) and that due to the interface traps (interfacetrapped charge). These charges in turn result in shifts in the characteristics of both active and parasitic MOS devices. The hardness or tolerance of an integrated circuit to a dose of ionizing radiation can be affected by a number of factors. These include the irradiation conditions (energy of the radiation [2], dose rate [3], circuit bias [4], and temperature [1,5]), the postirradiation conditions [6] (bias, time and temperature), the transistor characteristics (geometry [7], type [4], and fabrication method [S]), and the circuit design [9] (logic type, logic implementation, and layout). Only a few of these factors will be illustrated below, but all of them must be considered when assessing the appropriateness of a circuit for a particular environment. Fig. 1 illustrates (for relatively radiation-tolerant transistors) the types of shifts which can be observed as a function of the static bias applied to the transistor during irradiation. Marked differences are seen between transistors biased ON or OFF during irradiation. “Turnaround” in the n-channel threshold voltage shift occurs as the charge in interface traps begins to dominate the oxide-trapped charge. Transistors in which the bias XI. DETECTORS/CALIBRATION
1292
THRESHOLD VOLTAGE (VOLTS)
P. V. Dressendorfer / Effecis of radiation on microelectronics
0 10’ -,
105
DOSE (RIDS)
106
p-cll
ON
-2 \
OFF
Fig. 1. Threshold voltage of n- and p-channel MOS transistors as a function of radiation dose for different static biases applied during irradiation.
100
100
10’0
10”
10’2
10’3
IO”
,a
l5
NEUTRON FLUENCE (“led)
is changed during the irradiation time show qualitatively similar behavior, but the resultant threshold need not fall between the ON and OFF bias cases [4]. The threshold voltage of MOS transistors is typically not stable with time after an irradiation. There is often a long term buildup of interface traps [5], and compensation via electron tunneling or annealing of the oxide trapped charge can also occur [lo]. Both of these processes are affected by the electric field and temperature [5,10]. As a result, the dose rate at which the radiation is received can also have a significant effect on the threshold voltage shift observed, as illustrated in fig. 2 [3]. At the lower dose rates it takes more time to accumulate the same total dose, and the threshold shift is more positive as the dose rate is lowered. These types of changes in MOS transistor characteristics with irradiation are reflected in the response of an integrated circuit. In an ionizing radiation environment, a circuit may show complete loss of functionality; large shifts can occur in power supply current, input currents, timing delays for various signal paths, input and output voltage levels, output drive capability, minimum and
THRESHOLOVOLTAGE SHIFT A VU,(V)
Fig. 3. Relative sensitivity of lifetime, carrier concentration, and carrier mobility to neutron bombardment. Effects for two values of preirradiation lifetime are shown. (After Srour et al., ref. [ll].)
maximum functional frequencies, minimum power supply voltage, and noise margins. However, with appropriate care in design and fabrication, advanced CMOS technologies have demonstrated total dose hardness levels in excess of 10’ rad (Si). 2.2. Displacement
damage
Energetic particles incident on silicon circuits can cause displacement of atoms from their lattice sites. The resultant defect centers decrease the generation and minority carrier recombination lifetimes, the majority carrier concentration (carrier removal), and the carrier mobility [ll]. These effects are illustrated in fig. 3 for neutron bombardment of 2 D cm silicon [ll]. Lifetime is much more sensitive to displacement damage than the other properties, so that the gain of bipolar transistors (which depends upon recombination lifetime) is affected more than that of MOS transistors. However, advanced bipolar technologies with narrow basewidths are much less susceptible to displacement damage than older technologies; hardness levels of 10’3-10’4 neutrons/cm2 can be routinely attained in digital circuits. One other important effect from displacement damage is the increase in leakage currents in the circuit. This can cause reduced sensitivity in charge coupled devices and reduced resolution in analog-to-digital converters. 2.3. Single event upset
IO’
105
106
OOSE (rmd (SW
Fig. 2. Threshold voltage shifts for n-channel transistors as a function of radiation dose for varying dose rates. (After Winokur et al., ref. [3].)
Single event upset can occur when a single highly energetic ion creates enough charge locally within an integrated circuit to alter information or generate erroneous signals [12]. Susceptibility to SEU becomes greater as the feature sizes of individual circuit elements are reduced (to achieve larger scale integration or higher
1293
P. V. Dressendorfer / Effects of radiation on microelectronics
speed), since the amount of charge stored at circuit nodes to represent information becomes less [13]. Although passage of a single ion may induce latchup and subsequent circuit failure [14], more typically the effect is to change the data stored in memory elements or create false signals.
A
Vit
2.0 I.6 1.6
-
1.4
-
;.f
-“‘=
r = vp =
100 krad
.49
4.0 3.5 3.0
Integrated circuits can be made more tolerant of radiation damage by altering the processes utilized in their fabrication, by appropriate design practices, and by system-level techniques. Some of the approaches applicable to hardening MOS circuits to total dose damage are described below.
-
r =
100 kr4d
lox
INCREASING
-5
-2
.l
SHIFT(V)
-0.2
-0.1
I”
GATE OXIDE
ll&tt4E&nm)
Fig. 4. Dependence of the flatband voltage shift of MOS devices on the oxide thickness for oxides grown under three condition and for two values of applied field during irradiation. (After Shiono et al., ref. [20].)
B
C
b HYDROGEN IN PROCESS
Fig. 5. Voltage shift due to radiation-induced traps (Vi,) and oxide-trapped charge (V,,) for MOS capacitors processed with different amounts of hydrogen ((A) with the least amount and (C) with the most.) (After Schwank et al., ref. [22].)
applied electric field that the radiation induced threshold voltage shift can be reduced markedly by making the gate oxide thinner. Depending on the particular process used to grow the gate oxide, a factor of 2 decrease in oxide thickness can cause a factor of 3 to 8 decrease in the threshold voltage shift for a given radiation dose. The temperature and time of annealing processes after the gate oxide is grown are critical to maintaining the hardness of the oxide [21]. Generally process temperatures should be kept below 900 o C to prevent degradation in the hardness characteristics. Hydrogen has been shown to be correlated with increased radiation sensitivity, as illustrated in fig. 5 [22]. As the amount of hydrogen used in various steps of the process was increased, the density of both oxidetrapped charge and interface trap charge increased. 3.2. Design
-0.5
2.92
= lolnm
A
Hundreds of individual process steps must be performed to create an integrated circuit from a silicon wafer, and a large number of these can have a significant impact upon the sensitivity of the MOS device structure to ionizing radiation. Some of the steps which have been demonstrated to be important include the cleaning of the wafer before gate oxidation [15], the gate oxidation process itself [8] (growth temperature, ambient, and anneals), the use of refractory electrode materials [16], the energy and species for source/drain implants [17], ambients and temperatures of activation/ densification cycles [18], metal deposition techniques [8], and the final passivation layer [19]. A key item in minimizing the changes in MOS device characteristics is the thickness of the gate oxide. Fig. 4 [20] shows for different growth ambients and values of
@IO,)
vg = 10 volts
3.1. Fabrication
VFS
1.15
“lnm
:6 .6 -
3. Hardening techniques
(5102)
10 volt4
considerations
A number of factors can be utilized during the design of a circuit to improve the radiation tolerance. Full CMOS logic is preferrable to NMOS, static circuitry is better than dynamic, and in general synchronous circuitry is easier to harden than asynchronous circuitry [9]. Layout can be used to minimize leakage paths such as might occur with parasitic field oxide devices [23]. Simulations can be used to optimize the design to handle parameter shifts in the transistors, balance offset currents, account for possible radiationinduced leakage, etc. XI. DETECTORS/CALIBRATION
I294 3.3. System
P. V. Dressendorfer / Effects of radiation on microelectronics hardening
Although generally not an attractive alternative, it is possible to harden against total dose effects to some degree at the system level. For example, shielding of critical parts may be provided, power supplies may be made more robust to provide for increased current, and interface protocols may be relaxed to allow for degradation in chip input and output voltage levels.
4. sllnlmary Total dose damage in integrated circuits results primarily from the buildup of oxide-trapped and interface trap charge in the oxide layers. High energy particles can create displacement damage or cause single event upset. These forms of radiation damage can cause major changes in the characteristics of microelectronic devices. The overall radiation hardness of integrated circuits depends on the details of the radiation and use environments. To improve the radiation hardness of circuits requires the consideration of both the fabrication techniques and the design methodology. Important factors to consider for hardening MOS devices to total dose damage include the gate oxide thickness, processing temperatures after gate oxide growth, and the use of hydrogen in the processing ambients.
References [l] F.B. McLean, H.E. Boesch, Jr., and J.M. McGarrity, The Physics of SiO, and its Interfaces, ed. S.T. Panteleides, (Pergamon Press, Elmsford, NY, 1978) p. 19. [2] C.M. Dozier and D.B. Brown, IEEE Trans. Nucl. Sci. NS-27 (1980) 1694. [3] P.S. Winokur, F.W. Sexton, J.R. Schwank, D.M. Fleetwood, P.V. Dressendorfer, T.F. Wrobel, and D.C. Turpin, IEEE Trans. Nucl. Sci. NS-33 (1986) 1343. [4] P.V. Dressendorfer, J.M. Soden, J.J. Harrington, and T.V. Nordstrom, IEEE Trans. Nucl. Sci. NS-28 (1981) 4281.
[S] P.S. Winokur, H.E. Boesch, Jr., J.M. McGarrity, and F.B. McLean, IEEE Trans. Nucl. Sci. NS-24 (1977) 2113. [6] D.M. Fleetwood, P.V. Dressendorfer, and D.C. Turpin, IEEE Trans. Nucl. Sci. NS-34 (1987) 1178. [7] J.W. S&rankler, R.K. Reich, M.S. Holt, D.H. Ju, J.S.T. Huang, G.D. Kirchner, and H.L. Hughes, IEEE Trans. Nucl. Sci. NS-32 (1985) 3988. (81 G.F. Derbenwick and B.L. Gregory, IEEE Trans. Nucl. Sci. NS-22 (1975) 2151. [9] W.S. Kim, T.M. Mnich, W.T. Corbett, R.K. Treece, A.E. Giddings, and J.L. Jorgensen, IEEE Trans. Nucl. Sci. NS-30 (1983) 4229. [lo] J.R. Schwa& P.S. Winokur, P.J. McWhorter, F.W. Sexton, P.V. Dressendorfer, and D.C. Turpin, IEEE Trans. Nucl. Sci. NS-31 (1984) 1434. [ll] J.R. Srour, D.M. Long, D.G. Millward, R.L. Fitzwilson, and W.L. Chadsey, Radiation Effects on and Dose Enhancement of Electronic Materials (Noyes Publication, Park Ridge, NJ, 1984). [12] T.C. May and M.H. Woods, IEEE Trans. Electron. Dev. ED-26 (1979) 2. [13] E.L. Petersen, P. Shapiro, J.H. Adams, Jr., and E.A. Burke, IEEE Trans. Nucl. Sci. NS-29 (1982) 2055. [14] K. Soliman and D.K. Nichols, IEEE Trans. Nucl. Sci. NS-30 (1983) 4514. [15] E.F. daSilva, T.P. Ma, and Y. Nishioka, IEEE Trans. Nucl. Sci. NS-34 (1987) 1190. [16] K. Kasama, F. Toyokawa, M. Tsukiji, M. Sakamoto, and K. Kobayashi, IEEE Trans. Nucl. Sci. NS-33 (1986) 1210. [17] R.K. Smeltzer, IEEE Trans. Nucl. Sci. NS-27 (1980) 1745. [18] P.S. Winokur, E.B. Errett, D.M. Fleetwood, P.V. Dressendorfer, and D.C. Turpin, IEEE Trans. Nucl. Sci. NS-32 (1985) 3954. 1191 R.E. Anderson, IEEE Trans. Nucl. Sci. NS-26 (1979) 5180. [20] N. Shiono, M. Shimaya, and K. Sano, Jpn. J. Appl. Phys. 22 (1983) 1430. [21] H. Borkan, IEEE Trans. Nucl. Sci. NS-24 (1977) 2043. [22] J.R. Schwank, D.M. Fleetwood, P.S. Winokur, P.V. Dressendorfer, D.C. Turpin, and D.T. Sanders, IEEE Trans. Nucl. Sci. NS-34 (1987) 1152. [23] J.R. Adams and F.N. Coppage, IEEE Trans. Nucl. Sci. NS-23 (1976) 1604.