Electron-beam testing for chip verification of 16-Mbit DRAMs

Microelectronic Elsevier

Engineering

16 (1992) 213-222 213

Electron-Beam Testing for Chip Verification of 16-Mbit DRAMS F. Foxa, S. G6rlicha, M. Menkeb Siemens AG, “Corporate Research and Development and bSemiconductor Division, Otto-Hahn-Ring 6, D-8000 Miinchen 83, Germany

Abstract Comparison of design and technology data of the 16-Mbit DRAM with that of circuits from the previous generation shows that the former have not become more critical for electron-beam testing. The performance of the submicron electron-beam tester developed for the 4-Mbit generation is also sufficient for the present generation. The main difficulty for the latter is caused by the use of two metallization layers. There is no longer any direct access to most internal signals, even for designverification. To obtain the same observability as in modules with one metallization layer, Alu 2 test pads were consistently used. The advantages of this layout for testability are compared with those of other approaches. Examples and results of such test pads are presented. After manufacture, measuring sites can be made accessible by local preparation using a focused ion beam (FIB). However, this method is expensive and time-consuming. Various examples of this approach and the quality of the results obtained by it are discussed. When using the layout for testability and local preparation, design verification is also possible in two-layer metallization without restrictions.

1. INTRODUCTION Chip verification of DRAMS always makes the heaviest demands on the performance of electron-beam testers. These demands are directed not at the CAD or CAT link to support the debugging procedure, as is the case for chip verification of large logic devices, but mainly at the quality of the electron-optical column and of the spectrometer. This is because DRAMS are produced in the most advanced technology using the finest geometrical structures, and because designers and engineers require not only exact timing results on the scale of logic levels, but also precise quantitative waveforms, so that analogous measurements are required. 0167-9317/92/$05.00

0 1992 - Elsevier Science Publishers

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F. Fox et al. 1 Chip verification

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Table 1: Technology

of lh-Mbit DRAMS

and design data of 4-Mbit DRAM and 16-Mbit DRAM

4-Mbit DRAM

l&Mbit DRAM

Technology

0.9 ,um CMOS

0.6,um CMOS

Cell size

2.3 pm x 3.6 ,um

Chip size

6.5 mm x 14.05 mm

Access time

80 ns

t

Number of metal layers

pitch of bit line

1.3pm 2.6 pm AlLl2

of bus line

l.Opm 2.0pm Alul

150 mV I

2.

DEMANDS ON ELECTRON-BEAM TESTIN G

In Table 1, data of the 4-Mbit and 16-Mbit DRAMS [ l] of interest testing are listed. Important points are: .

the 16-Mbit DRAM

.

two metal layers are used,

.

critical signal swings are about the same,

.

despite shrinking design rules, the upper metallization

for electron-beam

is faster,

Therefore the main requirements on the parameters not really increased for the 16-Mbit DRAM [2].

becomes

wider.

for the electron-beam

tester have

F. Fox et al. I Chip vertfication of I&Mbit DRAMS

215

Hence the setup used for chip verification of 4-Mbit DRAMS is also used here [3]. It consists of an ICI 9010 electron-beam tester, an HP 8180A word generator, a CAD link to a workstation to support positioning from layout data and to compare measured and simulated waveforms. Some minor improvements were made: higher time resolution by using a 50-ps primary pulse, noise reduction by applying filtering techniques, easier handling with the aid of vector scan mode for semi-automated positioning. The important new feature for compensating the address error is described in another paper [4]. As a method for internal measurements, electron-beam testing is one of several tools for chip verification. This includes external tools such as functional testing, parameter measurements etc., but also internal tools such as mechanical microprobing. The use of laser or ion beams for chip manipulation to support special internal investigations should also be mentioned. The environment used has been described in detail in [3,5]. 3. LAYOUT FOR ELECTRON-BEAM

TESTABILITY

In comparing chip verification of 4-Mbit DRAMS to that of 16-Mbit DRAMS, one of the main problems is due to the two metal layers. As the wiring is mainly done in Alu 1, there is no direct access to these signals. Even in the case of nonpassivated devices, the Alu 1 lines are covered with oxide, or what is more problematic, with wide Alu 2 wires, especially VDD and Vss. In the case of oxide-covered lines, the application of capacitive coupling voltage contrast is in principle possible. The fine geometry of Alu 1 leads to errors like capacitive coupling error and capacitive coupling crosstalk, causing a reduction in signal swing of about 25% and signal crosstalk of about 20% respectively [6]. This means that only timing information is feasible, but not real quantitative measurements. However, the latter is necessary for chip verification. There are several ways to achieve free access to the nodes, for example: .

increased use of Alu 2 for wiring,

. etching off nearly the whole oxide layer between Alu 1 and Alu 2 during production, . etching local windows into the oxide during production l

formation of local windows with ion beams or laser-stimulated etching after production,

. use of Alu 2 test pads connected to Alu 1 lines. Normally we take the last approach (which is not new [7]) because of the following drawbacks of the other options: .

restrictions due to design rules,

.

etching of oxide layers or windows needs a new or refined mask and makes the process critical, because there is no etch stop,

.

the use of ion or laser beams is time-consuming and expensive and therefore useful only for specific cases.

The test pads are in general 4 pm x 4,~rn Alu 2 connected to Alul via a contact at the corner of the square. There is no shielding around the test pads [3,7]. A label is positioned

216

F. Fox et ul. I Chip verification

of /h-Mbit

DRAMS

at the center of the pad by using a special layer in the layout data. Advantages

are:

no change in production, very easy handling for the designer, label supports

finding of test pads,

size allows automated

positioning

of probe from layout data,

size enables quantitative measurement in case of not properly tuned EBT), mechanical

without errors due to local field effects (ever

probing can also be applied.

4. EXAMPLES OF INTERNAL ANALYSIS 4.1 Measurements

at test pads

An example of the application is given in Fig. 1, showing both the layout screen on the workstation and the voltage contrast image on the electron-beam tester. In the plot of the layout, the bus structure in Alu 1 can be clearly seen, but it disappears in the dark of the voltage contrast image. The list on the left of the layout screen names the test pads that are immediately visible in the layout. Fig. lb demonstrates that the test pads are lined up diagonally. This is vety helpful for logic state mappings with the electron-beam scanned in line mode across several test pads, giving a quick overview of the signal timing. Precise measurements can easily be made by automatic positioning in vector scan mode. Both of these are shown in Fig. 2 a and b, respectively

a

b

t

1

10pm

beam testability in 16-Mbit DRAM: Alu 2 test pads of Fig. 1: Example for electron 4 pm x 4 pm connected to Alul-bus: layout at workstation (a), voltage contrast image at electron beam tester (b)

F. Fox et al. I Chip verification

-

of 16-Mbit DRAMS

217

Delay range 400 ns Sl

s2 s3 s4 S5

a

Signals Sl

t U

s2

s3

s4

s5 b 25 ns/DIV Fig. 2:

t+

Logic state mapping (a) at test pads of internal bus of 16-Mbit DRAM (compare Fig.1) and waveform measurement in vector scan mode (b)

Measuring the sense signals in the cell area of DRAMS is normally a difficult task, as they are rather small (=150 mV) and the lines are the narrowest in the IC. But this task becomes very easy with the aid of design for electron-beam testability, as demonstrated in Fig. 3. The layout plot again shows labeled test pads connected to bit lines. The waveforms in Fig. 3b of the BL and m signals measured at the pads B1002 and BN1002 are compared to the RAS signal for determining internal delay times. The sense signal, the difference between BL and m, was easily detected. These results were obtained in a straightforward way without any problems.

218

F. Fox et al. I Chip verification

t

oj’I6Mhit

DRAMS

I

r U,,

U

‘PE 7

1 n 3 ‘I.

RAS

b

= 1kV 1;

;;

= 100 ns tM n = 500 points ave. = 6

10 ns/DIV

t

Fig. 3: Measurement

of sense signal: layout showing test pads connected to bit line (a) signals BL and= measured at test pads B1002 and BN1002 in comparison to signal RAS.

Many measurements were taken at different test sites to obtain several signals for analyzing the internal delays and comparing them with simulations (SPICE). This is done to understand special design weaknesses and find ways of eliminating them. 4.2 Measurements

after local preparation

Even for design verification, a test pad is naturally not always prepared at all critical nodes. Measurements are therefore also performed at normal conduction lines (perhaps even through oxides) or after local preparation (similar results are published in [8]). The layout of a chip area is plotted in Fig. 4, where the measurements were taken. Test pads in Alu 2 linked to a wide bus wired in Alu 1 are connected as described above. At these unpassivated chips, the Alu 1 is covered with 0.6,~m of SiOa. Near the test pads, four types of local preparations were performed using the focused ion beam (FIB) [9,10]. .

small windows about 2.0pm square to open the oxide for just one conduction

.

small windows about 1.4 pm square filled with tungsten deposition using W(CO)6 gas [lo],

.

wide windows, about 2.5 ,um x 4 ,um or up to 10 pm wide, open the oxide for several parallel conduction lines,

l

deposition

after ion-beam

of a thin layer of W (few nm) over the whole oxide-covered

line,

stimulated

bus.

F. Fox et al. I Chip ver#cation

219

of I&Mbit DRAMS

Fig. 4:

Layout of Alu 1 bus, showing Alu 2 test pads and test sites after local preparation by a focused ion beam The experience gained in using an FIB for local preparation is very promising. It gave good secondary electron images familiar to the user of electron-beam testers. Selection of the area of interest is then easy, and the window to be etched can be chosen in an interactive manner. The etching procedure is merely monitored by the secondary electron signal, which exhibits an abrupt and dramatic increase when the interface between oxide and conduction line appears. The homogeneity of the etched area can also be controlled in this way. Of course, the etching time depends on the ion-beam current, the material to be etched and its thickness as well as the size of the window to be opened. In our case, etching took between several seconds and a few minutes. Hence local preparation of windows through the oxide was easy and straightforward. This is also true for the deposition of tungsten, which we used only to fill a hole that had just been etched. However, this always leads to the deposition of a thin-film sphere around the intended deposition area, which should be strongly defined by the scan area of the ion radiation. This sphere could be etched away by using an inverted digital scan area. However, it turned out that this thin tungsten film has attractive properties such as topical antistats [ll], easily enabling voltage contrast images and logic state mappings at the oxide-covered Alu 1 conduction lines without any need for properly adjusting the primary electron energy or the extraction field. Furthermore, in the case of passivated circuits, local preparation has the advantage, compared to global etching of the whole passivation layer, that the capacitive load is unchanged and internal timing is therefore preserved. However, we did not succeed in using the FIB for preparing native production chips with all passivation layers (“sandwich” of oxide and nitride, plus polyimide). The positive charging was so strong that no proper secondary electron image was available for localization. The polyimide at least must previously be etched away homogeneously by other means.

220

F. Fox et al. ! Chip verijication

50 ns/DIV

a

of l&Mbit

t-

DRAMs

b

5 ns/DIV

Fig. 5: Waveforms

measured at a test pad (1,3) and a conduction line (2,4) covered with oxide and a thin layer of W, averaged only 8 times (1,2) and additionally filtered [median = 5, average = 21 (3,4), a) overview, b) zoomed rising edges

Fig. 5 shows four curves. Curves 1 and 3 measured at the test pads exhibited the right voltage swing of 5 V, whereas curves 2 and 4 measured at the bus of W-coated conduction lines show a reduced swing. Furthermore, the comparison between curves 1 and 2, which are conventionally averaged, and curves 3 and 4, which are averaged only twice but median filtered in situ, shows the improved signal-to-noise ratio. No important details of the curves were lost either, but the measuring time was reduced by a factor of four in this case. The zoomed detail in part b of this figure proves that rise and delay times are unchanged by this data improvement. Measurements of the same internal address signal at four different sites are compared in Fig. 6: at the Alu 2 test pad (a), a wide etched window (b), a small etched window (c), and a test point covered with Wand SiO2 (d) (cf. Figure 4). Parameters of the measurement were: primary electron-beam of 1 keV and 2 nA, pulse width 1 ns, delay range 1 ,LLS,1000 points, 2 averages, median filter of 5. It is obvious that all four measurements are about the same. Only small differences are observed, showing that local preparation gives a reasonable result in all cases. The curves a and b are really identical within the low-noise margin, whereas differences exist to curves c and d. In the case of the small window (c), the measured signal swing is still correct (5V), but a small amount of crosstalk caused by a neighboring signal can be seen. In the case of the W-covered SiO2 (d), the swing is reduced (= 4.3 V) and crosstalk is about 0.7 V.

F. Fox et al. I Chip verification

100 ns/DIV

of 16Mbit

DRAMS

t+

221

Fig. 6: Same signal measured at four test sites: a) Alu 2 test pads, b) wide etched window, c) small etched hole , covered 4 Alu 1 bus after W deposition

Results at small test points filled with W after etching a small window also show good results if they are carefully prepared. If this was not the case, a type of capacitive coupling was found with characteristic rise and fall times, probably due to the remaining SiO2 layer not being fully etched away. However, no advantage was found for the W-filled test sites, so that the additional preparation effort was not justified. Opening of local windows thus seems an adequate alternative where no test site is available in Alu 2.

5. CONCLUSION As for electron-beam testing, the main changes between the 4-Mbit DRAM and the 16-Mbit DRAM are due to the use of two metal layers that reduce observability drastically. Two approaches were pursued to overcome this problem: in the design phase, test pads in Alu 2 are connected to Alu 1 lines; after production, windows are etched through the oxide layer by local preparation using a focused ion beam. Both approaches enable exact quantitative measurements, which are necessary for design verification of DRAMS.

6. ACKNOWLEDGEMENT We would like to thank M. Peisl, E. Plies and E. Wolfgang for their general support. Special thanks are due to H. Mulatz and Mrs. H. Uthoff for device mounting and local preparation of the focused ion beam respectively. We owe our thanks to R. Michell for improving the English translation and Mrs B. Gorlich for typing the manuscript.

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DRAMS

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[2]

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[3]

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[4]

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[7]

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[8]

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[9]

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[lo]

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circuit modification

[ 111 H. Hosoi, H. Yuasa, M. Kudoh, K. Nikawa, S. Inoue:

Electron beam testing for LSI failure analysis IPFA Symp. Proc. (1987) 7-13