EPROM testing — Part II: Application to 16K N-channel devices

Microeleetron. Reliab., Vol. 22, No. 5, pp. 987-996, 1982. Printed in Great Britain.

EPR

OM

TESTING

0026-2714/82/050987-10503.00/0 © 1982 Pergamon Press Ltd.

- PART

S. A L L I N E Y ,

It: A P P L I C A T I O N

D. B E R T O T T I ,

T O 16K N - C H A N N E L

F. F A N T I N I

DEVICES

and C. M O R A N D I

Universita di Bologna - Istituto di Idraulica, V. le Risorgimento, Z, 40136 B O L O G N A , Italy. ~elettra

S. p.A. -Quality and Reliability Division, 20059 V I M E R C A T E (MI), Italy.

Telettra S. p.A. - Quality and IReliability Division, 40017 S. G i o v a n n i i n Persiceto (BO) Italy. Universita di Bologna - Istituto di Elettronica, V. le Risorgimento, Z, 40136 B O L O G N A , Italy. (R eceived for publication 18th D e c e m b e r

1981)

ABSTRACT

This paper

paper

[i]

shows

may

how

the

fault

models

introduced

in the parent

be applied to a commercial device.

After discussion of typical EPROhl architecture a n d circuitry, it is shown that

most

of

additional circuitry

the

faults

tests are which

are

detected

sug.Rested

are

not

by

to detect

described

by

the those

the

proposed faults

test sequence;

in the peripheral

"symmetric

decoder

fault"

model. Although results

developed of

this

with work

architecture is c o m m o n

reference to a specific architecture, most of the have

~eneral

validity,

since

the

analysed

to the ~reat majority of available devices.

1 - INTRODUCTION

In the field of automatic testing of memories it is commonly a

sensible

electric very

gap

is

present

between

functional

faults or the oate level faults actually

difficult

sequetlce,

to

link

any

result

on

the

fault

models

observed,

fault

felt that and

the

so that it is

coverage

of

a

test

optimized with reference to a functional model, with the actual

coverage of f a i l u r e s at the gate level. This paper shows that this l i n k can be easily established in the case of EPROI~Is with introduced

in

Part

reference to the Symmetric Decoder Faults (SDF)

I [i] . Of

course, 987

it is necessary

to refer

to a

988

S. ALLINEY et al.

relatively

well defined

n-channel

MOS d e v i c e w i l l b e c o n s i d e r e d

St i s s h o w n t h a t circuits

faults

t h e w i d e l y u s e d 2Kx8 f l o a t i n g

occurring

in

in those

looic

are

Part

I apply.

blocks

then

because

part

of the peripheral

to SDFs, s o t h a t

the considerations

The effects of single

where

a fault

discussed,

and

gate,

of its popularity.

in a large

of the memory are equivalent

developed

viour

architecture:

would cause

failure

"stuck-at"

(SA) f a u l t s

a non-symmetric

detection

procedures

beha-

are

given,

where possible.

2 - A REFERENCF. ARCHITECTURE:

Our first actual

goal

structure

scheme

of

micrographs

THE 16K EPROM

i s to f i t t h e a b s t r a c t of

Fig.

an

EPROM.

1,

of t h e

To t h i s

which

chip,

model p r e s e n t e d

was

end

we w i l l

obtained

the layout

by

in Part

refer

1 to t h e

to the

block

reconstructing,

of the devices

from

made by four

major

suppliers of 16K EPROEs.

~,] AIOT

-o

_rye__:

", ~, o °

'~- - I ' - ~ "

....

.

~o

"-

"

~

.

.

o~,

-~

I .

,2~

~

,0 o

j

I--'--

~ ___

~,0

=

' °

j',o°~

l

j

C'~/PGM

:~

,,,

,,

I

'~'

-.--

-----

----

~

~

....

--

'~

I '

11

....

,' • ; ~

"

-::

[iRAY11

SWI1CH

.__ p a 6T

L

VPP vPPL o

0"~ q

--INPUT

INPUT

i

i

O0 Fig. 1

Z.Z:

=1

I,'-m.I :'g~l-~SP., ~ F t

- .... ....

___.

-:t-

I ~_ I p1eo

~-

o

.-i-,= ~

-:::

l . )

A4 o

"°

.

I

=

-- 0 A5 ¢

__

!

O1

Detailed block scheme of a typical 16K E P R O M

The operating mode of the memory is determined by the voltage levels on pins PI8 (CE---/PGM), P20 (OE'---)and P21 (Vpp), which are connected to C, a combinatorial circuit generating voltage describes

levels the

between operating

~round modes:

and

six control signals, Vcc.The

Vpp L

truth

indicates

table

the

C 1 - C6, at of

logic

Fi~.

2

variable

K

EPROM application

~

L

0

1

PGM

0

0

READ

0

1

DISABLE INHIBIT

1

1

STDBY

PGM

1

0

STDBY

-

VFY

OUTP

Fig. 2 associated

with

989

PGM

O p e r a t i n g modes e s t a b l i s h e d by P I 8 , P20 a n d VPPL the two p o s s i b l e v a l u e s of the v o l t a g e at Vpp

(5V or

25V). Positive logic is used for the discussion. The

eleven

address

buffers, el0 +¢tiO,

bits, A 0 + AIO, are connected to the address

which

provide the eleven regenerated

address bits,

AOT + AIO T, and their complements AOF + AIO F. In the absence of faults, AnT = An . C2, and AnF -'=~n The

term

C2"

C 2 = PI8 + Vpp L forces both AnT and AnF to logic "0" in (i) , so that power dissipation on the NOR decoder circuits

standby mode

is minimal. In the other modes of operation AnT and AnF follow An and A-n' respectively. Let us first consider the rows (addresses A& + Al0).The select .~ates of the memory matrix are driven by the "I of 128 decoder"; the voltage level on these ~ates should switch between 0 and 5V normally, between 0 and

25V

durin~

programming. To this end, a set of Controlled Level (2) Translators (CLT) , raises the high level output to Vpp when C I -= PI8 ~ P20 "Vpp L = 0 indlcates the P R O G R A M mode. With

reference

submatrix

to column

decoding,

the

analog

switches of each

are arranged in two arrays of eight, driven by the "i of 8"

decoder (addresses A 1 - A3), and two more switches (address AO), select the group. Once more, CLTs are required to allow a correct transfer of the programming voltage through the analog gates. (i) In some manufacturers' decoder

by

the

address

layouts this condition is realised on the row 4 only,

and

does

not apply

to the column

decoder.

(2) Some

manufacturers

use

decoders, not shown in fi~. I.

a

second

set

of CLTs

in

front of

the

990

S. ALLINEY et al.

The i n p u t and the

circuits

the drain memory

I/O pin,

plifier

a

the

occurrino

the switch

a "0" i s p r e s e n t oate

at

buffer

(o 0 -~ 0 7 ) ' e a c h which

is

path

b e t w e e n Vpp

array)

only when

the corresponding

has to be charred.

i n READ o r PGM VFY m o d e , circuits

3-State

3 - SYMMETRIC From

is

output

mode i s d i f f e r e n t

and

a low i m p e d a n c e

(through

that the floating

memory

to t h e

with

cell

i n PGM m o d e ,

indicating

connected

establish

of t h e s e l e c t e d

is

When t h e

- i 7)

(i 0

forced

to

the selected

cell

is

including

a sense

am-

HIGH-Z

whenever

the

from READ o r PGM VFY. FAULTS

structure

described

in the decoders,

it is possible to infer that

in the switch arrays a n d

faults

in the ii address

buffers can be described by matrices obeyinq the symmetry relations, if the remaining

peripheral circuits are functioning correctly.

Therefore,

accordino to the theory developed in Part T, these faults will almost be certainly sixteen

detected: hundred

this

means

transistors

covering

(nearly

somethinR between

2/3

of the

twelve an~_

peripheral

circuitry)

dependinq on the actual device considered. },.!ore in detail, eleven

the proof of the above

address

buffers

and

statement is immediate

the decoders.

Altoo.ether they

for the

represent a

r.

combinatorial network with 12 inputs (A 0 - A10 and ~.2) a n d 138 outputs (128 row

selections

and

8+2 column

selection c o m m a n d s ) .

In effect C 2

takes up the same value in PGM, PGb! V F Y and READ modes, so that the combinatorial

network

has

no

means

of

distinguishing

between

the

different operation modes, a n d its behaviour, even in presence of faults, will be the same in the three cases, verifying the s y m m e t r y hypothesis. The

proof

is slightly less direct for the switch arrays

multiplexer and

PGM

(3)

In this case the "high" input level m a y

VFY,

or 25V

in

PGM

mode.

In order

of the column be 5V in R E A D

to meet

the

symmetry

conditions, it is necessary for the truth table of the faulty circuit to be the same, irrespective of the input level. Taking met

into account the possible failure modes, this condition is always

apart

from

the

unlikely

case

of

a

large

positive

drift

of the

threshold voltage of the transistors in the switch array. If the resulting threshold is between 5V ded.

However

if the

and 25V the symmetry conditions are disregar-

anomalous

during the test sequence,

threshold

entire columns

voltage

is stable

at least

or .groups of columns will be

apparently "stuck-at-O" (SA0) in R E A D or P G M V F Y modes.

(3) s i m i l a r present

considerations

upstream.

can be developed

for the decoders,

i f CLTs a r e

EPROM application

991

4 - NON-SYMMETRIC FAULTS The

peripheral

circuits

which,

in

case

of f a u l t ,

may

cause

a

non-symmetric behaviour are: the control logic c , the eight I/O c i r c u i t s (Z0 - Z 7 ; o 0 - 0 7 ) and the controlled level t r a n s l a t o r s CLT. In

fact the control logic is just designed to d i s t i n g u i s h between the

various operating modes; as for the I/O c i r c u i t s , due to the physical s e p a r a t i o n of input and output, faults in the input c i r c u i t affect only PGM operation

and,

conversely, f a u l t s in the output c i r c u i t s mainly

affect PGM VFY and READ modes. We s h a l l consider those electric f a u l t s which can be modeled by single " s t u c k - a t " nodes.

4[~L~

~-

0 C5

.

7

oC4

1

P20 0

18T - " ~ 1 9 2oi'~21

P18 0 "1" 0

0C2

9c/.~

0C3

VPPL 0

0C6

Fig. 3 The c i r c u i t of

Gate level scheme of the control logic (~) the

description shown in operators

does

not

control logic

Fig.

3.

deserve

was

reduced

to

the

gate level

The actual implementation of the logic special

comments

since

it

is

based

on

s t a n d a r d n - c h a n n e l , depletion-load c i r c u i t r y , l t .turns out t h a t we must consider 29 nodes, i . e . 59 possible "stuck-at" f a u l t s . A quite similar a n a l y s i s was c a r r i e d out for the I/O c i r c u i t s : in the resulting loqic diagram of Fi~. £ we consider " s t u c k - a t " f a u l t s in 18 nodes. Before

discussing

in

detail

the

effect

of

the

SA f a u l t s ,

it

is

necessary to Rive more information about the Sense Amplifier (S) and the 3-State I n v e r t e r Buffer (B), whose typical implementation is shown in Fig.

5.

Whilst

in general logic "0" and

voltage

levels

respectively,

corresponds,

the

loqic

"I"

input

represent low and high of

the

Sense

Amplifier

in the electric c i r c u i t , to the presence ("I") or absence

992

S. ALLINEYet at.

.L,II'

to the cell m a t r i x

C2

6.

pI I I I

C30

.

C4

.

C5

.

3

4

I

1

C4 C). C6 0

:2L

2

14

I I I I

Vpp

[

On Fig. 4

Gate l e v e l scheme of the I/O c i r c u i t r y Vcc

i!

O0

Io

(a)

I Vcc i

O O

O

i

l- -q O O

H1 H2

I

H1

H2

O

1

1

0

0

0

I

0

1

-

-

1

HIGH Z

H1

Fig. 5

H2

a) Sense Amplifier b) T h r e e - S t a t e I n v e r t e r Buffer

(b)

EPROM application

993

("0") of a direct connection from node I (I0 in Fig. 4) to ground. The 3-State

Inverter

Buffer

makes

use

of two controls

H1 and

H2, and

operates according to the truth table of Fiq. 5b. Of the 57 possible $A faults in the Control Logic, 49 can be revealed by an accurate functional test, including the procedures outlined in Table I.

In a similar way,

30 of the 36 possible SA faults of an 120 circuit

are revealed as shown in Table I t .

TABLE I

FAULTV NODE

FAILURE MOPE

NU~ER OF

FAULTS

SA ~

SA I

I, 3, 6, 8, I0, 14, 15 19, 20, 22, 25, ~6, 29

1, 12, 16, I?, 18, 21 23, 24, 27, 28

The memory ~annot be programmed (CI = "I" i n PGM ~ d e )

23

~, 9, 13

I, 3, 4, 5, 8, 10, 11

The output goes i ~ mode

10

11, 12, 23, 24, 2?

2, 13, 22, 25, 26

The output impedance i s low i n STDBV ~ d e when ~/PGM i s high

16

14

Programming oecur~ i n PROGRAM INHIBIT mode

4, 5

HZ i n READ

10

Exceedingly long ~ F from C'-E, with ~ low The output g o ~ into HZ a f t e r several second~ in s t a t i c READ mode 15, 19, 20, 29

I?, 21, 28, 18 Finally, l e t which

are

us c o n s i d e r

UNPREDICTABLE

faults i n

commonly implemented

t h e controlled l e v e l

according to the

translators,

scheme of Fig.

6.

Transistor M2 is a r e l a t i v e l y resistive load which tends to pull up the load capacitance. Except in the PGM mode M1 always operates with a gate voltage V , and represents a small resistance in series to the cc input voltage signal. The favourable resistance ratio, in this condition, forces the output voltage to track the input closely. In PGM mode, the gate voltage of N~ '2 is close to zero: when the input si.~nal is low, M1, bein~ a depletion device, s t i l l conducts enough to bring the output low; when, on the contrary, the input is hi qh ('~Vcc), MI is turned off and M2 raises the output node to Vpp ('~25V). M.R. 22/5~F

S. ALLINEY et al.

994

Vpp

C1

~-~ M2 0

( ~I - - - ~ M1

t

0-- fI - -

I

I

'

I

C L

I I

Fig.

Controlled

6

Level Translator

TABLE II

FAILURE MODE

FAULTV NODE sA ~

NUI@BER OF FAULTS

SA 7

I, 1, 8

The memory cannot be programmed

2, 3, 4, 5, 6

(~ys ?, 8"

1)

O~tp~ i s ~b~ays "~" i n READ MODE

Atl the cJJ~ m e u ~ e ~ i v ~ y p r o g ~ e d { ~ y s ¢)

2, 3, 6

4, 5

1

UNPREDICTABLE

11, 12, 14, 15

I0, 18

The output is alway~ I i n READ MODE

9, 10, 13, 18

11, 12, 14, 15

The o~tp~t is always ~ in READ MODE

16, I t

I"I

HZ o~tput

9, 13, 16

UNPREDICTABLE (in~reased pow~ d~sipation)

This network three,

implements

two-level

is clear

that

inputs:

a three-level I (0V,

the classical

5V),

logic CI

function

O (OV, 5V, 25V) of

(OV, 5V) a n d

SAO o r SAt f a u l t

V

(SV, 25V). I t PP m o d e l s a r e of l i t t l e h e l p i n

this case. Vle

therefore

exhaustive

list

preferred of

possible

to

limit

electric

our

analysis

faults

shown

to in

the

Table

relatively Ill.

It

is

EPROM application

995

TABLE I I I

FAILURE MODE

FAILURE MECHANISM

I

Missing eonnectA~n to Vpp

2

M2 s t u c k open

I t ,66 not ~ o s s ~ l e to program t h e memory c e l t 4 s e l e ~ e d

3

O sho~

t~ Vcc

4

O short~

t~ GROUND

5

0 shorted to CI

6

0 shorted to f (MI s t u c k ~ o s ~ d )

7

O shorted t~ Vpp

8

MI s t u c k open

M~Ltiple s ~ e ~ n READ and PROGRAM. S~t~ie fault

9

I

UNPREDICTABLE

shorted t~ CI

found that, memory tests,

by t h e f a u l t y CLT

in 8 of the 9 c o n s i d e r e d c a s e s ,

matrix

exhibit

an

anomalous

dw~ng

e n t i r e rows or c o l u m n s of the

behaviour

durin~

the

functional

so t h a t the f a u l t is s a f e l y d e t e c t e d .

5 - CONCLUSIONS

T h e following E P R O M

failure modes were considered in this work:

i)

"stuck-at"

storage elements;

ii)

faults,

the

in

peripheral

circuitry,

which

may

be

modeled

as

SDFs;

faults

iii)

in

the

peripheral

circuitry

which

cannot

be modeled as

SDFs.

It w a s screened

found in Part I that faults of ~roup i[) can be effectively

by

pro.qramming

and

verifying

a

test pattern

including

a

physical diagonal of "O's", and that failure detection is not impaired by the simultaneous presence of faults of groups [) and iii), provided that two additional patterns, "all ones" and "all zeros" are verified. The analysis carried out in this paper demonstrates that, in a large part of the peripheral circuitry, logic faults can be modeled as SDFs a n d are

easily

detected,

provided

they

do

not

transform

combinatorial

circuits into sequential ones. That part of peripheral circuitry, which is not covered by the SDF model was

analysed

at the gate level, under the assumption of single

996

S. ALLINEY et al.

"stuck-at" faults. The results show

that,

even

for these circuits, fault coverage is quite

satisfactory if some additional steps are inserted in the test sequence. Although developed with reference to a specific architecture, most of the

conclusions

of

this

architecture is c o m m o n

work

have

general

validity,

since

this

to the great majority of commercially available

devices. AKNOWL EDGEMENTS The

authors

manuscript

wish

and

Mr

to thank A.

Mrs

P.

Maggio

for carefully

Fantini for the drawings.

editing

the

The encouragement of

prof. E. De Castro and dr.G. Mattana is gratefully acknowledged. REFERENCES

1

S. Alliney, F. Fantini and C. Morandi, Microelectron. Reliab., 22, 965 (1982)