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European Conference on Electronic Design Automation EDA84
358
Integration
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European Conference on Electronic Design Automation EDA The European Conference on Electronic Design Automation EDA is the second in a series of biennial conferences. EDA will start with an opening address by B. W. Oakley, the director of the UK Alvey program. Then in a quick succession 52 technical papers are presented. Session A. The role of design automation Al “The UK5000 project: A collaborative approach to achieve design automation”. J.R. Grierson. British Telecom (United Kingdom). A2 “Management of computer aids to design. manufacture and testing in a large electronics company”. T.S. McLeod. Plessey (United Kingdom). Session B. Simulation and circuit analysis Bl “The design of a hierarchical circuit-level simulator”, M. Zwolinski and K.G. Nichols, Southampton University (United Kingdom). B2 “A circuit analysis program using an attached array processor-FFINAP-AP”. T. Kage et al., Fujitsu (Japan). B3 “An interpreted code sparse matrix solver which beats generated machine code for simulation of large circuits”, D.G. Agnew, Northern Telecom Electronics (Canada). B4 “An eight-value modelling technique for logic simulation of transmission gates and buses”, C.B. Almeida and M.J.A. Lanca (Portugal). Session C. VLSI design systems Cl “Systematic design methodology and performance verification for digital macro systems”, J.S. Saini and E.J. Zaluski, Rediffusion Computers Ltd. (United Kingdom). C2 “An approach to VLSI logic design”, L.F. Saunders, IBM (U.S.A.). C3 “Custom CMOS design using the ASTRA CAD system”, P.A. Ivey and M.C. Revett, British Telecom (United Kingdom). C4 “On the integration of a CAD system for IC design”, E.M. DaCosta, TELEBRAS (Brasil). Session D. From resting to manufaclure Dl “The CIRRUS test generation system graphics interface”, B.D.V. Smith, Cirrus (United Kingdom). D2 “Integrating computer aided design and test”, P. Jennings, Marconi (United Kingdom). D3 “Auto PL/T”, T.J. Kristek et al., IBM (U.S.A.). D4 “PL/T for the graduate tester”, C.W. Basil, IBM (U.S.A.). D5 “Computer aided equipment for prototyping thick film hybrid circuits”, J.F. Herington et al., British Telecom (United Kingdom). Session E. Systems design and data management El “An information systems analysis of the design of complex systems”, A.C.W. Finkelstein. Royal College of Art (United Kingdom). E2 “IBM personal computer PCB design and release methodology”, J.C. Porsch et al., IBM (U.S.A.).
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News
359
E3 “Integration tool for computer aided design systems (ICADS)“, P.J. Horth and K.J. Baker, British Telecom (United Kingdom). E4 “Data management in the DAX design automation system”, D.C. Harwood, ICL (United Kingdom). E5 “Computer-aided implementation of microprocessor application system”, J.A. Bowen, Reading University (United Kingdom). Session F. Tesr and testability of systems and circuits Fl “Petri net test generation on systems”, T. Alukaidey and G. Musgrave, Brunei University (United Kingdom). F2 “New method of functional testing of digital systems described by RTL”. E. Villar and S. Bracho, Cantabria University (Spain). F3 “Behavioural test method of microprocessors and automated generation: The GAPf system”, C. Bellon et al.. IMAG (France). F4 “Fault mechanisms, fault effects and their influence on test pattern generation for MOS chips”, R.J. Wilkins et al., British Telecom (United Kingdom). Session G. h~our for VLSI Gl “Describmg integrated circuit layouts in Pascal: Techniques and conclusions”, D.J. Kinniment and S.S. Dlay. University of Newcastle upon Tyne (United Kingdom). G2 “SYLAM: An adaptive symbolic layout system”, C. Landrault et al.. Languedoc University (France). G3 “Optimal VLSI layout data parameters for hierarchical analysis”, D.K. Milligan and J.W. Ugwu, Brunei University (United Kingdom). G4 “Logic and topological design in MOS technology”. G. Maupetit and G. Saucier, IMAG (France). Session H. Design ueri/ication of systems Hl “A multilevel mixed state simulator for hierarchical design verification”, S. Hodgson. ICL (United Kingdom). H2 “Computer-aided design of microsystems”, A.D. Ivannikov and P.P. Sipchuk, Moscow Institute of Electronic Machine Building, Moscow (U.S.S.R.). H3 “Timing evaluation of logic design”, A. Kay and C. Oldland, ICL (United Kingdom). Session I. Design automation worksrations and hardware 11 “A front end graphic interface to the first silicon compiler”, J.H. Nash, Edinburgh University (United Kingdom). 12 “An engineering design workstation for the autolayout of ULA gate arrays”, F.R. Ramsay, Ferranti (United Kingdom). 13 “Computer aided engineering and engineering workstations at BAe-dynamics group”, R.D. Roe, British Aerospace (United Kingdom). 14 “Wire routing on a raster pipeline subarray machine: Hardware support for design automation”, T.N. Mudge et al.. Michigan University (U.S.A.). Session J. Design of gate arrays Jl “A function testable design of programmable logic arrays”, G. Musgrave and Chongxun Zheng, Brunei University (United Kingdom). 52 “Texas Instruments logic array design system”, C.K. Thomas, T.I. (United Kingdom). 53 “A microelectronic gate array designed to give efficient automated circuit implementations”, A. McDonald, Bath University (United Kingdom). Session K. Design verificaiion of VLSI Kl “CADOC: A functional specification
and simulation
tool”, P. Amblard
et al., IMAG
(France).
360
Infegration
News
K2 “Architecture of a conversational symbolic simulator for the digital circuit design”, E. Chouraqui et al., CNRS (France). K3 “Timing verification of large digital circuits”, M.J.A. Lanca and I.M.C. Teixeira, CEAUTL (Portugal). Session L Testing and testability of VLSI Ll “One-chip microcomputer design based on isochronity and selftesting”. L. Spaanenburg et al., Twente University (The Netherlands). L2 “Intelligent assistance for test program generation”, C. Robach. IMAG (France). L3 “Complete multiple fault detection test set generation for programmable logic arrays”, J. Rajski and J. Tyszer, Poznan University (Poland). L4 “Computation of the critical area in semiconductor yield theory”, A.V. Ferris-Prabhu, IBM (U.S.A.). Session M. Placement for Ml “An automatic chip M2 “Parallel placement M3 “Classification and IMAG (France).
VLSI planning tool”, P. Antognietti et al., Genua University, Genua (Italy). for structured VLSI”, G. Saucier and P. Chaisemartin, IMAG (France). comparison of different strategies for structured logic”, A. Bellon et al.,
Session N. Specification design languages Nl “A hierarchical hardware description language”, M. Miyata et al., Toshiba (Japan). N2 “A concept for computer hardware description on the register transfer level”, K. Kuchcinski, Politechnika Gdanska (Poland). N3 “A VLSI design language incorporating self-timed concurrent processes”, D.J. Allerton et al.. Southampton University, Southampton (United Kingdom). N4 “Hack: A hardware compiler kit”, S.J. Baker et al.. Philips (United Kingdom).
Integration
News
European Conference on Electronic Design Automation EDA The European Conference on Electronic Design Automation EDA is the second in a series of biennial conferences. EDA will start with an opening address by B. W. Oakley, the director of the UK Alvey program. Then in a quick succession 52 technical papers are presented. Session A. The role of design automation Al “The UK5000 project: A collaborative approach to achieve design automation”. J.R. Grierson. British Telecom (United Kingdom). A2 “Management of computer aids to design. manufacture and testing in a large electronics company”. T.S. McLeod. Plessey (United Kingdom). Session B. Simulation and circuit analysis Bl “The design of a hierarchical circuit-level simulator”, M. Zwolinski and K.G. Nichols, Southampton University (United Kingdom). B2 “A circuit analysis program using an attached array processor-FFINAP-AP”. T. Kage et al., Fujitsu (Japan). B3 “An interpreted code sparse matrix solver which beats generated machine code for simulation of large circuits”, D.G. Agnew, Northern Telecom Electronics (Canada). B4 “An eight-value modelling technique for logic simulation of transmission gates and buses”, C.B. Almeida and M.J.A. Lanca (Portugal). Session C. VLSI design systems Cl “Systematic design methodology and performance verification for digital macro systems”, J.S. Saini and E.J. Zaluski, Rediffusion Computers Ltd. (United Kingdom). C2 “An approach to VLSI logic design”, L.F. Saunders, IBM (U.S.A.). C3 “Custom CMOS design using the ASTRA CAD system”, P.A. Ivey and M.C. Revett, British Telecom (United Kingdom). C4 “On the integration of a CAD system for IC design”, E.M. DaCosta, TELEBRAS (Brasil). Session D. From resting to manufaclure Dl “The CIRRUS test generation system graphics interface”, B.D.V. Smith, Cirrus (United Kingdom). D2 “Integrating computer aided design and test”, P. Jennings, Marconi (United Kingdom). D3 “Auto PL/T”, T.J. Kristek et al., IBM (U.S.A.). D4 “PL/T for the graduate tester”, C.W. Basil, IBM (U.S.A.). D5 “Computer aided equipment for prototyping thick film hybrid circuits”, J.F. Herington et al., British Telecom (United Kingdom). Session E. Systems design and data management El “An information systems analysis of the design of complex systems”, A.C.W. Finkelstein. Royal College of Art (United Kingdom). E2 “IBM personal computer PCB design and release methodology”, J.C. Porsch et al., IBM (U.S.A.).
Inregration
News
359
E3 “Integration tool for computer aided design systems (ICADS)“, P.J. Horth and K.J. Baker, British Telecom (United Kingdom). E4 “Data management in the DAX design automation system”, D.C. Harwood, ICL (United Kingdom). E5 “Computer-aided implementation of microprocessor application system”, J.A. Bowen, Reading University (United Kingdom). Session F. Tesr and testability of systems and circuits Fl “Petri net test generation on systems”, T. Alukaidey and G. Musgrave, Brunei University (United Kingdom). F2 “New method of functional testing of digital systems described by RTL”. E. Villar and S. Bracho, Cantabria University (Spain). F3 “Behavioural test method of microprocessors and automated generation: The GAPf system”, C. Bellon et al.. IMAG (France). F4 “Fault mechanisms, fault effects and their influence on test pattern generation for MOS chips”, R.J. Wilkins et al., British Telecom (United Kingdom). Session G. h~our for VLSI Gl “Describmg integrated circuit layouts in Pascal: Techniques and conclusions”, D.J. Kinniment and S.S. Dlay. University of Newcastle upon Tyne (United Kingdom). G2 “SYLAM: An adaptive symbolic layout system”, C. Landrault et al.. Languedoc University (France). G3 “Optimal VLSI layout data parameters for hierarchical analysis”, D.K. Milligan and J.W. Ugwu, Brunei University (United Kingdom). G4 “Logic and topological design in MOS technology”. G. Maupetit and G. Saucier, IMAG (France). Session H. Design ueri/ication of systems Hl “A multilevel mixed state simulator for hierarchical design verification”, S. Hodgson. ICL (United Kingdom). H2 “Computer-aided design of microsystems”, A.D. Ivannikov and P.P. Sipchuk, Moscow Institute of Electronic Machine Building, Moscow (U.S.S.R.). H3 “Timing evaluation of logic design”, A. Kay and C. Oldland, ICL (United Kingdom). Session I. Design automation worksrations and hardware 11 “A front end graphic interface to the first silicon compiler”, J.H. Nash, Edinburgh University (United Kingdom). 12 “An engineering design workstation for the autolayout of ULA gate arrays”, F.R. Ramsay, Ferranti (United Kingdom). 13 “Computer aided engineering and engineering workstations at BAe-dynamics group”, R.D. Roe, British Aerospace (United Kingdom). 14 “Wire routing on a raster pipeline subarray machine: Hardware support for design automation”, T.N. Mudge et al.. Michigan University (U.S.A.). Session J. Design of gate arrays Jl “A function testable design of programmable logic arrays”, G. Musgrave and Chongxun Zheng, Brunei University (United Kingdom). 52 “Texas Instruments logic array design system”, C.K. Thomas, T.I. (United Kingdom). 53 “A microelectronic gate array designed to give efficient automated circuit implementations”, A. McDonald, Bath University (United Kingdom). Session K. Design verificaiion of VLSI Kl “CADOC: A functional specification
and simulation
tool”, P. Amblard
et al., IMAG
(France).
360
Infegration
News
K2 “Architecture of a conversational symbolic simulator for the digital circuit design”, E. Chouraqui et al., CNRS (France). K3 “Timing verification of large digital circuits”, M.J.A. Lanca and I.M.C. Teixeira, CEAUTL (Portugal). Session L Testing and testability of VLSI Ll “One-chip microcomputer design based on isochronity and selftesting”. L. Spaanenburg et al., Twente University (The Netherlands). L2 “Intelligent assistance for test program generation”, C. Robach. IMAG (France). L3 “Complete multiple fault detection test set generation for programmable logic arrays”, J. Rajski and J. Tyszer, Poznan University (Poland). L4 “Computation of the critical area in semiconductor yield theory”, A.V. Ferris-Prabhu, IBM (U.S.A.). Session M. Placement for Ml “An automatic chip M2 “Parallel placement M3 “Classification and IMAG (France).
VLSI planning tool”, P. Antognietti et al., Genua University, Genua (Italy). for structured VLSI”, G. Saucier and P. Chaisemartin, IMAG (France). comparison of different strategies for structured logic”, A. Bellon et al.,
Session N. Specification design languages Nl “A hierarchical hardware description language”, M. Miyata et al., Toshiba (Japan). N2 “A concept for computer hardware description on the register transfer level”, K. Kuchcinski, Politechnika Gdanska (Poland). N3 “A VLSI design language incorporating self-timed concurrent processes”, D.J. Allerton et al.. Southampton University, Southampton (United Kingdom). N4 “Hack: A hardware compiler kit”, S.J. Baker et al.. Philips (United Kingdom).