I2L speed improvement by an ion implantation modification to a standard bipolar process

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2L

1 speed improvement by an ion implantation modification to a standard bipolar process by J. P. Pieters, A. G. K. LutschandH. F.leRoux Rand AfrikaansUniversity,Johannesburg,South Africa

A techniqueis described of the modification of a standardbipolarprocess by the addition of a single ion implantationstep with one extra photo mask to give a relatively high speed-power productand a high yield ofanalogcompatible 12 l circuits. The method is flexible in thatthe 12 l device characteristicsare determined mainly by the ion implantationparameters,and the rest of the bipolarprocess can be tailoredfor analogdevice requirements.Experimental results are presented which show an 12 l f3up of 6 per collector for the npn transistorsand a speed-power product of 0.5 pJ for a fan-outof 4.

1. Introduction For many applicationsit is advantageousto combine digital and analog circuitry on the same integrated circuit chip. IntegratedInjectionLogic (PL) 1.2 is a dense, low power logic family which is ideally suited for such analog-digitalcombinations.The factthatPL can be produced through a general-purpose standard bipolar technology;' makes it very attractive as an analog-compatiblelogic type. Many research institutions favour a standard bipolar process as a general purpose technology for producing test structures. With one basic process, not only can analog ICs capableof fairly highfrequency be produced, but also digital ICs up to a high packing density. 2. Optimisation approach As mentioned above, the standard process which was tailored for optimum analogdevice characteristicsshould not be tampered with. We wish only to add one or more process steps for the manufactureof the critical parts of the PL devices. The non-criticalparts of a typical FLstructureare the injectorand theareasofthe npn basearoundthe contactand aroundthe collectors. The only really important part of the I2L cell is the area of the baseimmediately below each collector, as well as the collectors themselves. This latter area is called the "active"area. The process parametersnecessary for optimum PL performanceare different from those necessary for optimum analog performance. This implies a trade-off between the characteristics of the IlL circuits and those of theanalogcircuits if the two types are to be made on the same chip. These compromises in process parametersmake it difficult to keep to existing standard process schedules. In order to achieve standardisationit is necessary to keep the process parametersfor the analog devices fixed, and to add aseparateprocess step (or steps) for manufacturingthe digital devices, with the further constraint that these extra process steps should not have anappreciableeffect on the performanceof the analog devices. MICROELECTRONICS JOURNALVol 14 No 2 © 1983 Benn ElectronicsPublicationsLtd. Luton

27

12l speed improvement by an ion implantationmodification etc continuedfrompage27

3. Process considerations The important parametersto be considered for improving the clock frequency of operation and the speed-power productare the upwardscurrentgain,f3up, and the minimumdelay time, T d. In terms of processing parameters,these are given by: f3up =

j-1

A c [1+F(I-A cl Ab)fNb dX + (F+l)SpfN bdx fNbdx

Ab

OnNepi

... (1)

and Td

=

AAbc

l-2(F+l)WePif Nb ON N epi

dX

l_

-I

... (2)

where the various terms are: the upwardscurrentgain the areaof one collector (active base area) the total base area, which includes the active area of one base and the non-active area of one base measured between the symmetry lines between adjacentcollectors the numberof collectors (which is also the fan-out) F j Nj dx = the Gummel numberof the active base areaonly j Ng dx = the Guinmel numbercorrespondingto A b the surfacerecombinationvelocity Sp the "effective" diffusivity of minority carriers in the base, including On electric field effects the doping concentrationin the epitaxial layer N epi the correspondingepitaxial layer thickness W epi the minimum gate delay time Td Furthermore,the breakdown voltage for a narrow-basebipolar structureis given by:' Vpt

= -q- [(fNl,dX)2 2€r€o

N,

J

I + WbfNb dx

.... (3)

where:

v, q

the punch-throughbreakdown voltage electronic charge relative permittivity of silicon absolute permittivity of free space impurity concentrationin the collector effective base width

The above equations show clearly not only the constraintsinvolved, but also the possible areas of improvement of both the analogand I2L sections of the chip. Apart from layout changes (alterationof A c and A b) it is possible to improve both f3up and T d by increasingthe doping density in the epitaxial layer, N epi- This has the unfortunateeffect of decreasingthe breakdown voltage of the analogtransistors,for which the epitaxial layer is the collector. Similarly, to decrease the integralbase doping in the active area (the Gummel number fNl, dx) will increasef3up and decrease Td' but will also decrease breakdown voltage V pt of the analog transistors.The numberof collectors F, or the "fanout", is determined by the circuit function. 28

Table I Process flowchart

! 1

Clean type substrate

13

Photolithography, windows for analog emitter

14

Phosphorous diffusion to form emitters (shortened time)

'if'

2

3

1

First ox i da t i on

r

Photolithography, windows for buried layer

-1

~ 4

Apply Arseno-silica film

5

Arsenic diffusion to form buried layer

15

Photolithography, windows for 12 L collector areas

16

Ion Implantation: B: high energy,low dose, for 1 2L active base.

!

1

~ 6

Remove

5i0 2

As: low energy, high dose, for 1 2L collectors.

J. 7

Grow epitaxial layer

1

! 8

Second oxidation

17

Annealing and reoxidation

18

Photolithography, contact windows

1

! 9

Photolithography, windows for isolation reg ion

10

Boron predeposition and diffusion to form isolation

11

Photolithography, windows for analog base, and 12 L non-active base

12

Boron predeposition and diffusion to form analog and 12 L non-active base areas

1 19

1 Evaporation of Ti-Al I'letallization structure

1

1 20

Photolithography, definition of interconnection pattern

1

! 21

Alloying, passivation and encapsulation

t One aspect that does not come out clearly in the aboveequations,is the emitter efficiency." In the normal bipolar structurewith the highly doped emitter on top having a smallerarea than the base, and the base having a doing densitygradientthat is negative (decreases away from the surface) and the epitaxial layer being even more lightly doped than the base and having a big area and a wide space-charge layer, one finds that the injection efficiency of minority carriers into the base is very high, Furthermore,the injected carriers are being accelerated by the built-in electric field (due to the doping gradient) in the base, and are efficiently collected at the large base-collector junction. In I2L however, all the above is reversed. Now, the top n" structurewith a small cross-sectionalareais being used ascollector and the carriersare injected from the epitaxial layer which is used as theemitter. Injection into the base takes place througha n-p junctionyielding only a low injection efficiency. The 29

12L speed improvement by an ion implantationmodification etc continuedfrompage29

Table II Process Step

Material

First oxidation Buried layer

Value 1.2JLrn

As

Epitaxial layer Second o xid at ion Isolation diffusion Base diffusion (analog) Ernitterdiffusion Acti ve ba se (12L)

P

B

As

I x lOt6 crn-2

B P

Metallisation

Ti.AI Ct

B

14urn.100/V 6.5 j-Lrn. 0.75 O·crn 1.0JLrn 11 - 14 JLrn. 28 - 35 O/V 1.8JLrn. 80 - 90 O/V 1.8 pst» , 5 O/V 1.-5 "X 1012crn-2

B

Collectors (12L)

INJ

Typical process parameters

C2

1.1 JLrn. Al

C3

p

Ct,

p

n

epitaxial layer

n+

buried layer

P

substrate

Fig. 1 Cross-section of the 12L structure.

fortunate few carriers that make it into the base are repelled from the coll ector by the "uphill"electric field in the base, and have areduced probability of being collected due to the small collector area. It is clear therefore, that ifoptimum analogand digital devices are to be on the same chip, one must segregate some of the process steps for the analogpart of the chip from those that determine the IlL part. 4. Description of process modification Bearing in mind the principlethat the process modification should not have an effect on the analogcircuitry, and that it should not be too complicated so that the overall yield isreduced or the price per chip pushed up too seriously, the following scheme was decided on: (i) to manufacturethe non-active I2Lbase areas simultaneouslywith the analog bases; (ii) to do a normalemitter diffusion in the analog areas, but for sahorteneddiffusion time; (iii) to then open up the FLcollector areas(which are also the active base areas) using one extra photomask; (iv) to implant boron ions at a highenergy and a low dose, for the future I2L active base areas, and then arsenic ions at a low energy and high dose for the2L I collectors; 30

As; '0 keY

i x 1016 cm-2

22 10

B: '00 keY

,.

2xi012 cm-2

I I

900 "c. - 30 min OX; 1000 ·C - 50 mn

AN~Al:

I I

21 10

I

I

;..",.---- ...... "/

B

/

15 10

,

/

+-~~-----+------T---F----------'<-.....- - - I

o

O~

0,2

0.3

0.'

0.5 depth

0.6

IfJml

0.7

0.6

0.9

1.0

1.2

1.3

Nepi

1.'

•

Fig.2 Collective impurity profiles in the active base.Brokenlines:as-implanted.Solid lines: after subsequentdiffusion.

(v) to do annealingandthena surfacere-oxidationafterwhich the process iscompleted in the normalway; except for (vi) the metallisation, which would consist of a thin layer of titanium followed by the normalthickness of aluminium. In this way the analog characteristics are unchanged and the 12L characteristics are determined by the ion implantationparametersalone, thus making it possible to choose an optimum active base concentrationand profile for relatively high injection efficiency, low doping density, fNbdx, and low collector doping density. It is thus possible to vary the I2L device characteristicson a wafer-to-wafer basis without disturbingthe analog circuit characteristics and in this way to have some low-power 12L and some high speed 12L, or any other desired characteristic,in the same batch. 31

W N

N

r-

7

t3' "0

6

~

•

Rl

3 Rl

a C"

5

-< III

:I

0'

i

:I

3'

4

8up

I

-=

"2l»

-=

_/

"\ .~

h

:I

near collector ~. o

:I

3

s 3i

3

~

s

:I

...o~

2

:::J

g. ~ Q.. :;-

3

far collector

o

'g ~

t.)

Iii

100pA

i

I

Iii

1nA

I

,

I

'

Iii

ii'

10 nA

100nA

Ib Fig.3

I

i

I

lt1JA

i i iI

Iii

10t1JA

IAI - .

Upwardscurrent gainf3 u[I as functionof collcctorcurrent.

iii

100,uA

i i i ' I

lmA

i

I

I

'I 10mA

10- 4

"

10-5

fJl

aI .&J

III 0'

10-6

W

& >.

III

~

~ 10-7

----1,1 ns

0,1 pJ

Ij-:---,i----.~-

10- 8 I

1.0-

w w

8

I

I

i

I 10-7

i

•

•

'I

10. 6

'

I

, . '"

10-5

" 0:5PJ,,1 pJ '

'I

I

"

-..,-

'''I

'I

1

10-1,

Power dissipation per gate (W) Fig.4 Delay time per gate as a function of power dissipation pcr gate.

..,- i

-----.

I

i

I

10. 3 '

.

I

10-2

12L speed improvement by an ionimplantationmodification etc continuedfrompage33

5. Experimentalresults Table I shows the process flow chartof the modified bipolarprocess, andTable II shows some relevant process parameters. Figure 1 shows a cross-section of an FL unit cell manufactured with this process, and Fig. 2 shows the collective impurity profiles in the active base areaafter implantation(dotted lines) and after subsequenthigh temperaturesteps. Test chips manufacturedwith the standard unmodified process and chips manufactured with the ion implantation modification in conjunction with the standard process were evaluated, and the results obtained are in the following figures and tables. Figure 3 shows the upwards current gain, {3up, as a function of collector current for the innermostand outermost collectors of a 4-collector 12Lgate. Figure 4 shows the delay time per gate as function of power dissipation per gate, as measuredon an eleven-stage ring oscillator making use of each of the fourcollector positions and thus presentingan "average". Table IIIshows a pnp, the forwardcurrentgain of the lateralpnp transistor,{3up, the upwards gain of the vertical npn transistor, and PTd, the power-delay product, measured on devices made with and without the process modification. Table III Results

Parameter Q

pnp

f3up

(lOOJLA)

(lJLA)

PTd

Standard BipolarProcess!

Standard+ Ion Implantation Sub-Process

0.35 3.5 1.5 pJ

0.35 5 O.5pJ

6. Discussion The results clearly show that an improvement by a factorof3 in terms of power-delay product has been achieved throughthe introductionof this process modification. A high yield of good chips per wafer was also observed, due mainly to the highly repeatable and controllable ion implantationprocess steps. Although it has been demonstrated that the modification scheme is viable, it is possible to improve further the observed characteristics by refinement of the ion implantation parameters, by using different ion species, by using a different annealing scheme (laser annealing,or electron pulse annealing)or by using a different metallisationscheme." The process modification is not a costly one, becauseit requiresonly one extraphotomask. The two ion implantation steps can take place immediately after one anotherwithout the samples being removed from the vacuum. It is believed that this process description will be of value to many researchinstitutionsand laboratories who, like ourselves, do not have the luxury of many production lines, each tailored for specific device or circuit characteristics.Here is a process that allows one to vary the device characteristicsfrom wafer to wafer or from batch to batchwithout tamperingwith the standardprocess schedules.

7. Acknowledgment The authors wish to thank the Microelectronicsteam and the staff of .the IC Manufacturing Facilityofthe CouncilforScientificand IndustrialResearchunderthe leadershipofT. C. Verster and J. D. Stuiting respectivelyfor carryingout the standardprocess steps andfor valuable discussions.The BursaryGrant Divisionof the CSIRand RAU are thankedforfinancialsupport. 34

8. References [1] Hart, K. and Slob, A. , "IntegratedInjection Logic - A new approach to LSI", IEEEJournal of Solid State Circuits, SC-7, 5, 346 (Oct. 1972). [2] Berger, H. H. and Wiedman, S. K., " Merged TransistorLog ic (MTL) - A low cost bipolar logic concept",IEEEJournalofSolid State Circuits, SC-7, 5,340, (Oct . 1972). [3] Crooke, M., Verster, T . c., Lutsch, A. G. K., Greyvenstein, R. F. and Stulting , J.D., "Integra ted Injection Logic using non-optimised processes", Microelectronics, 8, 23-31 (1978). [4] Klaassen, F. M., "Device Physics of IntegratedInjection Logic",IEEETrans, Electron. Devices, ED-22, 145-152 (March 1975). [5] Gegg, W. M., Saltich, J. L., Roop, M. and George, W. L. , "Ionimplanted super-gaintransistors" , IEEEJournalofSolid State Circuits,SC-U, 4, 485 (August 1976). [6] Davies, R. D. and Meindl, J . D., " Poly I2L - A high speed linear-compatiblestructure", IEEE JournalofSolid State Circuits, SC·13, 4, 367-375 (August 1978). [7] Lui, S. K. and Meyer, R. G., "A highfrequency bipolarJFETFLProcess",IEEETrans. Electron Devices, ED-29, 8,1319 (August 1982).

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