Methodologies for full custom VLSI design

Transition to one micro technology: Part 2 PIETER B U R G G R A F SemiconductorlnL, 136 (June 1984) Only those semiconductor manufacturers who aspire toward "world class" cleanliness and manufacturing productivity will avoid impending yield catastrophes. Design system for semi-custom VLSI cicuits A. D. CLOSE, L. FIStlER, R. M. McDERMO'Iq', T.A. NIX, D. M. PERRINE andJ. M. SCHOEN Electl. Commun. 58,372 (1984) The IT]" semi-custom design system enables complex VLSI circuits to be designed rapidly with a high expectation of correctness on the first pass. Planned improvements will make it possible to produce semi-custom circuits that arc as complex as today's full-custom design circuits. Improved planar isolation with buried-channel MOS FET's II. SUNAMI, Y KAWAMOTO, K. S}IIMOHIGASI:tl and N. IIASHIMOTO Microelectron Reliab. 24,555 (1984) A potential VLSI MOS device called BGP (buriedchannel) graded-drain with punchthrough stopper) with planar isolation is characterized in terms of fabrication techniques and its deL,ice performance. This planar isolation approach has been realized using highly directional dry etching and through-field-oxide implantation. It features simultaneous formation of punchthrough and parasitic channel stoppers and an effective channel width almost equivalent to nominal one. Fundamental device characteristics such as short-channel and narrowchannel effects arc investigated. Good isolation performances are demonstrated in devices having 1/~m feature size at standard 5 V operation. Bipolar device packaging.electrical, thermal, and mechanical stress considerations L. M. M A I t A L I N G H A M and D. J. REED Solid St. Technol. 167 (May 1984) As semiconductor devices become more complex and operate at higher speeds, packaging becomes more critical. High thermal performance, good electrical performance and low levels of mechanical stress arc required in the package for the devices to operate as desired. In digital bipolar logic, perhaps the most demanding requirements are with ECL VLSI devices. While the demands arc the greatest with ECL, the behaviour of other bipolar logic families may also .be affected by packaging. Packaging is also critical in linear devices. Low cost 16 bit A/D and D/A converters will be difficult to achieve if stress is not managed. The special needs in the packaging of both IC and discrete bipolar devices are explored. A comparison of MOS processes for VLSI Part I H. E. OLDHAM and S. L. P A R T R I D G E Solid St. TechnoL 177 (June 1984) A comparison of semiconductor technologies for VLSI is presented with particular reference to the limitations imposed by fundamental technological and circuit design considerations. Unichannel MOS and CMOS in

single crystal silicon or insulating substrates are the primary subjects for discussion. From the viewpoint of fabrication technology there appears little to choose between PMOS, NMOS and CMOS approaches. I Iowever, CMOS processes are clearly emerging as being optimum for many types of circuit design. Further improvements are to be achieved by the utilization of silicon-on-insulator CMOS and it is concluded that this technology will have an important place in th'e VLSI era. Methodologies for full custom VLSI design J. DANNEELS and M. MEINCK Electl. Commun. 58,389 (1984) As the complexity of integrated circuits continues to increase at a rapid pace, new design methodologies and tools are essential to ensure correct, cost-effective design. The goal is to be able to produce a correct chip design from the initial functional specification with minimal human interaction.

5. Hybrids

Improved electrical performance required for future MOS packaging. LEONARD W. S C t t A P E R and DANIEL I. AMEY IEEE Trans. Components ttybrids Mfg Technol. Chmt6 (3), 283 (September 1983) }tigh speed integrated circuit (IC) families and the demands which these devices place on interconnection and power systems are compared, concluding the new materials, components and packaging techniques arc required to provide a nonlimiting electrical environment for high performance systems using metal-oxide semiconductor (MOS) technologies.

Direct attachment of leadless chip carriers to organic matrix printed ~'iring boards. R O B E R T W . KORB and DAVID O. ROSS IEEE Trans. Components Hybrids Mfg Technol. Chmt6 (3) 227 (september 1983) A test program was performed that compares the reliability of various leadless chip carrier (LCC) solder joint configurations under conditions of temperature cycling from-55 to + 125"C. Since there is a co-efficient of thermal expansion mismatch between the ceramic body of the LCC (6 ppmPC), it was of interest to determine the optimum solder joint configuration that results in maximum reliability after extensive exposure to temperature extremes. This configuration was determined to be the one that results in a 45 ~ solder fillet; consequently, the distance the printed wiring board (PWB) pad extends beyond the edge of the LCC is a critical requirement. For an pad LCC, this distance is 40 mils.'lnformation on the use of various substrates for leadless chip carriers is also discussed. 47