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or poly-silicon on the dielectric characteristics of very thin oxides
Solid-Sme Elerrronics Vol. 33, No. 3, pp. 365-373, 1990 Printed in Great Britain. All rights reserved
0038-I lOI/ 53.00+ 0.00 Copyright 0 1990 Pergamon Press plc
THE EFFECT OF GATE ELECTRODES USING TUNGSTEN SILICIDES AND/OR POLY-SILICON ON THE DIELECTRIC CHARACTERISTICS OF VERY THIN OXIDES H. C. CHENG’, C. Y. CHAO’,W. D. Su*, S. W. CHANG*, M. K. LEE* and C. Y. WV’ ‘Department of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan, Republic of China and *Electronics Research and Service Organization, Hsinchu, Taiwan, Republic of China (Received 12 May 1989; in revised form 31 August 1989) Abstract-The effects of gate electrodes made of tungsten silicides and/or polysilicon on the dielectric characteristics of very thin gate oxides have been studied. For a WSi,/SiO,(lOO A)/!5 gate structure, the phase transition from hexagonal to tetragonal WSi, and the induced stress demonstrated the degradation of dielectric strength of gate oxide annealed at 700°C. Tungsten diffusion to the interface between SiO, and Si substrate as well as the enhanced local strain caused the deterioration of breakdown fields for annealing temperatures above 900°C. Drastic generation of hole traps at 1OOOCannealing further diminished the field to breakdown of thin oxide. For WSi,/poly-Si/SiO,(lOO A)/Si and poly-Si/SiO,(lOfl A)/Si structures annealed at lOOo”C, phosphorus diffusion to the SiO,/Si interface was also harmful to the dielectric characteristics of gate oxides besides the high-temperature hole trap generation and the thermally induced stress. Hence, MOS capacitors of WSi,r/poly-Si/SiO,(lOO A)/Si structures seemed to be superior to the other two structures when the sheet resistivity factor was also considered. The effect of thickness of gate oxide on the dielectric properties of three gate structures was also investigated.
I. INTRODUCTION Due to advances device dimensions
in integrated circuit technology, are being scaled down and chip
sizes are currently increasing[l]. However, the speed advantages attained from the short-channel design of smaller components could be offset by the interconnect resistance at the gate leve1[2,3]. In addition, the higher complexity and the larger chip size also result in a sheet-resistance contribution to the RC time delay and power consumption. Polycrystalline silicon (poly-Si) which possesses the feature of ability to withstand high temperatures encountered during fabrication process and was conventionally used as the gate electrode in MOS devices, did not satisfy the requirements of very-large-scale-integrated circuits (VLSI) due to its high resistivity[4]. Hence, refractory metals such as molybdenum (MO) and tungsten (W) have been considered. They have not been widely used due mostly to the fact that they could not withstand the many chemical reagents used and the oxidizing ambients at high temperatures[S]. An alternative choice is to use either refractory metal silicides, such as TiSi,, TaSi,, WSi, and MoSi, or a double layer of the refractory metal silicides over poly-Si[1,6,7]. With the features of relatively low electrical resistivities, good protection against the chemicals and oxygen, oxidizable property, good reliability of contact with shallow junctions, and ability to define fine lines, these refractory metal silicides are quite promising as gate materials in VLSI technologies[ l&9]. On the other hand, it has been projected that dielectric thickness of an 1 Mbit DRAM in VLSI S.S.E. 33,LD*
circuits was about 100 A due to the miniaturization of MOSFETs[lO]. Various methods such as dry oxidation[ 11,121, wet oxidation[ 11,121, rapid thermal processing[ 131, and plasma-enhanced chemical vapor deposition (PECVD)[14], have been used to grow the very thin gate oxide. Generally these grown oxides with a thickness about 100 A exhibited the optimum breakdown fields ranged from 10 MV/cm to 16 MV/cm. It has also been proposed that defects near the Si02/Si interface tended to nucleate holes which enhanced the dielectric breakdown[lS]. In addition, Flowers[ 161pointed out that post annealing of polysilicon gates lead to “pile up” of doping species at the oxide/polysilicon interface and resulted in attendant yield loss and reliability problems in devices due to the defect generation in the gate oxide. Furthermore, gate-induced strain[l7] and hole trapping generation[l8] also affected the dielectric properties. Very careful evaluation of the applications of the silicides as the gate electrodes on the MOS devices should become more important as the thickness of gate oxide (SiO,) decreases with smaller device dimensions[5]. However, most of the previous reports concerning the effect of gate silicides on the electrical characteristics of gate oxides have concentrated on the relatively thick oxides, which had thicknesses ranging from 200 to 1800 A[2,5,6,9,19]. Hence it is necessary to investigate the effect of silicide gate electrodes on the electrical breakdown of the very thin oxide, with a thickness about 100 A, for practical applications of silicides in future submicrometer technologies. Although CVD WSi,v had the advantages of low resistivity, less contamination of oxygen, as well as 365
H. C.
366
(h?NG
good step coverage, and was becoming widely used, the fluorine included in the film was found to be harmful to the dielectric characteristics of gate oxide[ 191.Sputtering has therefore often been used to deposit the WSi, film as a gate material[rl]. In this work, we report the effects of gate electrodes with sputtered WS& on the dielectric breakdown of the gate oxide with various thicknesses. For comparison, work with poly-Si gate electrodes was also performed. 2. EXPERIMENTAL
DETAILS
15-25 R-cm, 4-in-diameter, (100) oriented P-type silicon wafers were used to fabricate the investigated MOS capacitors. After the HF dip cleaning, the wafers were oxidized at 920°C in dry O2 ambient to obtain the gate oxides with 100, 270 and 540A thickness, in-situ annealed at the same temperature for 30 min in N, ambient. One part of oxidized wafers were deposited with a layer of WSi, (x = 2.3) by a dc. Magnetron MRC 603 sputtering system. Alloy deposition was carried out in a chamber evacuated to lo-‘torr prior to backfilling with argon. The deposited thickness of the tungsten silicide was 2300 A. No substrate heating was used during the deposition. Consequently, the as-deposited film had a sheet resistance of 41 R/sq. Then, the MOS capacitors with 82 x 82 pm in area were plasma-etched by a DRIE plasma 100 system. These capacitors were classified as WSi,/SiOz/Si. The other part of the oxidized silicon wafers were deposited with a low-pressure chemical-vapor-deposited (LPCVD) polysilicon film of thickness about 4500 A and then doped by POCl, diffusion. After a drive-in process at 950°C in nitrogen ambient, these samples possessed two kinds of sheet resistance, i.e. 12 G/sq. and 20 R/sq. respectively. The samples with the former resistance were then patterned by the same etching procedure mentioned above and were classified as poly-Si/SiO,/Si. Those with the latter resistance were first deposited with a layer of tungsten-silicon mixture WSi, with the same conditions as those for WSi,/Si02/Si and then defined into the desired pattern by the two step plasma etching process. These specimens were therefore named as WSi,/poly-Si/SiO,/Si capacitors. To lower the sheet resistances of gate electrodes and investigate the electrical reliability of thin oxide after high-temperature processings, these three kinds of MOS capacitors were all then annealed in N2 ambient at temperatures ranged from 500°C to 1000°C. Nz gas was first purified by titanium getter before entering the annealing furnace. Electrical breakdown tests were performed by using a voltage ramp technique which involved ramping a stairwise voltage from 0 to 20 V on the capacitor and measuring the current across the device[20]. A breakdown event was detected by a sudden increase of the measured current (current snapback) and the voltage at the first snapback was recorded as break-
et
al.
down voltage Vbd. The time zero dielectric breakdown TZDB field EM was then estimated with the value of Vbddivided by the thickness of gate oxide. The linear ramping rate of stress voltage is 0.1 V/s. The gate electrode was negatively biased with respect to the P-type silicon substrate (gate injection) to avoid surface depletion and voltage loss in the silicon region, i.e. accumulation style. Measurements were performed with a HP 4145A semiconductor analyzer. A desk computer HP85 was also utilized to control this instrument. Constant-voltage-stressed currentvoltage measurements were used to confirm the breakdown characteristics. In addition, the sheet resistance (Rs) of WSi, silicides was also determined by a four point probe instrument for practical purposes in VLSI circuits. Microstructural examinations were used to explain the electrical characteristics of gate oxides with the WB, electrodes. Transmission electron microscopy was carried out with a JEOL200CX scanning transmission electron microscope operating at 200 kV. In order to investigate annealing effects on the gate oxides, Auger electron spectroscopy (AES) was also performed with a PerkinElmer PHI-590 Spectrometer. AES has been combined with an argon ion miller to provide the composition-depth profiles. 3. RESULTS AND DISCUSSION
3.1. Microstructures and composition-depth profiles Generally, tungsten silicide forms only in the WSi, phase as the thin film of tungsten reacts with the silicon substrate. Moreover, WSi, crystallizes in the hexagonal structure at low temperatures, the tetragonal phase at higher temperatures[l,21]. In order to understand the effect of the phase transition of WB, (x = 2.3) on the gate oxide, diffraction patterns of the specimens annealed at various temperatures for WSi,/SiO,/Si and WSi,/poly-Si/SiO,/Si gate structures were analyzed. The as-deposited WSi, film appeared to be near-amorphous. The hexagonal phase of WSi, was found exclusively at annealing temperatures 500°C and 600°C for both gate structures. Furthermore, the tetragonal WSi, formed at annealing temperatures above 600°C for these two structures. Dark-field micrographs were also taken to confirm this phase transition. The needle-like morphology of tungsten silicide for 500°C and 600°C annealings was observed. Examples are shown in Figs l(a) and 2(a) for WSi,/Si02/Si and WSi,/polySi/SiO*/Si, respectively. At annealing temperatures above 7OO’C, the silicide grains became rounded in shape and increased in average sizes from 300 to 1200 A, as shown in Figs l(b)-(c) and Figs 2(b)-(c) for WSi,/SiO,/Si and WSi,r/poly-Si/SiO,/Si, accordingly. The morphology transition from needle-like to rounded shape corresponds to the phase transition from hexagonal to tetragonal phase deduced from the diffraction analysis. This is consistent with the
Tungsten silicides as gate electrodes
361
Fig. 1. Dark-field (DF) micrographs of WSi,~iO,(lOO A)/% specimens annealed at (a) SOO”C,(b) 700°C
and (c) lOOO”C,respectively, insets corresponding diffraction patterns (DPs). previous report[l]. As compared with the published result[ 11, the delayed transition of tetragonal WSiz at slightly higher temperature and larger average grain size in this study could be ascribed to the difference of the deposition methods, i.e. sputtering in this work and LPCVD in the previous study. Hence, it is reasonable to say that the transition temperature from hexagonal to tetragonal WSi, is at the annealing temperature between 600°C and 700°C. Due to this
transition, the densities of defects such as stacking faults and dislocations etc. abruptly increased for the silicide structures annealed at this temperature[22,23]. This would seriously degrade the electrical characteristics of gate oxides in WSi,/SiO,/Si capacitors, which would be discussed in the Section 3.2. Figures 3(aHc) shows the AES depth profiles of WSi,/SiOz (100 A)/Si samples annealed at 7OO”C, 900°C and lOOO”C, respectively. The value (100 A)
368
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Fig. 2. DF micrographs of WSi,/poly-Si/SiO,(lOO &/Si samples annealed at (a) XMYC, (b) 700°C and (c) lOOO”C,accordingly, insets corresponding DPs. marked
after
the SiO, represents
the thickness
of
gate oxide. As can be seen, tungsten diffused into oxide at annealing temperatures above 700°C but did not arrive over the interface between oxide and Si substrate until 900°C. However, this phenomenon was not evident for the WSi,/poly-Si/SiO,(lOO A)/Si specimens even annealed at 1000°C. It is therefore conjectured that the dielectric properties of SiO, in WSi,/Si02(100 A)/Si should be affected by the
tungsten annealed
diffusion after these capacitors at temperatures above 900°C.
3.2. Electrical characteristics difSent gate structures
were
of thermal oxides with
In this section, we report the electrical properties of gate oxide with 100 A in thickness. The effect of oxide thickness on the TZDB field of gate oxide is then discussed.
Tungsten silicides as gate electrodes wsip, I SiO2(1ooA)/
--
Si
369
WSi~/SiO2(t&)r
Si
I
60-
60-
01 5
0
2
4
6
6
10
60 -
s 801
/
” Si
60
Time (min 1
WS&/Si~(lOOf~lSi 1000%
1
1
1
7
1
a
1
1
9
1
I
10
(100% I div.)
Fig. 4. Dielectric strength of WSi,/SiO,(lOO A)/Si structure as a function of annealing temperature.
60-
E
1
6
Annealing Temperature
12
Sputtering lime (min 1
Sputtering
1
1
-
Sputtering Time (min 1
Fig. 3. Auger depth profiles of WSi,/SiO,(lOO A)/.%samples annealed at (a) 7oo”C, (b) 9oo”C, (c) lOOO”C,respectively.
A. The electrical characteristics of gate oxide with lOOA in thickness. The curve of TZDB field strength vs annealing temperature for WSi,/SiO,/Si gate structure is shown in Fig. 4. The peak value of field strength, 1S- 16 MV/cm, occurs at annealing temperature about 600°C. Then the field has a sudden decrease at 700°C and exhibits a small variation at the temperature between 700°C and 800°C. For the
samples annealed at and above 9OOC, large drop of the strength was observed. Any improvement of the breakdown characteristics of gate oxides would require an improvement of the interface between SiO, and Si substrate [24]. This implies that the defects at the interface between poly-Si and SiO, degrade the quality of the gate oxide[25]. It is therefore surmised that the defects accompanying the phase transition from hexagonal to tetragonal WSir at annealing temperature between 600°C and 700°C play an important role in the deterioration of the breakdown field of the gate oxide. It has been reported[26] that the interface traps in metal/SiO,/Si capacitors depended on the initial damage level, the gate-induced stress, and the presence of certain chemical impurities or bonding defects in the gate oxide. Strain is induced in the silicon-dioxide by the difference between the thermal expansion coefficients of the gate electrodes and the silicon-dioxide[ 171. The strained bonds may be more readily broken by ionizing radiation or high-field electrical injection than unstrained bonds[27]. Therefore, both the generated defects at the electrode_SiO, interface and the induced stress in the SiOr enhance the formation of interface traps or trapped charges which cause the degradation of the dielectric film. As the annealing temperature rises to 9OO”C, the field strength of gate oxide rapidly falls. This could be interpreted by tungsten diffusion over the interface between SiOr and Si substrate, as shown in Fig. 3(b). It has been reported that increased substrate heating temperature during molybdenum sputter deposition could affect the gate oxide quality by increasing MO atom penetration into the oxide[28]. Hokari et a1.[29] also showed that the inferior reliability in a MOS capacitor with a metal sintering anneal was caused by aluminum precipitates at the poly-Si/SiO, interface. Transition metal particles such as tungsten were even indicated to enhance the creation of electrical defects in gate oxide layer[30]. Moreover, a dielectric-breakdown model had been established by Hu et a1.[24,25] who suggested that the dielectric breakdown process could be
370
H. C. CHENG et al.
divided into two stages. The “early” breakdowns were caused by the “weak oxide area” which was weak because of a particularly high density of hole traps or large hole capture cross section at the local spot, or because of thinner oxide thickness, or lower effective barrier at time zero due to particulate contamination, crystalline defects or interface asperities in the silicon[25]. Hence, it is conjectured that the tungsten atoms diffusing to the silicon substrate would enhance the probability of electron-hole-pair generation via impact ionization and form the localized current flowing. The phenomenon of localized conduction has been previously observed, e.g. in Na+-contaminated devices[31], clean oxides[32], and in devices with stacking faults in the underlying silicon substrate[33]. Thus, the localized field enhancement was therefore enhanced by the tungsten impurities so as to cause the breakdown of the gate oxide. In addition, the local stress induced by the diffusing tungsten was also one of the reasons to depress the dielectric strength of gate oxide. Tungsten diffusion also played a role in the degradation of electrical breakdown of the thin oxide annealed at lOOO”C, as shown in Fig. 3(c). At this temperature, the field strength dropped to a value below 8 MV/cm. A post-oxidation annealing temperature above -900°C tended to cause a drastic increase of the hole trapping in the oxide which in turn reduced the charge to breakdown[ 181.Hence, the increase of the hole trapping rate in the gate oxide was also considered as one of the degrading factors of the gate oxides annealed at lOOO”C[34].Of course, thermally induced stress and increased quantity of oxygen vacancies near the Si02/Si interface due to high-temperature annealing could not be ruled out for the deterioration of the gate annealed at lOOO”C[35]. In order to demonstrate that defects induced by phase transition, local stress, tungsten diffusion, and high-temperature hole trapping are the predominant factors in deteriorating the gate oxides in WSi,Y/Si02/ Si structures annealed at temperatures beyond 600°C the cumulative distributions of breakdown fields, namely Weibull plots, of oxides at different annealing temperatures, are shown in Fig. 5. The number of defects leading to a breakdown at or below a certain field strength E is given by D(E).A, where D(E) is the field-dependent defect density and A is the surface area of the capacitor. When the defects are distributed at random over the surface, the failure probability that defects in area A will induce a breakdown at or below a field E can be given by F(E) = 1 - exp[ - A .D(E)][l 11. The probability of finding defects in the area A is given by In[ln(l - F(E)))‘] or In[A .D(E)][36]. Hence the defect density D(E) at a certain field strength E can be found directly from the value of ln[ln( 1 - F(E))-‘] in the Weibull plot. Figure 5 shows the results of WSi.,/SiOz( 100 A)/Si gates annealed at the various
3
WSix/ SiO#OA)t
I
Si
I
C-4 5cdc
-31
1
6
0
1
8
*
fi
10
8
1
12
c
Field Strength (WI
1
14
e
1
16
c
I
18
cm)
Fig. 5. Weibull plots for WSi,JSiO,(lOOA)/Si specimens at various annealing temperatures.
temperatures. Since the cumulative distribution of 500°C annealed specimens was concentrated at a rather high value about 15 MV/cm and similar to that for 600°C annealing, it is suggested that these capacitors had the same defects which came from the intrinsic features of thermal oxide with 100 A in thickness[ 111.As for 700°C and 800°C anneahngs, the distribution were both scattered into three distinct regions of straight lines and had a steep gradient at 12 MV/cm. Because most of defect-related failures shown in the Weibull plots would disperse over a large range of field strength, there should be extra defects formed in specimens annealed at 700°C and 800°C. Based on the microstructural analysis, the phase transition from hexagonal to tetragonal WSi, for 700°C annealing would be accompanied by a large amount of defects which would cause a scattering cumulative distribution and a lower field strength than that in 500°C annealing. The induced stress on the gate oxide at this temperature could also generate defects to deteriorate the dielectric strength. Furthermore, the scattering distributions were still obtained for 900°C and 1000°C annealings. The diffusion of tungsten atoms to the interface between SiO, and Si substrate as well as the induced stress were used to demonstrate the drop of steep-gradient field to about 9 MV/cm for samples annealed at 900°C. In addition to the tungsten diffusion, factors such as the hole trapping generation, local stress, and large quantity of oxygen vacancies were also believed to degrade the thermal oxide to a concentrated field around 8 MV/cm for the specimens annealed at 1000°C. The curve in Fig. 6 illustrates the dependence of TZDB field on the annealing temperature for WSi,Y/poly-Si/SiO, (100 A)/Si gate structure. It was observed that the field strength almost maintained a constant level for annealing temperatures below lOOO”C, at which there was a sudden decrease of dielectric strength. Since there was a layer of
Tungsten silicides as gate electrodes
*”
--
WSixI pOly+i/Si0~(100~)1Si
I
t
050 Annealing
Temperature
Poly-Si/SiO*(lO&/Si
5 (lOO*C/div.)
I
I-
OL
7
371
*
’
I
6 Annealing
1
0
7 Temperature
1
6
*
1
9
n
I
10
(lOO*C/div.)
Fig. 6. Field strength of WSi,/poly-Si/SiO,(lOO A)/Si structure at different annealing temperatures.
Fig. 7. Dielectric strength of poly-Si/SiO,(lOO A)/Si samples annealed at different temperatures.
interposed polysilicon between the WSi, film and the oxide, the phase change of tungsten silicide and diffusion of tungsten atoms into gate oxide no longer directly affected the breakdown field of oxide. Fukumoto et al. [37] have indicated that the migration of MO atoms into the underlying polysilicon after 1000°C annealing would give large stress and yield mechanical damage-like microcracks or pinholes at the localized parts of the underlying gate oxide. To further understand the deterioration of gate oxide at 1000°C annealing, poly-Si/SiO,(lOO A)/% gate structure was studied. The function of field strength vs annealing temperature for poly-Si/SiO,( 100 A)/Si gate, as shown in Fig. 7, appeared to have the same trend as that for WB, /poly-Si/SiO, (100 A)/Si. In addition to the thermal stress and the hole trapping generation, the doping impurity in poly-Si was considered to be another factor in degrading the breakdown field of gate oxide for 1000°C annealing. Because the sheet resistances of n+ poly-Si in polySi/SiOr (100 A)/S’1 and WSi, /poly-Si/SiO, (100 A)/Si were 12 R/sq. and 20 R/sq. respectively, the concentrations of phosphorus in poly-Si with 4500 A in thickness were therefore about 6 x 10”/cm3 and 3.1 x 1020/cm3,accordingly[38]. When the specimens of poly-Si/SiO,( 100 A)/Si and WSi,/poly-Si/ SiO, (100 A)/Si were annealed, the phosphorus would diffuse into the SiO,[39,40]. With the diffusion coefficient reported by Thurston et a[.[411 the diffusing depths of one tenth of surface concentration estimated by 2&, where D was the diffusion coefficient of phosphorus in SiO, at the annealing temperature and f was the annealing time, were then equal to 5 17 A and 87 A respectively for 900°C and 1000°C annealings. Hence the phosphorus at the SiO,/Si interface of specimens annealed at 1000°C would have the concentration of about 10’9/cm3. Phosphorus diffusion is therefore assumed to enhance the impact ionization and to degrade the dielectric properties of the oxide with 100 A in thickness[42]. The higher content of phosphorus impurity resulted in a lower breakdown field for poly-Si/
SiO,(lOO A)/Si than for WSi,/poly-Si/Si02(100 A)/Si gate structure at 1000°C annealing, as shown in Figs 6 and 7. To recognize the feature of time-dependent dielectric breakdown (TDDB) of thin oxides in various gate structures, the time-to-breakdown at constant voltage was also measured for several annealing conditions. As a consequence, it was shown that all defects via phase transition, thermally induced stress, impurity diffusion, or high-temperature trapping generation, affected the time-dependent dielectric breakdown in a similar way to that for the rampingvoltage breakdown. Examples are shown in Figs 8(a) and (b). Figure 8(a) shows the TDDB result of WSi,/Si02( 100 A)/Si tested with a field fixed at 12 MV/cm. The time to breakdown in Fig. 8(a) appears to have a similar dependence on the annealing temperature, except for 500°C as compared with that of the field strength in Fig. 4. Figure 8(b) also shows that the trend of time-to-breakdown with the tested field of 14 MV/cm against the annealing temperature corresponds to that of field to breakdown vs the annealing temperature, as shown in Fig. 6, for WSi,/poly-Si/SiO,( 100 A)/%. The sheet resistivities of three gate structures were also measured to appraise their contact properties. The resistivities of both WSiX/SiOl/Si and WSi,/ poly-Si/SiO,/Si specimens annealed at the temperatures above 800°C decreased to values below 230pf2-cm, which was comparable with previous results[l,4,9]. The variations of the resistivities of tungsten silicides among these studies could be mainly attributed to the difference of deposition methods such as sputtering, electron-beam coevaporation and low pressure CVD. On the other hand, the sheet resistivity of poly-Si/SiO,/Si structure was still as high as about 630 @-cm even after 1000°C annealing. Hence as judged from the breakdown characteristics and the sheet resistivities, the gate structure of WSi,/poly-Si/SiO,/Si seemed to be superior to WSiJSiOJSi and poly-Si/SiO,/Si for the very thin gate oxide with 100 A in thickness[34].
H. C.
312
CHENG et al.
(a)
20 103
_
WSixl SiO2(1C&/Si Stressed Field 12 MVlcm
16-
Poly-SiISi02(27OA)/Si
- - - -
WSix/ Poly-S;/s;O2(27O~)/Si
-
4-
16’1 5
6
Annealing (b)
0 7
8
9
10
5
’
6
a
WSix/Poly-SilSiO2(1oO$ISi Stressed Field 14 MVlcm
annealing temperature has almost a constant
Annealing
Temperature
ClOO’C/div.)
Time to breakdown of (a) WSi,/SiO,(lOO~)/Si structure stressed with a constant field 12 MV/cm and (b) WSiJpoly-Si/SiO,(lOO A)/Si specimens tested with a constant field 14 MV/cm, as a function of annealing temperature. 8.
B. Efect
of oxide thickness on the TZDB field
qf gate oxide. Figure 9 shows the curves of TZDB
field vs annealing temperature for WSi,/SiOz/Si gate specimens with gate oxides of 270 and 540 A. As can be seen, the strength slowly decreases with increasing
_ 16-z 2
g ?i 0, p
1
1
a
1
9
0
10
for WSi,/SiO,(270 A)/Si and value at about 10 MV/cm for
WSi,/SiO,(%O A)/Si. This is predictable because thicker oxides have a higher tolerance of interfacial defects induced by phase transition, which occurs at the temperature between 600°C and 7OO”C, than thin oxides. In addition, thicker oxides have also the higher tolerance of induced local stress and tungsten diffusion into the interface between SiO, and Si substrate. The TZDB fields for WSi,/polySi/Si02 (270 A)/Si and poly-Si/SiO,(270 A)/Si after annealing are shown in Fig. 10. These graphs indicate an almost constant level. This is reasonable since the thicker oxides of 270 A in thickness lessen the impact of high-temperature phosphorus diffusion and local stress. Furthermore, Fig. 11 shows the results of TZDB tests of WSi,/polySi/SiO,(540 A)/Si and poly-Si/SiO, (540 A)/Si. These data once more support the explanation mentioned above. It was therefore concluded that the variation of field strengths corresponding to various annealing temperatures decreases as the thickness of gate oxide increases. -_
L”
2“,
3
10. Field strengths of WSiJpoly-Si/SiO,(270 A)/Si and poly-Si/SiO,(270 A)/Si structures annealed at different temperatures.
,oo
Fig.
1
7
Annealing Tempemture (lOO*Cldiv.)
(100% I div.)
Temperature
’
WS+o2(27O&/S;
-
Poly-si/Si02(5&d)/Si
WSix/S;q(5COA)/S;
----
W&l
16 t
----
Poly-sinio2(5&OA)/s;
-
_
12e-h&_ --B-
4-
0
5
’
1
6
a
1
7
1
1
0
a
1
9
1
Annealing Temperature (100% I div.)
fields of WSi,/SiO, (270 A)/Si Fig. 9. Breakdown and WSi,JSiO,(540 A)/Si structures annealed at various temperatures.
Oti 5
6
7
Annealing Temperature
a
9 (100% I d;v .)
Fig. 11. Breakdown fields of WSiJpoly-Si/SiO,(540 A)/Si and poly-Si/SiO, (540 A)/Si structures annealed at different temperarures.
Tungsten silicides as gate electrodes
373
4. CONCLUSIONS
10. P. Fazan, M. Dutoit, C. Martin and M. Ilegems,
The correlation between materials analysis and the electrical characteristics of the gate structures, namely WSi,/Si02 /Si, WSi, /poly-Si/SiO, /Si, and poly-Si/ SiO,/Si, have been studied. The phase transition from hexagonal to tetragonal WSil and the induced stress can be used to interpret the degradation of dielectric strength of WSi,r/SiO,(lOO A)/Si capacitors annealed at 700°C. Tungsten diffusion to the interface between SiO, and Si substrate, and the locally enhanced strain, result in the depression of breakdown field of WSi,/ SiO,( 100 A)/Si annealed at the temperatures above 900°C. The field to breakdown of WSi,/Si02( 100 A)/ Si annealed at 1000°C further decreases due to the drastic generation of hole traps. On the other hand, not only the hole traps generation and the thermally induced stress but also phosphorus diffusion to the interface between Si02 and Si substrate is harmful to the dielectric characteristics of gate oxides in the WSi,V/poly-Si/SiO,(lOO A)/Si and poly-Si/ SiO,(lOO A)/Si structures annealed at 1000°C. As judged from the results of dielectric properties and sheet resistivities, MOS capacitors of WSi,r/polySi/Si02/Si structure seem to be superior to those with WSi,Y/SiOz/Si and poly-Si/SiO,/Si for the very thin oxide with 100 A in thickness. Moreover, the variation of field strength corresponding to different annealing temperatures decreases with increasing thickness of gate oxide.
11. T. N. Nauven and D. L. Ouinlan. Proc. MRS Svmo. . . Vol. 71, ;.-505 (1986). 12. M. Naito, H. Homma and N. Momma, So/id-St.
Solid-St. Electron. 30, 829 (1987).
Acknowledgement-The
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13. M. M. Moslehi, S. C. Shatas, K. C. Saraswat and J. D. Meindl, IEEE Trans. Electron Devices ED-34, 1407 (1987). 14. J. Batey, E. Tiemey and T. N. Nguyen, IEEE Electron Device L&t. EDL-8, 148 (1987). 15. R. M. Bradley, J. appl. Phys. 61, 545 (1987). 16. D. Flowers, J. Electrochem. Sot. 134, 698 (1987). 17. T. B. Hook and T. P. Ma, J. appl. Phys. 62,931 (1987). 18. S. Holland and C. Hu, J. Electrochem. Sot. 133, 1705 (1985).
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21. W. T. Lin and L. J. Chen, J. appl. Phys. 59,348l (1986). 22. S. P. Murarka, M. H. Read and C. C. Chang, J. appl. Phys. 52, 7450 (1981). 23. F. K. LeGoues, F. M. d’Heurle, R. Joshi and I. Suni, Proc. MRS Symp. Vol. 54, p. 51 (1985). 24. S. Holland, I. C. Chen, T. P. Ma and C. Hu, IEEE Electron Deuice L&t. EDL-5, 302 (1984). 25. I. C. Chen, S. E. Holland and C. Hu, IEEE Trans. Electron Devices ED-32, 413 (1985). 26. Y. Nishioka, E. F. Dasilva and T. P. Ma, IEEE Electron Device Left. EDLS, 566 (1987). 27. T. B. Hook and T. P. Ma, Appl. Phys. L&t. 48, 1208 (1986). 28. R. F. Kwasnick, E. B. Kaminsky, P. A. Frank, G. A. Franz, E. J. Polasko, R. J. Saia and T. B. Gorczya, IEEE Trans. Electron Devices 35, 1432 (1988). 29. Y. Hokari. J. a& Phvs. 58. 3536 (19851. 30. M. Liehr, H. Dallaporta and J. E. -Lewis, Appl. Phys. Lett. 53, 589 (1988).
31. T. H. Distefano, J. appl. Phys. 44, 527 (1973). 32. C. M. Osbum and N. J. Chou, J. Electrochem. Sot. 120, 1377 (1973). 33. P. S. D. Lin, R. B. Marcus and T. T. Sheng, J. Electrochem. Sot. 130, 1878 (1983). 34. H. C. Cheng, C. Y. Chao, W. D. Su, S. W. Chang, M. K. Lee and C. Y. Wu, Proc. CSMS Symp. Proc. Kaoshiung, Taiwan, p. 25 (1988). 35. J. R. Schwank and D. M. Fleetwood, Appl. Phys. L&t. 53, 770 (1988).
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0038-I lOI/ 53.00+ 0.00 Copyright 0 1990 Pergamon Press plc
THE EFFECT OF GATE ELECTRODES USING TUNGSTEN SILICIDES AND/OR POLY-SILICON ON THE DIELECTRIC CHARACTERISTICS OF VERY THIN OXIDES H. C. CHENG’, C. Y. CHAO’,W. D. Su*, S. W. CHANG*, M. K. LEE* and C. Y. WV’ ‘Department of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan, Republic of China and *Electronics Research and Service Organization, Hsinchu, Taiwan, Republic of China (Received 12 May 1989; in revised form 31 August 1989) Abstract-The effects of gate electrodes made of tungsten silicides and/or polysilicon on the dielectric characteristics of very thin gate oxides have been studied. For a WSi,/SiO,(lOO A)/!5 gate structure, the phase transition from hexagonal to tetragonal WSi, and the induced stress demonstrated the degradation of dielectric strength of gate oxide annealed at 700°C. Tungsten diffusion to the interface between SiO, and Si substrate as well as the enhanced local strain caused the deterioration of breakdown fields for annealing temperatures above 900°C. Drastic generation of hole traps at 1OOOCannealing further diminished the field to breakdown of thin oxide. For WSi,/poly-Si/SiO,(lOO A)/Si and poly-Si/SiO,(lOfl A)/Si structures annealed at lOOo”C, phosphorus diffusion to the SiO,/Si interface was also harmful to the dielectric characteristics of gate oxides besides the high-temperature hole trap generation and the thermally induced stress. Hence, MOS capacitors of WSi,r/poly-Si/SiO,(lOO A)/Si structures seemed to be superior to the other two structures when the sheet resistivity factor was also considered. The effect of thickness of gate oxide on the dielectric properties of three gate structures was also investigated.
I. INTRODUCTION Due to advances device dimensions
in integrated circuit technology, are being scaled down and chip
sizes are currently increasing[l]. However, the speed advantages attained from the short-channel design of smaller components could be offset by the interconnect resistance at the gate leve1[2,3]. In addition, the higher complexity and the larger chip size also result in a sheet-resistance contribution to the RC time delay and power consumption. Polycrystalline silicon (poly-Si) which possesses the feature of ability to withstand high temperatures encountered during fabrication process and was conventionally used as the gate electrode in MOS devices, did not satisfy the requirements of very-large-scale-integrated circuits (VLSI) due to its high resistivity[4]. Hence, refractory metals such as molybdenum (MO) and tungsten (W) have been considered. They have not been widely used due mostly to the fact that they could not withstand the many chemical reagents used and the oxidizing ambients at high temperatures[S]. An alternative choice is to use either refractory metal silicides, such as TiSi,, TaSi,, WSi, and MoSi, or a double layer of the refractory metal silicides over poly-Si[1,6,7]. With the features of relatively low electrical resistivities, good protection against the chemicals and oxygen, oxidizable property, good reliability of contact with shallow junctions, and ability to define fine lines, these refractory metal silicides are quite promising as gate materials in VLSI technologies[ l&9]. On the other hand, it has been projected that dielectric thickness of an 1 Mbit DRAM in VLSI S.S.E. 33,LD*
circuits was about 100 A due to the miniaturization of MOSFETs[lO]. Various methods such as dry oxidation[ 11,121, wet oxidation[ 11,121, rapid thermal processing[ 131, and plasma-enhanced chemical vapor deposition (PECVD)[14], have been used to grow the very thin gate oxide. Generally these grown oxides with a thickness about 100 A exhibited the optimum breakdown fields ranged from 10 MV/cm to 16 MV/cm. It has also been proposed that defects near the Si02/Si interface tended to nucleate holes which enhanced the dielectric breakdown[lS]. In addition, Flowers[ 161pointed out that post annealing of polysilicon gates lead to “pile up” of doping species at the oxide/polysilicon interface and resulted in attendant yield loss and reliability problems in devices due to the defect generation in the gate oxide. Furthermore, gate-induced strain[l7] and hole trapping generation[l8] also affected the dielectric properties. Very careful evaluation of the applications of the silicides as the gate electrodes on the MOS devices should become more important as the thickness of gate oxide (SiO,) decreases with smaller device dimensions[5]. However, most of the previous reports concerning the effect of gate silicides on the electrical characteristics of gate oxides have concentrated on the relatively thick oxides, which had thicknesses ranging from 200 to 1800 A[2,5,6,9,19]. Hence it is necessary to investigate the effect of silicide gate electrodes on the electrical breakdown of the very thin oxide, with a thickness about 100 A, for practical applications of silicides in future submicrometer technologies. Although CVD WSi,v had the advantages of low resistivity, less contamination of oxygen, as well as 365
H. C.
366
(h?NG
good step coverage, and was becoming widely used, the fluorine included in the film was found to be harmful to the dielectric characteristics of gate oxide[ 191.Sputtering has therefore often been used to deposit the WSi, film as a gate material[rl]. In this work, we report the effects of gate electrodes with sputtered WS& on the dielectric breakdown of the gate oxide with various thicknesses. For comparison, work with poly-Si gate electrodes was also performed. 2. EXPERIMENTAL
DETAILS
15-25 R-cm, 4-in-diameter, (100) oriented P-type silicon wafers were used to fabricate the investigated MOS capacitors. After the HF dip cleaning, the wafers were oxidized at 920°C in dry O2 ambient to obtain the gate oxides with 100, 270 and 540A thickness, in-situ annealed at the same temperature for 30 min in N, ambient. One part of oxidized wafers were deposited with a layer of WSi, (x = 2.3) by a dc. Magnetron MRC 603 sputtering system. Alloy deposition was carried out in a chamber evacuated to lo-‘torr prior to backfilling with argon. The deposited thickness of the tungsten silicide was 2300 A. No substrate heating was used during the deposition. Consequently, the as-deposited film had a sheet resistance of 41 R/sq. Then, the MOS capacitors with 82 x 82 pm in area were plasma-etched by a DRIE plasma 100 system. These capacitors were classified as WSi,/SiOz/Si. The other part of the oxidized silicon wafers were deposited with a low-pressure chemical-vapor-deposited (LPCVD) polysilicon film of thickness about 4500 A and then doped by POCl, diffusion. After a drive-in process at 950°C in nitrogen ambient, these samples possessed two kinds of sheet resistance, i.e. 12 G/sq. and 20 R/sq. respectively. The samples with the former resistance were then patterned by the same etching procedure mentioned above and were classified as poly-Si/SiO,/Si. Those with the latter resistance were first deposited with a layer of tungsten-silicon mixture WSi, with the same conditions as those for WSi,/Si02/Si and then defined into the desired pattern by the two step plasma etching process. These specimens were therefore named as WSi,/poly-Si/SiO,/Si capacitors. To lower the sheet resistances of gate electrodes and investigate the electrical reliability of thin oxide after high-temperature processings, these three kinds of MOS capacitors were all then annealed in N2 ambient at temperatures ranged from 500°C to 1000°C. Nz gas was first purified by titanium getter before entering the annealing furnace. Electrical breakdown tests were performed by using a voltage ramp technique which involved ramping a stairwise voltage from 0 to 20 V on the capacitor and measuring the current across the device[20]. A breakdown event was detected by a sudden increase of the measured current (current snapback) and the voltage at the first snapback was recorded as break-
et
al.
down voltage Vbd. The time zero dielectric breakdown TZDB field EM was then estimated with the value of Vbddivided by the thickness of gate oxide. The linear ramping rate of stress voltage is 0.1 V/s. The gate electrode was negatively biased with respect to the P-type silicon substrate (gate injection) to avoid surface depletion and voltage loss in the silicon region, i.e. accumulation style. Measurements were performed with a HP 4145A semiconductor analyzer. A desk computer HP85 was also utilized to control this instrument. Constant-voltage-stressed currentvoltage measurements were used to confirm the breakdown characteristics. In addition, the sheet resistance (Rs) of WSi, silicides was also determined by a four point probe instrument for practical purposes in VLSI circuits. Microstructural examinations were used to explain the electrical characteristics of gate oxides with the WB, electrodes. Transmission electron microscopy was carried out with a JEOL200CX scanning transmission electron microscope operating at 200 kV. In order to investigate annealing effects on the gate oxides, Auger electron spectroscopy (AES) was also performed with a PerkinElmer PHI-590 Spectrometer. AES has been combined with an argon ion miller to provide the composition-depth profiles. 3. RESULTS AND DISCUSSION
3.1. Microstructures and composition-depth profiles Generally, tungsten silicide forms only in the WSi, phase as the thin film of tungsten reacts with the silicon substrate. Moreover, WSi, crystallizes in the hexagonal structure at low temperatures, the tetragonal phase at higher temperatures[l,21]. In order to understand the effect of the phase transition of WB, (x = 2.3) on the gate oxide, diffraction patterns of the specimens annealed at various temperatures for WSi,/SiO,/Si and WSi,/poly-Si/SiO,/Si gate structures were analyzed. The as-deposited WSi, film appeared to be near-amorphous. The hexagonal phase of WSi, was found exclusively at annealing temperatures 500°C and 600°C for both gate structures. Furthermore, the tetragonal WSi, formed at annealing temperatures above 600°C for these two structures. Dark-field micrographs were also taken to confirm this phase transition. The needle-like morphology of tungsten silicide for 500°C and 600°C annealings was observed. Examples are shown in Figs l(a) and 2(a) for WSi,/Si02/Si and WSi,/polySi/SiO*/Si, respectively. At annealing temperatures above 7OO’C, the silicide grains became rounded in shape and increased in average sizes from 300 to 1200 A, as shown in Figs l(b)-(c) and Figs 2(b)-(c) for WSi,/SiO,/Si and WSi,r/poly-Si/SiO,/Si, accordingly. The morphology transition from needle-like to rounded shape corresponds to the phase transition from hexagonal to tetragonal phase deduced from the diffraction analysis. This is consistent with the
Tungsten silicides as gate electrodes
361
Fig. 1. Dark-field (DF) micrographs of WSi,~iO,(lOO A)/% specimens annealed at (a) SOO”C,(b) 700°C
and (c) lOOO”C,respectively, insets corresponding diffraction patterns (DPs). previous report[l]. As compared with the published result[ 11, the delayed transition of tetragonal WSiz at slightly higher temperature and larger average grain size in this study could be ascribed to the difference of the deposition methods, i.e. sputtering in this work and LPCVD in the previous study. Hence, it is reasonable to say that the transition temperature from hexagonal to tetragonal WSi, is at the annealing temperature between 600°C and 700°C. Due to this
transition, the densities of defects such as stacking faults and dislocations etc. abruptly increased for the silicide structures annealed at this temperature[22,23]. This would seriously degrade the electrical characteristics of gate oxides in WSi,/SiO,/Si capacitors, which would be discussed in the Section 3.2. Figures 3(aHc) shows the AES depth profiles of WSi,/SiOz (100 A)/Si samples annealed at 7OO”C, 900°C and lOOO”C, respectively. The value (100 A)
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Fig. 2. DF micrographs of WSi,/poly-Si/SiO,(lOO &/Si samples annealed at (a) XMYC, (b) 700°C and (c) lOOO”C,accordingly, insets corresponding DPs. marked
after
the SiO, represents
the thickness
of
gate oxide. As can be seen, tungsten diffused into oxide at annealing temperatures above 700°C but did not arrive over the interface between oxide and Si substrate until 900°C. However, this phenomenon was not evident for the WSi,/poly-Si/SiO,(lOO A)/Si specimens even annealed at 1000°C. It is therefore conjectured that the dielectric properties of SiO, in WSi,/Si02(100 A)/Si should be affected by the
tungsten annealed
diffusion after these capacitors at temperatures above 900°C.
3.2. Electrical characteristics difSent gate structures
were
of thermal oxides with
In this section, we report the electrical properties of gate oxide with 100 A in thickness. The effect of oxide thickness on the TZDB field of gate oxide is then discussed.
Tungsten silicides as gate electrodes wsip, I SiO2(1ooA)/
--
Si
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WSi~/SiO2(t&)r
Si
I
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60-
01 5
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s 801
/
” Si
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Time (min 1
WS&/Si~(lOOf~lSi 1000%
1
1
1
7
1
a
1
1
9
1
I
10
(100% I div.)
Fig. 4. Dielectric strength of WSi,/SiO,(lOO A)/Si structure as a function of annealing temperature.
60-
E
1
6
Annealing Temperature
12
Sputtering lime (min 1
Sputtering
1
1
-
Sputtering Time (min 1
Fig. 3. Auger depth profiles of WSi,/SiO,(lOO A)/.%samples annealed at (a) 7oo”C, (b) 9oo”C, (c) lOOO”C,respectively.
A. The electrical characteristics of gate oxide with lOOA in thickness. The curve of TZDB field strength vs annealing temperature for WSi,/SiO,/Si gate structure is shown in Fig. 4. The peak value of field strength, 1S- 16 MV/cm, occurs at annealing temperature about 600°C. Then the field has a sudden decrease at 700°C and exhibits a small variation at the temperature between 700°C and 800°C. For the
samples annealed at and above 9OOC, large drop of the strength was observed. Any improvement of the breakdown characteristics of gate oxides would require an improvement of the interface between SiO, and Si substrate [24]. This implies that the defects at the interface between poly-Si and SiO, degrade the quality of the gate oxide[25]. It is therefore surmised that the defects accompanying the phase transition from hexagonal to tetragonal WSir at annealing temperature between 600°C and 700°C play an important role in the deterioration of the breakdown field of the gate oxide. It has been reported[26] that the interface traps in metal/SiO,/Si capacitors depended on the initial damage level, the gate-induced stress, and the presence of certain chemical impurities or bonding defects in the gate oxide. Strain is induced in the silicon-dioxide by the difference between the thermal expansion coefficients of the gate electrodes and the silicon-dioxide[ 171. The strained bonds may be more readily broken by ionizing radiation or high-field electrical injection than unstrained bonds[27]. Therefore, both the generated defects at the electrode_SiO, interface and the induced stress in the SiOr enhance the formation of interface traps or trapped charges which cause the degradation of the dielectric film. As the annealing temperature rises to 9OO”C, the field strength of gate oxide rapidly falls. This could be interpreted by tungsten diffusion over the interface between SiOr and Si substrate, as shown in Fig. 3(b). It has been reported that increased substrate heating temperature during molybdenum sputter deposition could affect the gate oxide quality by increasing MO atom penetration into the oxide[28]. Hokari et a1.[29] also showed that the inferior reliability in a MOS capacitor with a metal sintering anneal was caused by aluminum precipitates at the poly-Si/SiO, interface. Transition metal particles such as tungsten were even indicated to enhance the creation of electrical defects in gate oxide layer[30]. Moreover, a dielectric-breakdown model had been established by Hu et a1.[24,25] who suggested that the dielectric breakdown process could be
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divided into two stages. The “early” breakdowns were caused by the “weak oxide area” which was weak because of a particularly high density of hole traps or large hole capture cross section at the local spot, or because of thinner oxide thickness, or lower effective barrier at time zero due to particulate contamination, crystalline defects or interface asperities in the silicon[25]. Hence, it is conjectured that the tungsten atoms diffusing to the silicon substrate would enhance the probability of electron-hole-pair generation via impact ionization and form the localized current flowing. The phenomenon of localized conduction has been previously observed, e.g. in Na+-contaminated devices[31], clean oxides[32], and in devices with stacking faults in the underlying silicon substrate[33]. Thus, the localized field enhancement was therefore enhanced by the tungsten impurities so as to cause the breakdown of the gate oxide. In addition, the local stress induced by the diffusing tungsten was also one of the reasons to depress the dielectric strength of gate oxide. Tungsten diffusion also played a role in the degradation of electrical breakdown of the thin oxide annealed at lOOO”C, as shown in Fig. 3(c). At this temperature, the field strength dropped to a value below 8 MV/cm. A post-oxidation annealing temperature above -900°C tended to cause a drastic increase of the hole trapping in the oxide which in turn reduced the charge to breakdown[ 181.Hence, the increase of the hole trapping rate in the gate oxide was also considered as one of the degrading factors of the gate oxides annealed at lOOO”C[34].Of course, thermally induced stress and increased quantity of oxygen vacancies near the Si02/Si interface due to high-temperature annealing could not be ruled out for the deterioration of the gate annealed at lOOO”C[35]. In order to demonstrate that defects induced by phase transition, local stress, tungsten diffusion, and high-temperature hole trapping are the predominant factors in deteriorating the gate oxides in WSi,Y/Si02/ Si structures annealed at temperatures beyond 600°C the cumulative distributions of breakdown fields, namely Weibull plots, of oxides at different annealing temperatures, are shown in Fig. 5. The number of defects leading to a breakdown at or below a certain field strength E is given by D(E).A, where D(E) is the field-dependent defect density and A is the surface area of the capacitor. When the defects are distributed at random over the surface, the failure probability that defects in area A will induce a breakdown at or below a field E can be given by F(E) = 1 - exp[ - A .D(E)][l 11. The probability of finding defects in the area A is given by In[ln(l - F(E)))‘] or In[A .D(E)][36]. Hence the defect density D(E) at a certain field strength E can be found directly from the value of ln[ln( 1 - F(E))-‘] in the Weibull plot. Figure 5 shows the results of WSi.,/SiOz( 100 A)/Si gates annealed at the various
3
WSix/ SiO#OA)t
I
Si
I
C-4 5cdc
-31
1
6
0
1
8
*
fi
10
8
1
12
c
Field Strength (WI
1
14
e
1
16
c
I
18
cm)
Fig. 5. Weibull plots for WSi,JSiO,(lOOA)/Si specimens at various annealing temperatures.
temperatures. Since the cumulative distribution of 500°C annealed specimens was concentrated at a rather high value about 15 MV/cm and similar to that for 600°C annealing, it is suggested that these capacitors had the same defects which came from the intrinsic features of thermal oxide with 100 A in thickness[ 111.As for 700°C and 800°C anneahngs, the distribution were both scattered into three distinct regions of straight lines and had a steep gradient at 12 MV/cm. Because most of defect-related failures shown in the Weibull plots would disperse over a large range of field strength, there should be extra defects formed in specimens annealed at 700°C and 800°C. Based on the microstructural analysis, the phase transition from hexagonal to tetragonal WSi, for 700°C annealing would be accompanied by a large amount of defects which would cause a scattering cumulative distribution and a lower field strength than that in 500°C annealing. The induced stress on the gate oxide at this temperature could also generate defects to deteriorate the dielectric strength. Furthermore, the scattering distributions were still obtained for 900°C and 1000°C annealings. The diffusion of tungsten atoms to the interface between SiO, and Si substrate as well as the induced stress were used to demonstrate the drop of steep-gradient field to about 9 MV/cm for samples annealed at 900°C. In addition to the tungsten diffusion, factors such as the hole trapping generation, local stress, and large quantity of oxygen vacancies were also believed to degrade the thermal oxide to a concentrated field around 8 MV/cm for the specimens annealed at 1000°C. The curve in Fig. 6 illustrates the dependence of TZDB field on the annealing temperature for WSi,Y/poly-Si/SiO, (100 A)/Si gate structure. It was observed that the field strength almost maintained a constant level for annealing temperatures below lOOO”C, at which there was a sudden decrease of dielectric strength. Since there was a layer of
Tungsten silicides as gate electrodes
*”
--
WSixI pOly+i/Si0~(100~)1Si
I
t
050 Annealing
Temperature
Poly-Si/SiO*(lO&/Si
5 (lOO*C/div.)
I
I-
OL
7
371
*
’
I
6 Annealing
1
0
7 Temperature
1
6
*
1
9
n
I
10
(lOO*C/div.)
Fig. 6. Field strength of WSi,/poly-Si/SiO,(lOO A)/Si structure at different annealing temperatures.
Fig. 7. Dielectric strength of poly-Si/SiO,(lOO A)/Si samples annealed at different temperatures.
interposed polysilicon between the WSi, film and the oxide, the phase change of tungsten silicide and diffusion of tungsten atoms into gate oxide no longer directly affected the breakdown field of oxide. Fukumoto et al. [37] have indicated that the migration of MO atoms into the underlying polysilicon after 1000°C annealing would give large stress and yield mechanical damage-like microcracks or pinholes at the localized parts of the underlying gate oxide. To further understand the deterioration of gate oxide at 1000°C annealing, poly-Si/SiO,(lOO A)/% gate structure was studied. The function of field strength vs annealing temperature for poly-Si/SiO,( 100 A)/Si gate, as shown in Fig. 7, appeared to have the same trend as that for WB, /poly-Si/SiO, (100 A)/Si. In addition to the thermal stress and the hole trapping generation, the doping impurity in poly-Si was considered to be another factor in degrading the breakdown field of gate oxide for 1000°C annealing. Because the sheet resistances of n+ poly-Si in polySi/SiOr (100 A)/S’1 and WSi, /poly-Si/SiO, (100 A)/Si were 12 R/sq. and 20 R/sq. respectively, the concentrations of phosphorus in poly-Si with 4500 A in thickness were therefore about 6 x 10”/cm3 and 3.1 x 1020/cm3,accordingly[38]. When the specimens of poly-Si/SiO,( 100 A)/Si and WSi,/poly-Si/ SiO, (100 A)/Si were annealed, the phosphorus would diffuse into the SiO,[39,40]. With the diffusion coefficient reported by Thurston et a[.[411 the diffusing depths of one tenth of surface concentration estimated by 2&, where D was the diffusion coefficient of phosphorus in SiO, at the annealing temperature and f was the annealing time, were then equal to 5 17 A and 87 A respectively for 900°C and 1000°C annealings. Hence the phosphorus at the SiO,/Si interface of specimens annealed at 1000°C would have the concentration of about 10’9/cm3. Phosphorus diffusion is therefore assumed to enhance the impact ionization and to degrade the dielectric properties of the oxide with 100 A in thickness[42]. The higher content of phosphorus impurity resulted in a lower breakdown field for poly-Si/
SiO,(lOO A)/Si than for WSi,/poly-Si/Si02(100 A)/Si gate structure at 1000°C annealing, as shown in Figs 6 and 7. To recognize the feature of time-dependent dielectric breakdown (TDDB) of thin oxides in various gate structures, the time-to-breakdown at constant voltage was also measured for several annealing conditions. As a consequence, it was shown that all defects via phase transition, thermally induced stress, impurity diffusion, or high-temperature trapping generation, affected the time-dependent dielectric breakdown in a similar way to that for the rampingvoltage breakdown. Examples are shown in Figs 8(a) and (b). Figure 8(a) shows the TDDB result of WSi,/Si02( 100 A)/Si tested with a field fixed at 12 MV/cm. The time to breakdown in Fig. 8(a) appears to have a similar dependence on the annealing temperature, except for 500°C as compared with that of the field strength in Fig. 4. Figure 8(b) also shows that the trend of time-to-breakdown with the tested field of 14 MV/cm against the annealing temperature corresponds to that of field to breakdown vs the annealing temperature, as shown in Fig. 6, for WSi,/poly-Si/SiO,( 100 A)/%. The sheet resistivities of three gate structures were also measured to appraise their contact properties. The resistivities of both WSiX/SiOl/Si and WSi,/ poly-Si/SiO,/Si specimens annealed at the temperatures above 800°C decreased to values below 230pf2-cm, which was comparable with previous results[l,4,9]. The variations of the resistivities of tungsten silicides among these studies could be mainly attributed to the difference of deposition methods such as sputtering, electron-beam coevaporation and low pressure CVD. On the other hand, the sheet resistivity of poly-Si/SiO,/Si structure was still as high as about 630 @-cm even after 1000°C annealing. Hence as judged from the breakdown characteristics and the sheet resistivities, the gate structure of WSi,/poly-Si/SiO,/Si seemed to be superior to WSiJSiOJSi and poly-Si/SiO,/Si for the very thin gate oxide with 100 A in thickness[34].
H. C.
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(a)
20 103
_
WSixl SiO2(1C&/Si Stressed Field 12 MVlcm
16-
Poly-SiISi02(27OA)/Si
- - - -
WSix/ Poly-S;/s;O2(27O~)/Si
-
4-
16’1 5
6
Annealing (b)
0 7
8
9
10
5
’
6
a
WSix/Poly-SilSiO2(1oO$ISi Stressed Field 14 MVlcm
annealing temperature has almost a constant
Annealing
Temperature
ClOO’C/div.)
Time to breakdown of (a) WSi,/SiO,(lOO~)/Si structure stressed with a constant field 12 MV/cm and (b) WSiJpoly-Si/SiO,(lOO A)/Si specimens tested with a constant field 14 MV/cm, as a function of annealing temperature. 8.
B. Efect
of oxide thickness on the TZDB field
qf gate oxide. Figure 9 shows the curves of TZDB
field vs annealing temperature for WSi,/SiOz/Si gate specimens with gate oxides of 270 and 540 A. As can be seen, the strength slowly decreases with increasing
_ 16-z 2
g ?i 0, p
1
1
a
1
9
0
10
for WSi,/SiO,(270 A)/Si and value at about 10 MV/cm for
WSi,/SiO,(%O A)/Si. This is predictable because thicker oxides have a higher tolerance of interfacial defects induced by phase transition, which occurs at the temperature between 600°C and 7OO”C, than thin oxides. In addition, thicker oxides have also the higher tolerance of induced local stress and tungsten diffusion into the interface between SiO, and Si substrate. The TZDB fields for WSi,/polySi/Si02 (270 A)/Si and poly-Si/SiO,(270 A)/Si after annealing are shown in Fig. 10. These graphs indicate an almost constant level. This is reasonable since the thicker oxides of 270 A in thickness lessen the impact of high-temperature phosphorus diffusion and local stress. Furthermore, Fig. 11 shows the results of TZDB tests of WSi,/polySi/SiO,(540 A)/Si and poly-Si/SiO, (540 A)/Si. These data once more support the explanation mentioned above. It was therefore concluded that the variation of field strengths corresponding to various annealing temperatures decreases as the thickness of gate oxide increases. -_
L”
2“,
3
10. Field strengths of WSiJpoly-Si/SiO,(270 A)/Si and poly-Si/SiO,(270 A)/Si structures annealed at different temperatures.
,oo
Fig.
1
7
Annealing Tempemture (lOO*Cldiv.)
(100% I div.)
Temperature
’
WS+o2(27O&/S;
-
Poly-si/Si02(5&d)/Si
WSix/S;q(5COA)/S;
----
W&l
16 t
----
Poly-sinio2(5&OA)/s;
-
_
12e-h&_ --B-
4-
0
5
’
1
6
a
1
7
1
1
0
a
1
9
1
Annealing Temperature (100% I div.)
fields of WSi,/SiO, (270 A)/Si Fig. 9. Breakdown and WSi,JSiO,(540 A)/Si structures annealed at various temperatures.
Oti 5
6
7
Annealing Temperature
a
9 (100% I d;v .)
Fig. 11. Breakdown fields of WSiJpoly-Si/SiO,(540 A)/Si and poly-Si/SiO, (540 A)/Si structures annealed at different temperarures.
Tungsten silicides as gate electrodes
373
4. CONCLUSIONS
10. P. Fazan, M. Dutoit, C. Martin and M. Ilegems,
The correlation between materials analysis and the electrical characteristics of the gate structures, namely WSi,/Si02 /Si, WSi, /poly-Si/SiO, /Si, and poly-Si/ SiO,/Si, have been studied. The phase transition from hexagonal to tetragonal WSil and the induced stress can be used to interpret the degradation of dielectric strength of WSi,r/SiO,(lOO A)/Si capacitors annealed at 700°C. Tungsten diffusion to the interface between SiO, and Si substrate, and the locally enhanced strain, result in the depression of breakdown field of WSi,/ SiO,( 100 A)/Si annealed at the temperatures above 900°C. The field to breakdown of WSi,/Si02( 100 A)/ Si annealed at 1000°C further decreases due to the drastic generation of hole traps. On the other hand, not only the hole traps generation and the thermally induced stress but also phosphorus diffusion to the interface between Si02 and Si substrate is harmful to the dielectric characteristics of gate oxides in the WSi,V/poly-Si/SiO,(lOO A)/Si and poly-Si/ SiO,(lOO A)/Si structures annealed at 1000°C. As judged from the results of dielectric properties and sheet resistivities, MOS capacitors of WSi,r/polySi/Si02/Si structure seem to be superior to those with WSi,Y/SiOz/Si and poly-Si/SiO,/Si for the very thin oxide with 100 A in thickness. Moreover, the variation of field strength corresponding to different annealing temperatures decreases with increasing thickness of gate oxide.
11. T. N. Nauven and D. L. Ouinlan. Proc. MRS Svmo. . . Vol. 71, ;.-505 (1986). 12. M. Naito, H. Homma and N. Momma, So/id-St.
Solid-St. Electron. 30, 829 (1987).
Acknowledgement-The
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