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Reconfigurable logic blocks based on a chaotic Chua circuit
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Chaos, Solitons and Fractals 41 (2009) 233–244 www.elsevier.com/locate/chaos
Reconfigurable logic blocks based on a chaotic Chua circuit Hamid Reza Pourshaghaghi a,b, Behnam Kia a, William Ditto c,d,*, Mohammad Reza Jahed-Motlagh a,b a
Chaos Computing Lab, Department of Computer Engineering, Iran University of Science and Technology, Tehran, Iran b Department of Electrical Engineering, Iran University of Science and Technology, Tehran, Iran c J. Crayton Pruitt Family Department of Biomedical Engineering, University of Florida, Gainesville, FL 32611-6131, USA d ChaoLogix Inc., 101 SE 2nd Place, Suite 201-B, Gainesville, FL 32601, USA Accepted 27 November 2007
Abstract To investigate morphable chaotic logic we have constructed, out of discrete circuitry, a chaotic logic block that can morph between all two input, one output logic gates. Additionally, we investigate the sensitivity of such a block to noise and have been able to formulate a method that demonstrates that the chaotic saddles of the inherent chaotic dynamics can be exploited to enhance the robustness of the logic functions with respect to noise. Ó 2007 Elsevier Ltd. All rights reserved.
1. Introduction Recently there have been breakthroughs in the exploitation of chaotic dynamics to perform calculations through morphing chaotic logic gates [1–3]. The next steps in the evolution of mature chaotic computing systems involve demonstrating that morphing chaotic logic elements can be combined into chaotic logic blocks to perform higher level functions. Towards this end several efforts have shown promising results. In [4] an analog continuous time chaotic Chua circuit based logic block was introduced which constructs a single NOR gate. In [5] a single NOR gate was constructed in a discrete time chaotic map. Additionally, it has been shown [6] that fundamental logic gates, consisting of AND, OR, XOR and NOT gates can be constructed by a single morphing chaotic circuit. In [7] construction of sequential gates based on chaotic circuits was studied, and a Chua circuit based SR flip-flop was presented. The next real challenge in the construction of chaos based morphing computer architectures lies in how to interconnect logic blocks to perform higher order functions [8]. It also has been problematic to construct robust analog chaotic circuits that can demonstrate reliable computation either at the logic or higher order levels. The purpose of this work is to demonstrate that we can build stable chaotic logic blocks and higher order functions from analog chaotic circuits. In [3] the theoretical background for direct construction of all digital functions from a single chaotic element was introduced. Based on [3], in this paper, we construct a robust discrete analog circuit that can be reconfigured to work as all two input, one output combinational logic gates. One important challenge for the construction of practical chaos * Corresponding author. Address: J. Crayton Pruitt Family Department of Biomedical Engineering, University of Florida, Gainesville, FL 32611-6131, USA. E-mail address: [email protected]fl.edu (W. Ditto).
0960-0779/$ - see front matter Ó 2007 Elsevier Ltd. All rights reserved. doi:10.1016/j.chaos.2007.11.030
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based reconfigurable logic blocks deals with the stability of instruction set of such logic block in the presence of environmental noise. In this paper, we utilize chaotic saddles to improve the robustness of the constructed chaotic logic block, in the presence of noise. We demonstrate that by restricting the operation of chaotic logic gates to the chaotic saddles within the chaotic attractor the instruction set of the logic block, remains robust and fixed in front of environmental noise. In this paper, a Chua circuit is chosen as continuous time analog chaotic circuit in implementation of logic block, because it is a well-characterized chaotic circuit for the evaluation of chaos based applications. The flow of this paper is as follows: In part 2 theoretical background for chaotic computing is introduced, in part 3 the experimental realization of a morphing logic block is presented. The paper is concluded in part 4.
2. Theoretical background for chaotic computing Chaotic systems are rich sources of behaviors and dynamics, which can be recruited in different branches of informatics. Recently the possibility of emulation and construction of reconfigurable logic blocks from chaotic systems have been introduced [1–6]. In [3] it was demonstrated that every logic gate could be constructed from a single chaotic system. The main idea is to harness the library of the many orbits/patterns inherent in chaotic systems to select out logic operations and to utilize the sensitivity to initial conditions (or unpredictability) of such systems to perform rapid switching (morphing) between all logic functions. These features provide us with all that we need to create reconfigurable logic blocks out of analog circuits. By applying special encoding methods, or equally restricting the dynamics of the chaotic systems to a robust chaotic saddle embedded in the chaotic attractor of the system, the symbolic itineraries of the orbits remain stable and robust in the presence of noise and fluctuations. This robustness to environmental noise means that, although the system is chaotic, the type of constructed gate remains stable. In this part, in Section 2.1 the chaotic computing model is introduced, in Section 2.2 we demonstrate how can unpredictability of chaotic computing engine, result in universality of chaotic logic block in computation, and in Section 2.3 we describe how can this logic block be made robust to noise. 2.1. Chaos based flexible computing model Chaos based computation consists of a chaotic system (continuous or discrete) as the computing engine and two translation maps, which bridge between the chaotic computing engine, the inputs and the outputs [3]. In this model, chaotic system provides us with the unpredictability, which based on Shannon’s information theory point of view, is a rich source of information [9]. The first (forward) translation map, translates the inputs to the points in state space of the chaotic computing engine, to be processed by the chaotic computing engine, and the second (backward) translation map, translates the final state of the chaotic computing engine to the outputs. To be more precise, let the m digital data inputs to the computing model are X 1data ; X 2data ; . . . ; X mdata and the n digital control inputs are X 1control ; X 2control ; . . . ; X ncontrol . A schematic of this approach is shown in Fig. 1. The computing operation of the system consists of three steps: Step 1: Each set of data and control inputs is mapped to a point on the unstable manifold of the chaotic system. This point, in the next step of the computing operation of the logic block will be used as the initial condition of the chaotic systems. Let T be the forward translation map, L the set, consisting of the all possible values of a digital
Data input : 1 2 m X data , X data , ... , X data
Forward translation map
Initial Condition of Chaotic System
Chaotic system as computing engine
Final State of Chaotic System
Backward translation map
output
Control input : 1 2 n X control , X control , ... , X control
Fig. 1. Schematics of chaotic computing model. Inputs are mapped to an initial condition of chaotic system working as computing engine, and the final state of the chaotic system is decoded to output through backward translation map.
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binary variable, {0, 1}, then L(n+m) represents the domain of T which consists of all possible combinations of digital data and control inputs, b, be the unstable manifold of the chaotic system, Rs the general state space of the chaotic system, and Y be the output of forward translation map on the unstable manifold. In this case the general form of forward translation map,T, is as follows: T : LðmþnÞ ! b; Y ¼
b Rs ; L ¼ f0; 1g
T ðX 1control ; X 2control ; . . . ; X ncontrol ; X 1data ; X 2data ; . . . ; X mdata Þ
ð1Þ ð2Þ
Based on this definition, the forward translation map can be any map, working between inputs and the unstable manifold of the chaotic system. In this section we will introduce another constraint for the forward translation map, regarding the distance between the consecutive images of forward translation map on unstable manifold, which should be considered during choosing the appropriate forward translation map. In practice we should choose the simplest forward translation map for implementation that follows the constraints. Step 2: Under the initial conditions produced by forward translation map, the chaotic system evolves for a fixed time (for a fixed iteration number, if the chaotic system is discrete). This evolution time should be chosen so that orbits starting from nearby initial conditions produced by forward translation of the map statistically uncorrelated. This is the new constraint on forward translation map, which describes that the distance between images of the map should be wide enough so that after the evolution time they get uncorrelated. Step 3: After the evolution time, the system stops working and its state at the end of evolution time is sampled. This final state is decoded to the outputs through the backward translation map. In decoding the final state of the system to a symbol as output of computation, symbolic dynamics can be utilized which consists of partitioning state space of the system, and assigning a symbol to each partition. In our computing algorithm the number of these partitions should be equal to the number of possible outputs of computation and the symbols of these partitions are the possible outputs of the computation. For example in building two input one output logic gates, state space of chaotic system should be divided to two parts and the symbols of these partitions should be 0 and 1. The output of the computation is the symbol of partition that final state of the chaotic system (computing engine) settles upon. At the end, notice the aim of this model is to utilize unpredictability of chaotic systems in flexible computations. Toward this aim, forward translation map, maps digital data and control inputs to the points on the unstable manifold of the chaotic system, and these points evolve under chaotic dynamics of the system. So by changing just one bit of control inputs, the orbits starting from initial conditions produced by forward translation map change considerably, resulting in emulation of a different digital function. So this model, recruits unpredictability of chaotic systems in flexible computations. 2.2. How can unpredictability of chaotic computing engines result in universality of logic block in computation? The aim of chaotic computing approach is to transform the unpredictability of a chaotic system working as the computing engine, to provide the mechanism for reconfiguring the logic block. The purpose of this part is to quantitatively demonstrate how and why the chaotic computing approach is computationally universal. Orbits of chaotic systems are sensitive to initial conditions. The forward translation map, maps different sets of the inputs to different points on unstable manifold of chaotic system and these points are used as initial conditions of chaotic system. Thus the orbits of chaotic system are very sensitive to the bits of inputs and they dramatically change, when there is just a change in one bit of the control input. Thus controlling inputs can be used to reconfigure a chaotic logic block. To evaluate which digital function is emulated with a control input, one can simply assign this control input to the logic block and give all combinations of data inputs to the logic block and observe the output to construct the truth table of the constructed function. With a high probability, by changing the control input and repeating this procedure (of constructing the truth table of digital function) one may obtain another digital function different from the first one. This is the meaning of the flexibility, or equivalently reconfigurability, of chaotic logic block in computations. The remaining questions are: (1) how flexible is this computation model? and (2) is this model computationally universal? To answer these questions we apply statistics and probability theory to chaotic computation. Without loss of the generality, let the goal be the emulation of m-input, 1-output combinational digital functions. At first we hold the controlling inputs fixed. Based on the statistical uncorrelation of orbits produced by the chaotic systems the process of assigning each set of data inputs and observing the output is a seemingly random experiment from the view of external observer. Notice that the initial conditions produced by forward translation map are situated on unstable manifold of the chaotic system, thus by evolution of the system they are strongly uncorrelated. Hence an external observer, when provided
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Table 1 Probabilities of random variable Random variable Probability
1 P
0 q=1p
different inputs to system, observes completely different and uncorrelated outputs from the system. Loosely speaking, the external observer finds the outputs random. In fact this process is a Bernoulli experiment [10] where the output has two possible conditions, 0 or 1. Let Z be random variable of Bernoulli distribution (Z Ber(p)). The probabilities of this random variable are shown in Table 1 [3]. The process of assigning different possible combinations of data inputs (still with a fixed control input) and observing the binary outputs is a Binomial experiment [10]. The reason is again uncorrelation of orbits (iterates) of the system under the chaotic dynamics of the system. The random variable of this experiment is V Bin(2m,p) where p is the probability of success of an individual Bernoulli experiment and 2m shows that the Binomial experiment consists of 2m Bernoulli experiments. We define the sample space of this Binomial experiment as follows: S B ¼ fa1 a2 . . . a2m jaj 2 f0; 1gg
ð3Þ
where aj is the output of jth Bernoulli experiment. In fact each sample of this space is a truth table of one m-input, 1output digital function. Each Binomial experiment takes one of these samples as result and it means that the chaosbased model emulate this function with the used control input. The probability of obtaining a desired function, e.g. a01 a02 . . . a02m by this Binomial experiment is: P Binomial ða01 a02 . . . a02m Þ ¼ P Bernoulli ða01 Þ P Bernoulli ða02m Þ
ð4Þ
This probability function can be simplified to the following: P Binomial ða01 a02 . . . a02m Þ ¼ ps qr ¼ ps ð1 pÞr
ð5Þ
where p and q are the probabilities of observing ‘‘1” and ‘‘0” as the outputs of Bernoulli experiment, respectively, ‘‘s” and ‘‘r” are the number of ‘‘1”s and ‘‘0”s in the desired sample of space (representing desired function), respectively. Based on Eq. (5) the computation model will be biased to simulate functions with more ‘‘1”s (‘‘0”s) in their outputs if 0.5 < p (0.5 < q). To obtain a generic (or fair in the sense of statistical fairness) computational model one must have p ¼ q ¼ 12 [3]. This is a new constraint the designer should follow it during implementation. Based on this fact, to have a flexible computing system, we fix the value of p and q to 0.5. As a result the probability function of obtaining desired function by Binomial experiment becomes: P Binomial ða01 a02 . . . a02m Þ ¼ ð0:5Þ2
m
ð6Þ
Thus the probability of obtaining the desired function is very low and one should repeat the Binomial experiment to obtain the desired function. One can repeat this Binomial experiment by changing the control inputs. Such binomial experiments are Bernoulli experiment again because they have two possible conditions, succeeding in simulation of desired function or failure in it. The probabilities of random variable of new Bernoulli experiment are shown in Table 2. Repeating the new Bernoulli experiment constructs a new Binomial experiment. Notice again that these new Bernoulli experiments are themselves independent because of the lack of correlation between orbits. The random variable m of new Binomial experiment is B Binðf ; ð0; 5Þ2 ). Now the question is about the value of f, where one can obtain the desired function by this iteration of Bernoulli experiment. This probability can be obtained based on the following equation: P Bin ðObserving desired function by f iterationsÞ ¼ 1 pBin ðno observation in f iterationÞ m
¼ 1 ð1 ð0:5Þ2 Þf
ð7Þ
An interesting feature of this probability function is that it is approximately independent of m and is just a function of f m m m [3]. With f ¼ 22 , this probability function becomes about 0.6, with f ¼ 22 þ2 it becomes about 0.98, by f ¼ 22 þ3 it m m becomes 0.9997 and by f ¼ 22 þ4 it becomes 1 when calculating in double precision. Notice that there are 22 different Table 2 Probabilities of random variable Outcome Probability
Success in emulation (1) m ð0:5Þ2
Failure inm emulation (0) 1 ð0:5Þ2
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m-input, 1-output digital functions and hence to determine all of them uniquely the number of controlling inputs should be at least 2m . But here 2m þ 3 or 2m þ 4 control inputs are needed. The reason for this extra control inputs is that there is no rule governing the emulation of functions, and emulation of functions for more than once is completely possible. These extra control inputs are the cost of obtaining a dynamically reconfigurable logic block. So by use of three or four extra control inputs one can construct all digital functions from the introduced computing model. Designer can provide all possible control inputs to the logic block, observe the emulated functions, and construct the instruction set of the logic block, which associates to each function, one control input that constructs it. The statistical modeling and study of the chaos based computing system can demonstrate how the unpredictability of a chaotic system working as the computing engine of the logic block can result in universality of the logic block in computation. 2.3. Robustness of model to environmental noise In the previous sections the structure of chaotic computing model was introduced and it was described how the unpredictability of chaotic systems can be utilized in universal computation. An important question remains. Is the obtained instruction set of the logic block robust to environmental noise? In this model, the chaotic system working as the engine of computing iterates for limited times (e.g. h times) if it is discrete, or for limited time (e.g. s) if it is continuous. Continuous chaotic systems can be discretized to maps by using Poincare cross sections [11]. So here we study robustness just in chaotic maps working as the computing engine of logic block. Orbits of chaotic computing engine can be made robust to additive noise by restricting them to the chaotic saddles, embedded in the system [3]. In our introduced computing model the output is the symbol of the partition that the state of the system, at the end of the evolution time, falls into. Hence the operation of chaotic computing model can be described as a set to set mapping, because for each symbolic itinerary, there is collection of initial conditions, grouped in a set, which produce the same symbolic itinerary under the iteration of chaotic map. Finally these initial conditions produce the same output. This phenomenon can be formulated as a symbolic cylinder [11] on which all the points in this cylinder symbolically behave the same under the iteration of the map, and finally produce the same output. For example for h iterations of chaotic map, a two-symbol {0, 1} cylinder is [11]: C i0 ;i1 ;i2 ;...;ih1 ¼ f/ 2 Xþ : /0 ¼ i0 ; /1 ¼ i1 ; . . . ; /h1 ¼ ih1 g;
ij 2 f0; 1g; j ¼ 0; 1; . . . ; h 1
ð8Þ
where X+ is symbolic phase space consisting of different symbolic itineraries, /: Xþ ¼ f0; 1gzþ ¼ f/ ¼ ð/0 ; /1 ; /2 ; . . . ; /n ; . . .Þ;
/d 2 f0; 1g; d ¼ 0; 1; 2; . . . n; . . .g
ð9Þ
In our chaos based computing model, /h-1 in Eq. (8) is the output of computation. Assume the forward translation map has mapped one set of inputs to an initial condition, which is in a cylinder, e.g., C i0 ;i1 ;i2 ;...;ih1 and h is iteration number of chaotic system working as computing engine. Until the noise perturbs the chosen initial condition to other points in this cylinder, the symbolic representation of the orbits originating from the perturbed initial condition remains unchanged and the gate will produce the correct result. Also if noise perturbs the images of the chosen initial condition into the images of this cylinder, the symbolic representation of orbits and final output will still remain unchanged and hence the gate will work correctly. This condition for robustness works well for initial conditions that are in middle of the cylinder. If one uses an initial condition that is near to the boundary of the partition (preimages of this boundary) small perturbations could bring the trajectory to the other partition that has a symbol different from that of original partition and as a result the output of computation changes (which is an obvious instability). The obvious solution to this problem is to avoid initial conditions that go near the boundaries. In other words we can define a forbidden region around the boundaries of the partition and dynamically remove this forbidden boundary and its preimages from the attractor [12]. The remaining of attractor is a chaotic saddle [12]. In [12] it has shown that such chaotic saddles are robust to additive noise and the symbolic itineraries of orbits within such chaotic saddles are robust to noise. To exploit this in our computing model the following method can be used [3]. In the process of assigning different control inputs to the system for obtaining instruction set of the logic block, we do not consider control inputs that produce trajectories that enter to forbidden region during evolution. By this policy the operation of chaotic logic gate will be restricted to the chaotic saddles within the chaotic attractor and such saddles are robust to noise [12]. Large forbidden region results in high robustness, and small forbidden region results in less robustness [12]. Environmental noise determines the measure of forbidden region in chaotic saddles to keep the instruction set stable. However notice that large forbidden region results in less unpredictability [12] and in consequence less flexibility for the computing system. Thus one should look for a tradeoff between robustness and unpredictability [12]. In [3] a model for the effects of the noise on one-dimensional discrete chaotic maps was presented. Such models of the effects of the noise on system help us in determination of measure of the forbidden region [3]. Also one can experimentally determine the appropriate measure of the forbidden region by testing different forbidden regions with different measures and then
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using the smallest one that keeps the computing system stable in the presence of environmental noises. In the presented Chua circuit based implementation for a chaotic logic block, we exploit this experimental approach for the determination of forbidden region size.
3. Experimental realization of a morphing chaotic logic block In this section we present the results of an analog electronic circuit experiment that demonstrates that the chaotic computing model is a universal approach for computing and one which can emulate many (if not all) digital functions. To study the feasibility of this model, and also experimental verification of the claim of universality of this chaotic computing model, a Chua circuit based two input, one output logic block is constructed. Notice the presented chaotic computing model, is a general m input, r output computing system. But here, for simplicity, we construct a 2 input, 1 output logic block to study whether it stably emulate all possible 2 input, 1 output functions? As described in Section 2.1, the computing model involves three steps; hence three clocks are needed to direct the system to perform these steps one by one. Fig. 2 shows the condition of theses three clocks relative to each other. In this implementation, a Chua circuit is the chaotic computing engine of the logic block. Here, the Chua circuit, as is illustrated in Fig. 3, is constructed based on [13]. We set the parameters of the Chua circuit as follows: R = 1.877 kX, C1 = 4.7 nF, L = 18 mH, C2 = 100 nF and r = 15X. As was discussed in Section 2.1, to use unpredictability of Chua circuit in computation, range of forward translation map should be unstable manifold of chaotic computing engine. Our chosen Chua circuit is a piecewise linear system, so within each linear region of Chua system, at each point the unstable manifold contains unstable tangent directions at that point. So we can set the range of forward translation map to an unstable tangent direction as well. In a piecewise linear system, like Chua system, these unstable tangent directions at each linear region are parallel to the unstable eigenvectors of that region. In our Chua system, the unstable eigenvector of the origin is approximately v2 = 0.109v1, il = 0. We choose following unstable direction as the range of forward translation map:
Initializing clock
t
Evolution clock
t
Sensing and output production clock
t
One instruction cycle
Fig. 2. Three clocks used in logic block. These clocks determine different steps of the algorithms.
R
C2
C1
r
Fig. 3. The Chua circuit is illustrated.
Nonlinear resistor
L
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v2 ¼ 0:109v1 0:00329
jv1 j < 1;
239
i3 ¼ 0
ð10Þ
As demonstrated in Section 2.2, three extra control bits make the probability of obtaining a universal computing system very near to 1. Thus here three extra control inputs are used and these 22 + 3 control inputs are utilized to obtain all possible two input, one output digital functions. Hardware implementation of a forward translation map is illustrated in Fig. 4. All inputs are passed through resistors and then are added together by a conventional op-amp based summation circuit. Actually this section of circuit is a digital to analog converter, which converts each set of digital inputs to a scalar. The resulted signal is v2, and fed to C2, as is shown in Fig. 5. On the other hand this signal is amplified by gain 9.11 and then added by 0.03 to track the unstable direction in Eq. (10). Notice Eq. (10) can be rewritten as v1 = 9.11v2 + 0.03,jv2j < 0.065.
Weighting Resistors
Summation circuit
Gain 9.11
Inverting Summation by 0.03
Gain -1
1k
1k
1k
23k
9.11k 0.03 v
11.75k
7.2
1k
5.61k
Control input
2.7k
1k
1k
To V1
0.06v
1.3k 0.618 k
To V2
0.315 k
Op-Amps: UA741 Switches : 4066 or manual Resistors : Low Tolerance
0.143 k
Data input 0.75v
0.047 k
Fig. 4. Forward translation map.
To initalizing circuit
To initalizing circuit
switch3
switch2
A
1.877 k
15
C1 =6.8n F
switch4
Nonlinear resistor
1 8mH
B
C2 =100 nF
switch1
Fig. 5. Connecting forward translation map to Chua circuit through switches number 2 and 3.
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Fig. 6. Outputs of forward translation map introduced in Fig. 3. (a) and (b) are showing v1 and v2, respectively, when different combinations of inputs are giving to the circuit.
The outputs of the circuit in Fig. 4 when different combinations of data and control inputs are given to the circuit are shown in Fig. 6. As is obvious from the Fig. 6, the outputs are tracking the desired unstable direction in Eq. (10). This circuit is connected to a Chua circuit through analog switches (number 2, 3) as shown in Fig. 5. The control of these two switches and also switch number 1 is initializing clock. When this clock is on, the initializing circuit connects to the Chua circuit through switch number 2 and 3, and initiates it to the desired state based on the inputs, and also the current of inductor resets to 0 through switch 1. When this clock goes off, the initialization circuits disconnects from Chua circuit. We have added an extra switch, switch number 4 in Fig. 5. The reason for addition of this switch is that it lets the points A and B in Fig. 5 be initialized to different voltages and makes it possible to simultaneously reset the current of the inductor to zero and initialize the capacitor C2 to different voltages. The control of this switch is the evolution clock. Thus this switch is open during initialization, letting the initializing circuit to set the states of inductor and capacitor independently to desired values and is closed during the evolution clock, letting the system evolve freely. Data and control inputs should be ready at the rising edge of the initializing clock, and should be kept fixed when the initializing clock is 1. During this interval, the initializing circuit produces associated initial condition and sets the state of the Chua circuit to it. Note that at each time the current of the inductor is reset to 0 (As stated in Eq. (10)). During the second step of computation, named evolution, which is indicated by the evolution clock, transmission gates between the Chua circuit and the initializing circuits are disconnected and switch 4 closes letting the Chua circuit evolve freely for a fixed time. At the third step of computation, determined by sensing and output production clock, the state of the system is sampled by the sample and hold (S/H) circuits and is passed on to the state detection circuit. To construct one-output functions, one needs to divide the state space of the system to two parts, and assign to each part one symbol, 0 or 1. The best choice, which is compatible by the dynamical aspects of the Chua circuit, is to use the stable eigenplane of the origin as the partition boundary. In the other words, the upper scroll represents 1 and the lower scroll represents 0. Note that the orbits never cross the manifold. Hence one could approximate the stable eigenplane of the inner region, according to the orientation of the orbits, entering into the inner region. Based on Fig. 7, one could approximate the stable eigenplane with v1 = 3.3v2 (It is almost independent of il). Hardware implementation of this decoding is shown in Fig. 8. This circuit is connected to the Chua circuit through analog switches number 5 and 6, where their controls is output production clock. When the state detection and output production clock comes, v1 and v2 are sampled and hold by sampling capacitor. These voltages are compared to detect at which scroll the final state is situated, and based on it produces 1 or 0. As introduced in Section 2.3, chaotic saddles can be recruited to make the computing system robust. Chaotic saddles are defined through introducing forbidden regions around partition boundaries, here the stable eigenplane. In this paper the forbidden region is the space between two parallel planes around the stable eigenplane of the origin, and these two planes are parallel to this eigenplane too. This situation is depicted in Fig. 7. The measure of this forbidden region depends on the power of the noise (intensity of the noise), affecting the system. Orbits that enter to this forbidden region are sensitive to noise, because a small amount of noise may bring the orbit to the wrong partition (scroll), which has the reverse symbol. But orbits outside of this forbidden region, which construct the chaotic saddle, are robust to noise and their corresponding symbolic itineraries remain relatively insensitive to noise. Our chaotic computing model consists of translating inputs to the points on the unstable manifold of the system, evolving these points under chaotic dynamics of
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Fig. 7. Partitioning double-scroll Chua circuit to 0 and 1. Also forbidden region is shaded.
Gain : -3.3 Buffer
V2
Buffer switch5
3.3k 1k
C =1nF Output production clock
Comparator
Buffer
C=1nF
Buffer
V1
switch 6
C=1nF
Op-Amps: AD712 Switchs : 4066
Output production clock
Fig. 8. Backward translation map. This circuit samples the states of the Chua circuit and based on it produces the output.
the system, and observing and decoding the state of the chaotic system after evolution time to outputs of computation. To make this process robust, these orbits should not be allowed to enter to forbidden region. To implement this idea, we need a circuit to detect whether this computing orbit enters to forbidden region or not. In practice, we try different measures of the forbidden region, from 0 to 3, and found 1 as an appropriate and robust value for this measure, which makes the logic block robust in one side, and on the other side it is not so large that we miss most of the possible control inputs by allowing the system to enter forbidden region. Notice that this value depends on the test environment and implementation technology. The forbidden region is determined through two concurrent constraints: jv1j < 1 and 3.3v2 1 < v1 < 3.3 v2 + 1. Thus to implement this, one should check whether the computing orbit satisfy these constraints at least once in its evolution? If the orbit satisfies these constraints at least once, it shows that it has entered the forbidden region and hence this reconfigured or constructed gate is very sensitive to noise. Implementation of these two constraints is depicted in Fig. 9. This circuit is connected directly to v1 and v2 and the computing orbit is tracked and checked whether it enters into the forbidden region. The upper side of the circuit depicted in Fig. 9, determined by dashed line, detects the second constraint (3.3v2 1 < v1 < 3.3 v2 + 1), and lower part the first constraint (jv1j < 1). Then the results of these two constraints are fed to AND gate to find out when these two constraints are
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3.3k 1k
1v
V2
1v
−3.3v2 − 1 < v1 < −3.3v2 + 1
Output of robustness circuit
1v
C = 1nF
v1 〈1
Buffer
Op-Apms: AD712 And gate: 4082
1v
V1
Fig. 9. Robustness detection circuit is achieved by implementing two introduced concurrent constraints, determining forbidden region. This circuit detects whether computing orbits go to forbidden region or not.
satisfied together and hence the orbit is in the forbidden region. Notice this robustness detection circuit is not needed for computing operation of the logic block, here we used it just for detecting the stability of the instruction set and after determination of a robust instruction set, there is no need for this circuit. To derive the instruction set of this logic block that associates to each function one control input, we test the system with different control inputs. With each control input, we evaluate the system outputs under different data inputs. The results are shown in Table 3. During testing the logic block with different control inputs, whenever one of the computing orbits goes to the forbidden region, the output of robustness detection circuit, which is shown in Fig. 9, goes to 1. In this condition we neglect the currently utilized control input and try another control input. Each row in Table 3 represents one digital function. In each row, the bits in first field of the row from left to right represents the output when inputs
Table 3 Instruction set of logic block Function
Control input
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
1100011 1111000 1100010 1001001 1100110 0110111 0111000 0100001 1101101 1011110 0110110 1111011 0010101 1111010 1010101 1110000
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changes from 00 to 11 step by step (i.e., 00, 01, 10, 11), respectively. Actually they are different samples of the random space introduced in Eq. (3). The second column represents the corresponding digital control inputs. These records could be used as a lookup table during reconfiguration of the system. After this work, whenever a special two input one output digital function is needed one can then simply consult the lookup table and use the control inputs that robustly give the desired function. For example, to construct OR gate, use ‘‘0100001” as control input, to construct NAND gate use ‘‘1010101”. Note that reconfiguration takes place dynamically. This logic block requires three clocks as is shown in Fig. 2. These clocks are generated by a microcontroller. One instruction cycle of this constructed logic block is 0.002 s. To implement this logic block it is necessary to take in account some practical considerations. Hazard in logic design [14] is one of the most important considerations in designing digital systems. The cause of hazard is different timing delay of different components and paths in the circuit, which results in incorrect momentary changes in output of circuit [14]. In the constructed logic block, the hazard may occur in the robustness detection circuit. The duty of this circuit is to detect whether the computing orbit goes to forbidden region or not and this region has determined by two concurrent constraints. Hazard in robustness detection circuit disturbs the concurrency between these two constraints. To overcome this problem we make the signal transition time in different paths equal by adding some extra components. Another important subject is that this computing system is dynamics based, so anything that changes the dynamics of the system results in changes of the structure of computing system. As an example, if the utilized resistors differ from the given values, or other types of op-amps are used, then the dynamics of the system changes and the obtained instruction set will be different. But notice that the resultant instruction set for this new logic block is robust relative to its own logic block. When all logic blocks should have the same instruction set, more advanced technology, e.g. VLSI, should be used. Another practical consideration is integrating these different components of the logic block, e.g. forward and backward translation maps, Chua circuit, etc, in a system so that loading effects does not affect the behavior of these components. In our implementation, some buffers are inserted between these components to prevent such problems and keep the blocks electrically independent.
4. Conclusion To study the feasibility of chaotic flexible computing model, and also experimental verification of its flexibility, in this paper a Chua circuit based logic block was constructed and studied. This logic block can be controlled to morph between all 2 input, 1 output digital functions. The instruction set of this logic block was derived and presented in Table 3. This table can be used for dynamic reconfiguration of the constructed logic block. Also chaotic saddles are utilized to make the instruction set of the logic block robust with respect to noise. Chaotic saddles obtain through introduction of some forbidden gap around partition boundaries. Different sizes of forbidden regions (regions of sensitivity to noise) were tested and finally, the gap was fixed to the minimum value that keeps the instruction set of the logic block stable to noise. This achieved instruction set was tested more than hundreds to test the robustness of the instruction set to noise and always it was stable. The main purpose of this work is to demonstrate the construction of robust, analog reconfigurable chaotic logic blocks with discrete element electronics. However the presented logic block designs have not been optimized to reduce size and power consumption and to maximize speed but merely been constructed to demonstrate the proof of concept. More sophisticated VLSI designs are currently being pursued by us and others to obtain optimized VLSI components that are optimal for possible commercial applications.
Acknowledgement William Ditto would like to acknowledge the funding support of the Office of Naval Research [N000140211019] and of ChaoLogix Inc.
References [1] Sinha S, Ditto WL. Computing with distributed chaos. Phys Rev E 1999;60:363–77. [2] Sinha S, Munakata T, Ditto WL. Flexible parallel implementation of logic gates using chaotic elements. Phys Rev E 2002;65(1– ):036216. [3] Jahed-Motlagh MR, Kia B, Ditto WL, Sinha S. Fault tolerance and detection in chaotic computers. Int J Bifurcat Chaos 2007;17(6):1–14.
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[4] Murali K, Sinha S, Ditto WL. Implementation of NOR gate by a chaotic Chua’s circuit. Int J Bifurcat Chaos (Lett.) 2003;13:2669–72. [5] Murali K, Sinha S, Ditto WL. Realization of the fundamental NOR gate using a chaotic circuit. Phys Rev E 2003;68(1–5):016205. [6] Murali K, Sinha S, Ditto WL. Construction of a reconfigurable dynamic logic cell. Pramana-J Phys 2005;64(3):433–41. [7] Cafagna D, Grassi G. Chaos-based SR flip-flop via Chua’s circuit. Int J Bifurcat Chaos 2006;16:1521–6. [8] Lai Y, Wang P. Hierarchical interconnection structures for field programmable gate arrays. IEEE Trans VLSI Syst 1997;5(2):186–96. [9] Shannon CE. A mathematical theory of communication. The Bell Syst Tech J 1948;27. [10] Hodges JL, Lehmann EL. Basic concepts of probability and statistics. 2nd ed. Holden-Day San Francisco; 1970. [11] Afraimovich V, Hsu SB. Lectures on chaotic dynamical systems. American Mathematics Society; 2002. [12] Bollt E. Review of chaos communication by feedback control of symbolic dynamics. IJBC 2003;13(2):269–85. [13] Kennedy MP. Three steps to chaos-part two: a Chua circuit primer. IEEE Trans Circuit Syst 1993;40(10). [14] Abramovici M, Breuer MA, Friedman AD. Digital system testing and testable design. Wiley–IEEE Press; 1994.
Chaos, Solitons and Fractals 41 (2009) 233–244 www.elsevier.com/locate/chaos
Reconfigurable logic blocks based on a chaotic Chua circuit Hamid Reza Pourshaghaghi a,b, Behnam Kia a, William Ditto c,d,*, Mohammad Reza Jahed-Motlagh a,b a
Chaos Computing Lab, Department of Computer Engineering, Iran University of Science and Technology, Tehran, Iran b Department of Electrical Engineering, Iran University of Science and Technology, Tehran, Iran c J. Crayton Pruitt Family Department of Biomedical Engineering, University of Florida, Gainesville, FL 32611-6131, USA d ChaoLogix Inc., 101 SE 2nd Place, Suite 201-B, Gainesville, FL 32601, USA Accepted 27 November 2007
Abstract To investigate morphable chaotic logic we have constructed, out of discrete circuitry, a chaotic logic block that can morph between all two input, one output logic gates. Additionally, we investigate the sensitivity of such a block to noise and have been able to formulate a method that demonstrates that the chaotic saddles of the inherent chaotic dynamics can be exploited to enhance the robustness of the logic functions with respect to noise. Ó 2007 Elsevier Ltd. All rights reserved.
1. Introduction Recently there have been breakthroughs in the exploitation of chaotic dynamics to perform calculations through morphing chaotic logic gates [1–3]. The next steps in the evolution of mature chaotic computing systems involve demonstrating that morphing chaotic logic elements can be combined into chaotic logic blocks to perform higher level functions. Towards this end several efforts have shown promising results. In [4] an analog continuous time chaotic Chua circuit based logic block was introduced which constructs a single NOR gate. In [5] a single NOR gate was constructed in a discrete time chaotic map. Additionally, it has been shown [6] that fundamental logic gates, consisting of AND, OR, XOR and NOT gates can be constructed by a single morphing chaotic circuit. In [7] construction of sequential gates based on chaotic circuits was studied, and a Chua circuit based SR flip-flop was presented. The next real challenge in the construction of chaos based morphing computer architectures lies in how to interconnect logic blocks to perform higher order functions [8]. It also has been problematic to construct robust analog chaotic circuits that can demonstrate reliable computation either at the logic or higher order levels. The purpose of this work is to demonstrate that we can build stable chaotic logic blocks and higher order functions from analog chaotic circuits. In [3] the theoretical background for direct construction of all digital functions from a single chaotic element was introduced. Based on [3], in this paper, we construct a robust discrete analog circuit that can be reconfigured to work as all two input, one output combinational logic gates. One important challenge for the construction of practical chaos * Corresponding author. Address: J. Crayton Pruitt Family Department of Biomedical Engineering, University of Florida, Gainesville, FL 32611-6131, USA. E-mail address: [email protected]fl.edu (W. Ditto).
0960-0779/$ - see front matter Ó 2007 Elsevier Ltd. All rights reserved. doi:10.1016/j.chaos.2007.11.030
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based reconfigurable logic blocks deals with the stability of instruction set of such logic block in the presence of environmental noise. In this paper, we utilize chaotic saddles to improve the robustness of the constructed chaotic logic block, in the presence of noise. We demonstrate that by restricting the operation of chaotic logic gates to the chaotic saddles within the chaotic attractor the instruction set of the logic block, remains robust and fixed in front of environmental noise. In this paper, a Chua circuit is chosen as continuous time analog chaotic circuit in implementation of logic block, because it is a well-characterized chaotic circuit for the evaluation of chaos based applications. The flow of this paper is as follows: In part 2 theoretical background for chaotic computing is introduced, in part 3 the experimental realization of a morphing logic block is presented. The paper is concluded in part 4.
2. Theoretical background for chaotic computing Chaotic systems are rich sources of behaviors and dynamics, which can be recruited in different branches of informatics. Recently the possibility of emulation and construction of reconfigurable logic blocks from chaotic systems have been introduced [1–6]. In [3] it was demonstrated that every logic gate could be constructed from a single chaotic system. The main idea is to harness the library of the many orbits/patterns inherent in chaotic systems to select out logic operations and to utilize the sensitivity to initial conditions (or unpredictability) of such systems to perform rapid switching (morphing) between all logic functions. These features provide us with all that we need to create reconfigurable logic blocks out of analog circuits. By applying special encoding methods, or equally restricting the dynamics of the chaotic systems to a robust chaotic saddle embedded in the chaotic attractor of the system, the symbolic itineraries of the orbits remain stable and robust in the presence of noise and fluctuations. This robustness to environmental noise means that, although the system is chaotic, the type of constructed gate remains stable. In this part, in Section 2.1 the chaotic computing model is introduced, in Section 2.2 we demonstrate how can unpredictability of chaotic computing engine, result in universality of chaotic logic block in computation, and in Section 2.3 we describe how can this logic block be made robust to noise. 2.1. Chaos based flexible computing model Chaos based computation consists of a chaotic system (continuous or discrete) as the computing engine and two translation maps, which bridge between the chaotic computing engine, the inputs and the outputs [3]. In this model, chaotic system provides us with the unpredictability, which based on Shannon’s information theory point of view, is a rich source of information [9]. The first (forward) translation map, translates the inputs to the points in state space of the chaotic computing engine, to be processed by the chaotic computing engine, and the second (backward) translation map, translates the final state of the chaotic computing engine to the outputs. To be more precise, let the m digital data inputs to the computing model are X 1data ; X 2data ; . . . ; X mdata and the n digital control inputs are X 1control ; X 2control ; . . . ; X ncontrol . A schematic of this approach is shown in Fig. 1. The computing operation of the system consists of three steps: Step 1: Each set of data and control inputs is mapped to a point on the unstable manifold of the chaotic system. This point, in the next step of the computing operation of the logic block will be used as the initial condition of the chaotic systems. Let T be the forward translation map, L the set, consisting of the all possible values of a digital
Data input : 1 2 m X data , X data , ... , X data
Forward translation map
Initial Condition of Chaotic System
Chaotic system as computing engine
Final State of Chaotic System
Backward translation map
output
Control input : 1 2 n X control , X control , ... , X control
Fig. 1. Schematics of chaotic computing model. Inputs are mapped to an initial condition of chaotic system working as computing engine, and the final state of the chaotic system is decoded to output through backward translation map.
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binary variable, {0, 1}, then L(n+m) represents the domain of T which consists of all possible combinations of digital data and control inputs, b, be the unstable manifold of the chaotic system, Rs the general state space of the chaotic system, and Y be the output of forward translation map on the unstable manifold. In this case the general form of forward translation map,T, is as follows: T : LðmþnÞ ! b; Y ¼
b Rs ; L ¼ f0; 1g
T ðX 1control ; X 2control ; . . . ; X ncontrol ; X 1data ; X 2data ; . . . ; X mdata Þ
ð1Þ ð2Þ
Based on this definition, the forward translation map can be any map, working between inputs and the unstable manifold of the chaotic system. In this section we will introduce another constraint for the forward translation map, regarding the distance between the consecutive images of forward translation map on unstable manifold, which should be considered during choosing the appropriate forward translation map. In practice we should choose the simplest forward translation map for implementation that follows the constraints. Step 2: Under the initial conditions produced by forward translation map, the chaotic system evolves for a fixed time (for a fixed iteration number, if the chaotic system is discrete). This evolution time should be chosen so that orbits starting from nearby initial conditions produced by forward translation of the map statistically uncorrelated. This is the new constraint on forward translation map, which describes that the distance between images of the map should be wide enough so that after the evolution time they get uncorrelated. Step 3: After the evolution time, the system stops working and its state at the end of evolution time is sampled. This final state is decoded to the outputs through the backward translation map. In decoding the final state of the system to a symbol as output of computation, symbolic dynamics can be utilized which consists of partitioning state space of the system, and assigning a symbol to each partition. In our computing algorithm the number of these partitions should be equal to the number of possible outputs of computation and the symbols of these partitions are the possible outputs of the computation. For example in building two input one output logic gates, state space of chaotic system should be divided to two parts and the symbols of these partitions should be 0 and 1. The output of the computation is the symbol of partition that final state of the chaotic system (computing engine) settles upon. At the end, notice the aim of this model is to utilize unpredictability of chaotic systems in flexible computations. Toward this aim, forward translation map, maps digital data and control inputs to the points on the unstable manifold of the chaotic system, and these points evolve under chaotic dynamics of the system. So by changing just one bit of control inputs, the orbits starting from initial conditions produced by forward translation map change considerably, resulting in emulation of a different digital function. So this model, recruits unpredictability of chaotic systems in flexible computations. 2.2. How can unpredictability of chaotic computing engines result in universality of logic block in computation? The aim of chaotic computing approach is to transform the unpredictability of a chaotic system working as the computing engine, to provide the mechanism for reconfiguring the logic block. The purpose of this part is to quantitatively demonstrate how and why the chaotic computing approach is computationally universal. Orbits of chaotic systems are sensitive to initial conditions. The forward translation map, maps different sets of the inputs to different points on unstable manifold of chaotic system and these points are used as initial conditions of chaotic system. Thus the orbits of chaotic system are very sensitive to the bits of inputs and they dramatically change, when there is just a change in one bit of the control input. Thus controlling inputs can be used to reconfigure a chaotic logic block. To evaluate which digital function is emulated with a control input, one can simply assign this control input to the logic block and give all combinations of data inputs to the logic block and observe the output to construct the truth table of the constructed function. With a high probability, by changing the control input and repeating this procedure (of constructing the truth table of digital function) one may obtain another digital function different from the first one. This is the meaning of the flexibility, or equivalently reconfigurability, of chaotic logic block in computations. The remaining questions are: (1) how flexible is this computation model? and (2) is this model computationally universal? To answer these questions we apply statistics and probability theory to chaotic computation. Without loss of the generality, let the goal be the emulation of m-input, 1-output combinational digital functions. At first we hold the controlling inputs fixed. Based on the statistical uncorrelation of orbits produced by the chaotic systems the process of assigning each set of data inputs and observing the output is a seemingly random experiment from the view of external observer. Notice that the initial conditions produced by forward translation map are situated on unstable manifold of the chaotic system, thus by evolution of the system they are strongly uncorrelated. Hence an external observer, when provided
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Table 1 Probabilities of random variable Random variable Probability
1 P
0 q=1p
different inputs to system, observes completely different and uncorrelated outputs from the system. Loosely speaking, the external observer finds the outputs random. In fact this process is a Bernoulli experiment [10] where the output has two possible conditions, 0 or 1. Let Z be random variable of Bernoulli distribution (Z Ber(p)). The probabilities of this random variable are shown in Table 1 [3]. The process of assigning different possible combinations of data inputs (still with a fixed control input) and observing the binary outputs is a Binomial experiment [10]. The reason is again uncorrelation of orbits (iterates) of the system under the chaotic dynamics of the system. The random variable of this experiment is V Bin(2m,p) where p is the probability of success of an individual Bernoulli experiment and 2m shows that the Binomial experiment consists of 2m Bernoulli experiments. We define the sample space of this Binomial experiment as follows: S B ¼ fa1 a2 . . . a2m jaj 2 f0; 1gg
ð3Þ
where aj is the output of jth Bernoulli experiment. In fact each sample of this space is a truth table of one m-input, 1output digital function. Each Binomial experiment takes one of these samples as result and it means that the chaosbased model emulate this function with the used control input. The probability of obtaining a desired function, e.g. a01 a02 . . . a02m by this Binomial experiment is: P Binomial ða01 a02 . . . a02m Þ ¼ P Bernoulli ða01 Þ P Bernoulli ða02m Þ
ð4Þ
This probability function can be simplified to the following: P Binomial ða01 a02 . . . a02m Þ ¼ ps qr ¼ ps ð1 pÞr
ð5Þ
where p and q are the probabilities of observing ‘‘1” and ‘‘0” as the outputs of Bernoulli experiment, respectively, ‘‘s” and ‘‘r” are the number of ‘‘1”s and ‘‘0”s in the desired sample of space (representing desired function), respectively. Based on Eq. (5) the computation model will be biased to simulate functions with more ‘‘1”s (‘‘0”s) in their outputs if 0.5 < p (0.5 < q). To obtain a generic (or fair in the sense of statistical fairness) computational model one must have p ¼ q ¼ 12 [3]. This is a new constraint the designer should follow it during implementation. Based on this fact, to have a flexible computing system, we fix the value of p and q to 0.5. As a result the probability function of obtaining desired function by Binomial experiment becomes: P Binomial ða01 a02 . . . a02m Þ ¼ ð0:5Þ2
m
ð6Þ
Thus the probability of obtaining the desired function is very low and one should repeat the Binomial experiment to obtain the desired function. One can repeat this Binomial experiment by changing the control inputs. Such binomial experiments are Bernoulli experiment again because they have two possible conditions, succeeding in simulation of desired function or failure in it. The probabilities of random variable of new Bernoulli experiment are shown in Table 2. Repeating the new Bernoulli experiment constructs a new Binomial experiment. Notice again that these new Bernoulli experiments are themselves independent because of the lack of correlation between orbits. The random variable m of new Binomial experiment is B Binðf ; ð0; 5Þ2 ). Now the question is about the value of f, where one can obtain the desired function by this iteration of Bernoulli experiment. This probability can be obtained based on the following equation: P Bin ðObserving desired function by f iterationsÞ ¼ 1 pBin ðno observation in f iterationÞ m
¼ 1 ð1 ð0:5Þ2 Þf
ð7Þ
An interesting feature of this probability function is that it is approximately independent of m and is just a function of f m m m [3]. With f ¼ 22 , this probability function becomes about 0.6, with f ¼ 22 þ2 it becomes about 0.98, by f ¼ 22 þ3 it m m becomes 0.9997 and by f ¼ 22 þ4 it becomes 1 when calculating in double precision. Notice that there are 22 different Table 2 Probabilities of random variable Outcome Probability
Success in emulation (1) m ð0:5Þ2
Failure inm emulation (0) 1 ð0:5Þ2
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m-input, 1-output digital functions and hence to determine all of them uniquely the number of controlling inputs should be at least 2m . But here 2m þ 3 or 2m þ 4 control inputs are needed. The reason for this extra control inputs is that there is no rule governing the emulation of functions, and emulation of functions for more than once is completely possible. These extra control inputs are the cost of obtaining a dynamically reconfigurable logic block. So by use of three or four extra control inputs one can construct all digital functions from the introduced computing model. Designer can provide all possible control inputs to the logic block, observe the emulated functions, and construct the instruction set of the logic block, which associates to each function, one control input that constructs it. The statistical modeling and study of the chaos based computing system can demonstrate how the unpredictability of a chaotic system working as the computing engine of the logic block can result in universality of the logic block in computation. 2.3. Robustness of model to environmental noise In the previous sections the structure of chaotic computing model was introduced and it was described how the unpredictability of chaotic systems can be utilized in universal computation. An important question remains. Is the obtained instruction set of the logic block robust to environmental noise? In this model, the chaotic system working as the engine of computing iterates for limited times (e.g. h times) if it is discrete, or for limited time (e.g. s) if it is continuous. Continuous chaotic systems can be discretized to maps by using Poincare cross sections [11]. So here we study robustness just in chaotic maps working as the computing engine of logic block. Orbits of chaotic computing engine can be made robust to additive noise by restricting them to the chaotic saddles, embedded in the system [3]. In our introduced computing model the output is the symbol of the partition that the state of the system, at the end of the evolution time, falls into. Hence the operation of chaotic computing model can be described as a set to set mapping, because for each symbolic itinerary, there is collection of initial conditions, grouped in a set, which produce the same symbolic itinerary under the iteration of chaotic map. Finally these initial conditions produce the same output. This phenomenon can be formulated as a symbolic cylinder [11] on which all the points in this cylinder symbolically behave the same under the iteration of the map, and finally produce the same output. For example for h iterations of chaotic map, a two-symbol {0, 1} cylinder is [11]: C i0 ;i1 ;i2 ;...;ih1 ¼ f/ 2 Xþ : /0 ¼ i0 ; /1 ¼ i1 ; . . . ; /h1 ¼ ih1 g;
ij 2 f0; 1g; j ¼ 0; 1; . . . ; h 1
ð8Þ
where X+ is symbolic phase space consisting of different symbolic itineraries, /: Xþ ¼ f0; 1gzþ ¼ f/ ¼ ð/0 ; /1 ; /2 ; . . . ; /n ; . . .Þ;
/d 2 f0; 1g; d ¼ 0; 1; 2; . . . n; . . .g
ð9Þ
In our chaos based computing model, /h-1 in Eq. (8) is the output of computation. Assume the forward translation map has mapped one set of inputs to an initial condition, which is in a cylinder, e.g., C i0 ;i1 ;i2 ;...;ih1 and h is iteration number of chaotic system working as computing engine. Until the noise perturbs the chosen initial condition to other points in this cylinder, the symbolic representation of the orbits originating from the perturbed initial condition remains unchanged and the gate will produce the correct result. Also if noise perturbs the images of the chosen initial condition into the images of this cylinder, the symbolic representation of orbits and final output will still remain unchanged and hence the gate will work correctly. This condition for robustness works well for initial conditions that are in middle of the cylinder. If one uses an initial condition that is near to the boundary of the partition (preimages of this boundary) small perturbations could bring the trajectory to the other partition that has a symbol different from that of original partition and as a result the output of computation changes (which is an obvious instability). The obvious solution to this problem is to avoid initial conditions that go near the boundaries. In other words we can define a forbidden region around the boundaries of the partition and dynamically remove this forbidden boundary and its preimages from the attractor [12]. The remaining of attractor is a chaotic saddle [12]. In [12] it has shown that such chaotic saddles are robust to additive noise and the symbolic itineraries of orbits within such chaotic saddles are robust to noise. To exploit this in our computing model the following method can be used [3]. In the process of assigning different control inputs to the system for obtaining instruction set of the logic block, we do not consider control inputs that produce trajectories that enter to forbidden region during evolution. By this policy the operation of chaotic logic gate will be restricted to the chaotic saddles within the chaotic attractor and such saddles are robust to noise [12]. Large forbidden region results in high robustness, and small forbidden region results in less robustness [12]. Environmental noise determines the measure of forbidden region in chaotic saddles to keep the instruction set stable. However notice that large forbidden region results in less unpredictability [12] and in consequence less flexibility for the computing system. Thus one should look for a tradeoff between robustness and unpredictability [12]. In [3] a model for the effects of the noise on one-dimensional discrete chaotic maps was presented. Such models of the effects of the noise on system help us in determination of measure of the forbidden region [3]. Also one can experimentally determine the appropriate measure of the forbidden region by testing different forbidden regions with different measures and then
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using the smallest one that keeps the computing system stable in the presence of environmental noises. In the presented Chua circuit based implementation for a chaotic logic block, we exploit this experimental approach for the determination of forbidden region size.
3. Experimental realization of a morphing chaotic logic block In this section we present the results of an analog electronic circuit experiment that demonstrates that the chaotic computing model is a universal approach for computing and one which can emulate many (if not all) digital functions. To study the feasibility of this model, and also experimental verification of the claim of universality of this chaotic computing model, a Chua circuit based two input, one output logic block is constructed. Notice the presented chaotic computing model, is a general m input, r output computing system. But here, for simplicity, we construct a 2 input, 1 output logic block to study whether it stably emulate all possible 2 input, 1 output functions? As described in Section 2.1, the computing model involves three steps; hence three clocks are needed to direct the system to perform these steps one by one. Fig. 2 shows the condition of theses three clocks relative to each other. In this implementation, a Chua circuit is the chaotic computing engine of the logic block. Here, the Chua circuit, as is illustrated in Fig. 3, is constructed based on [13]. We set the parameters of the Chua circuit as follows: R = 1.877 kX, C1 = 4.7 nF, L = 18 mH, C2 = 100 nF and r = 15X. As was discussed in Section 2.1, to use unpredictability of Chua circuit in computation, range of forward translation map should be unstable manifold of chaotic computing engine. Our chosen Chua circuit is a piecewise linear system, so within each linear region of Chua system, at each point the unstable manifold contains unstable tangent directions at that point. So we can set the range of forward translation map to an unstable tangent direction as well. In a piecewise linear system, like Chua system, these unstable tangent directions at each linear region are parallel to the unstable eigenvectors of that region. In our Chua system, the unstable eigenvector of the origin is approximately v2 = 0.109v1, il = 0. We choose following unstable direction as the range of forward translation map:
Initializing clock
t
Evolution clock
t
Sensing and output production clock
t
One instruction cycle
Fig. 2. Three clocks used in logic block. These clocks determine different steps of the algorithms.
R
C2
C1
r
Fig. 3. The Chua circuit is illustrated.
Nonlinear resistor
L
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v2 ¼ 0:109v1 0:00329
jv1 j < 1;
239
i3 ¼ 0
ð10Þ
As demonstrated in Section 2.2, three extra control bits make the probability of obtaining a universal computing system very near to 1. Thus here three extra control inputs are used and these 22 + 3 control inputs are utilized to obtain all possible two input, one output digital functions. Hardware implementation of a forward translation map is illustrated in Fig. 4. All inputs are passed through resistors and then are added together by a conventional op-amp based summation circuit. Actually this section of circuit is a digital to analog converter, which converts each set of digital inputs to a scalar. The resulted signal is v2, and fed to C2, as is shown in Fig. 5. On the other hand this signal is amplified by gain 9.11 and then added by 0.03 to track the unstable direction in Eq. (10). Notice Eq. (10) can be rewritten as v1 = 9.11v2 + 0.03,jv2j < 0.065.
Weighting Resistors
Summation circuit
Gain 9.11
Inverting Summation by 0.03
Gain -1
1k
1k
1k
23k
9.11k 0.03 v
11.75k
7.2
1k
5.61k
Control input
2.7k
1k
1k
To V1
0.06v
1.3k 0.618 k
To V2
0.315 k
Op-Amps: UA741 Switches : 4066 or manual Resistors : Low Tolerance
0.143 k
Data input 0.75v
0.047 k
Fig. 4. Forward translation map.
To initalizing circuit
To initalizing circuit
switch3
switch2
A
1.877 k
15
C1 =6.8n F
switch4
Nonlinear resistor
1 8mH
B
C2 =100 nF
switch1
Fig. 5. Connecting forward translation map to Chua circuit through switches number 2 and 3.
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Fig. 6. Outputs of forward translation map introduced in Fig. 3. (a) and (b) are showing v1 and v2, respectively, when different combinations of inputs are giving to the circuit.
The outputs of the circuit in Fig. 4 when different combinations of data and control inputs are given to the circuit are shown in Fig. 6. As is obvious from the Fig. 6, the outputs are tracking the desired unstable direction in Eq. (10). This circuit is connected to a Chua circuit through analog switches (number 2, 3) as shown in Fig. 5. The control of these two switches and also switch number 1 is initializing clock. When this clock is on, the initializing circuit connects to the Chua circuit through switch number 2 and 3, and initiates it to the desired state based on the inputs, and also the current of inductor resets to 0 through switch 1. When this clock goes off, the initialization circuits disconnects from Chua circuit. We have added an extra switch, switch number 4 in Fig. 5. The reason for addition of this switch is that it lets the points A and B in Fig. 5 be initialized to different voltages and makes it possible to simultaneously reset the current of the inductor to zero and initialize the capacitor C2 to different voltages. The control of this switch is the evolution clock. Thus this switch is open during initialization, letting the initializing circuit to set the states of inductor and capacitor independently to desired values and is closed during the evolution clock, letting the system evolve freely. Data and control inputs should be ready at the rising edge of the initializing clock, and should be kept fixed when the initializing clock is 1. During this interval, the initializing circuit produces associated initial condition and sets the state of the Chua circuit to it. Note that at each time the current of the inductor is reset to 0 (As stated in Eq. (10)). During the second step of computation, named evolution, which is indicated by the evolution clock, transmission gates between the Chua circuit and the initializing circuits are disconnected and switch 4 closes letting the Chua circuit evolve freely for a fixed time. At the third step of computation, determined by sensing and output production clock, the state of the system is sampled by the sample and hold (S/H) circuits and is passed on to the state detection circuit. To construct one-output functions, one needs to divide the state space of the system to two parts, and assign to each part one symbol, 0 or 1. The best choice, which is compatible by the dynamical aspects of the Chua circuit, is to use the stable eigenplane of the origin as the partition boundary. In the other words, the upper scroll represents 1 and the lower scroll represents 0. Note that the orbits never cross the manifold. Hence one could approximate the stable eigenplane of the inner region, according to the orientation of the orbits, entering into the inner region. Based on Fig. 7, one could approximate the stable eigenplane with v1 = 3.3v2 (It is almost independent of il). Hardware implementation of this decoding is shown in Fig. 8. This circuit is connected to the Chua circuit through analog switches number 5 and 6, where their controls is output production clock. When the state detection and output production clock comes, v1 and v2 are sampled and hold by sampling capacitor. These voltages are compared to detect at which scroll the final state is situated, and based on it produces 1 or 0. As introduced in Section 2.3, chaotic saddles can be recruited to make the computing system robust. Chaotic saddles are defined through introducing forbidden regions around partition boundaries, here the stable eigenplane. In this paper the forbidden region is the space between two parallel planes around the stable eigenplane of the origin, and these two planes are parallel to this eigenplane too. This situation is depicted in Fig. 7. The measure of this forbidden region depends on the power of the noise (intensity of the noise), affecting the system. Orbits that enter to this forbidden region are sensitive to noise, because a small amount of noise may bring the orbit to the wrong partition (scroll), which has the reverse symbol. But orbits outside of this forbidden region, which construct the chaotic saddle, are robust to noise and their corresponding symbolic itineraries remain relatively insensitive to noise. Our chaotic computing model consists of translating inputs to the points on the unstable manifold of the system, evolving these points under chaotic dynamics of
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Fig. 7. Partitioning double-scroll Chua circuit to 0 and 1. Also forbidden region is shaded.
Gain : -3.3 Buffer
V2
Buffer switch5
3.3k 1k
C =1nF Output production clock
Comparator
Buffer
C=1nF
Buffer
V1
switch 6
C=1nF
Op-Amps: AD712 Switchs : 4066
Output production clock
Fig. 8. Backward translation map. This circuit samples the states of the Chua circuit and based on it produces the output.
the system, and observing and decoding the state of the chaotic system after evolution time to outputs of computation. To make this process robust, these orbits should not be allowed to enter to forbidden region. To implement this idea, we need a circuit to detect whether this computing orbit enters to forbidden region or not. In practice, we try different measures of the forbidden region, from 0 to 3, and found 1 as an appropriate and robust value for this measure, which makes the logic block robust in one side, and on the other side it is not so large that we miss most of the possible control inputs by allowing the system to enter forbidden region. Notice that this value depends on the test environment and implementation technology. The forbidden region is determined through two concurrent constraints: jv1j < 1 and 3.3v2 1 < v1 < 3.3 v2 + 1. Thus to implement this, one should check whether the computing orbit satisfy these constraints at least once in its evolution? If the orbit satisfies these constraints at least once, it shows that it has entered the forbidden region and hence this reconfigured or constructed gate is very sensitive to noise. Implementation of these two constraints is depicted in Fig. 9. This circuit is connected directly to v1 and v2 and the computing orbit is tracked and checked whether it enters into the forbidden region. The upper side of the circuit depicted in Fig. 9, determined by dashed line, detects the second constraint (3.3v2 1 < v1 < 3.3 v2 + 1), and lower part the first constraint (jv1j < 1). Then the results of these two constraints are fed to AND gate to find out when these two constraints are
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3.3k 1k
1v
V2
1v
−3.3v2 − 1 < v1 < −3.3v2 + 1
Output of robustness circuit
1v
C = 1nF
v1 〈1
Buffer
Op-Apms: AD712 And gate: 4082
1v
V1
Fig. 9. Robustness detection circuit is achieved by implementing two introduced concurrent constraints, determining forbidden region. This circuit detects whether computing orbits go to forbidden region or not.
satisfied together and hence the orbit is in the forbidden region. Notice this robustness detection circuit is not needed for computing operation of the logic block, here we used it just for detecting the stability of the instruction set and after determination of a robust instruction set, there is no need for this circuit. To derive the instruction set of this logic block that associates to each function one control input, we test the system with different control inputs. With each control input, we evaluate the system outputs under different data inputs. The results are shown in Table 3. During testing the logic block with different control inputs, whenever one of the computing orbits goes to the forbidden region, the output of robustness detection circuit, which is shown in Fig. 9, goes to 1. In this condition we neglect the currently utilized control input and try another control input. Each row in Table 3 represents one digital function. In each row, the bits in first field of the row from left to right represents the output when inputs
Table 3 Instruction set of logic block Function
Control input
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
1100011 1111000 1100010 1001001 1100110 0110111 0111000 0100001 1101101 1011110 0110110 1111011 0010101 1111010 1010101 1110000
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changes from 00 to 11 step by step (i.e., 00, 01, 10, 11), respectively. Actually they are different samples of the random space introduced in Eq. (3). The second column represents the corresponding digital control inputs. These records could be used as a lookup table during reconfiguration of the system. After this work, whenever a special two input one output digital function is needed one can then simply consult the lookup table and use the control inputs that robustly give the desired function. For example, to construct OR gate, use ‘‘0100001” as control input, to construct NAND gate use ‘‘1010101”. Note that reconfiguration takes place dynamically. This logic block requires three clocks as is shown in Fig. 2. These clocks are generated by a microcontroller. One instruction cycle of this constructed logic block is 0.002 s. To implement this logic block it is necessary to take in account some practical considerations. Hazard in logic design [14] is one of the most important considerations in designing digital systems. The cause of hazard is different timing delay of different components and paths in the circuit, which results in incorrect momentary changes in output of circuit [14]. In the constructed logic block, the hazard may occur in the robustness detection circuit. The duty of this circuit is to detect whether the computing orbit goes to forbidden region or not and this region has determined by two concurrent constraints. Hazard in robustness detection circuit disturbs the concurrency between these two constraints. To overcome this problem we make the signal transition time in different paths equal by adding some extra components. Another important subject is that this computing system is dynamics based, so anything that changes the dynamics of the system results in changes of the structure of computing system. As an example, if the utilized resistors differ from the given values, or other types of op-amps are used, then the dynamics of the system changes and the obtained instruction set will be different. But notice that the resultant instruction set for this new logic block is robust relative to its own logic block. When all logic blocks should have the same instruction set, more advanced technology, e.g. VLSI, should be used. Another practical consideration is integrating these different components of the logic block, e.g. forward and backward translation maps, Chua circuit, etc, in a system so that loading effects does not affect the behavior of these components. In our implementation, some buffers are inserted between these components to prevent such problems and keep the blocks electrically independent.
4. Conclusion To study the feasibility of chaotic flexible computing model, and also experimental verification of its flexibility, in this paper a Chua circuit based logic block was constructed and studied. This logic block can be controlled to morph between all 2 input, 1 output digital functions. The instruction set of this logic block was derived and presented in Table 3. This table can be used for dynamic reconfiguration of the constructed logic block. Also chaotic saddles are utilized to make the instruction set of the logic block robust with respect to noise. Chaotic saddles obtain through introduction of some forbidden gap around partition boundaries. Different sizes of forbidden regions (regions of sensitivity to noise) were tested and finally, the gap was fixed to the minimum value that keeps the instruction set of the logic block stable to noise. This achieved instruction set was tested more than hundreds to test the robustness of the instruction set to noise and always it was stable. The main purpose of this work is to demonstrate the construction of robust, analog reconfigurable chaotic logic blocks with discrete element electronics. However the presented logic block designs have not been optimized to reduce size and power consumption and to maximize speed but merely been constructed to demonstrate the proof of concept. More sophisticated VLSI designs are currently being pursued by us and others to obtain optimized VLSI components that are optimal for possible commercial applications.
Acknowledgement William Ditto would like to acknowledge the funding support of the Office of Naval Research [N000140211019] and of ChaoLogix Inc.
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