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Selective MLE growth of GaAs and surface treatment for ideal static induction transistor (ISIT) application
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AZ3 mm
applied surface science
__
ELSEVIER
Applied SurfaceScience 82/83 (1994) 41-45
Selective MLE growth of GaAs and surface treatment for ideal static induction transistor (ISIT) application Yutaka Oyama a,*, Piotr Plotka a, Jun-ichi Nishizawa b aSemiconductor Research Institute, Semiconductor Research Foundation, Kawauchi Aoba-ku, Sendai 980, Japan b Tohoku University, Katahira Aoba-ku, Sendai 980, Japan
Received2 May 1994; acceptedfor publication 9 July 1994
Abstract This paper reports the effects of low temperature surface treatment on the GaAs regrown interface quality prepared by photo-stimulated molecular layer epitaxy. The regrown diode characteristics are investigated as functions of treatment temperature, exposing ASH, pressure and duration. Optimized surface treatment gives a good regrown interface even at low temperatures of N 480°C compared with conventional high temperature treatment at N 600°C. The surface treatment mechanism is also discussed in combination with the results of X-ray photo-emission spectroscopy (XPS) and quadrupole mass analysis (QMS). Low temperature surface treatment is successfully applied to the ISIT fabrication with a channel length of 1800-100 A having a few monolayer p+ barrier layer thickness, which shows the DC transconductance g, as high as 1500 mS/mm with good reproducibility.
1. Introduction The surface just prior to epitaxial growth is the important factor to be controlled, because the epitaxial growth is based on the continuity of the crystal lattice between the substrate and the epitaxial layer. In addition, the external regrown gate and regrown contact layer with a good interface has been urgently required in the fabrication of mesoscopic semiconductor devices. Furthermore, high temperature processes cannot be applied especially to the III-V semiconductor devices with thin multi-layered structures due to its deviation from the stoichiometric composition and the degradation of the thin multilayers with atomic accuracy.
* Correspondingauthor. Fax: + 81 022 223 7289. 0169-4332/94/$07.00 0 1994 Elsevier Science B.V. All rights reserved SSDI 0169.4332(94)00195-2
Nishizawa et al. proposed the idea of the ideal static induction transistor (ISIT) [l] to achieve the tera-Herz operation, in which electrons transport in the crystal without collision with lattices. ISIT requires a multi-layered structure with atomic accuracy. Therefore, Nishizawa applied the idea of atomic layer epitaxy (ALE) after Suntola and co-workers [2] to form a GaAs mono-molecular layer [3] by the alternative injection of the source gases used in the field of MOCVD. Many methods on the surface cleaning process of GaAs have been reported. By the Auger analysis [4], it was already reported that the sulfuric acid-base etchant produces the Ga-rich GaAsO layer at the surface and the pile-up of arsenic was also observed at the interfacial region. It has been reported that the surface oxides can be removed by HF, HCl dipping [4], sulfur treatment [5] and so on. However, the
42
Y. Oyama et al. /Applied
Surface Science X2 / 83 (1994) 41-45
native oxide is required to be removed prior to epitaxial growth. Conventional surface treatment in vacuum is carried out at about 600°C. This may be related to the removal of a layer of GaAs-oxide from our results. However, it is shown that such high temperature treatment cannot be applied to the thin multi-layered structure. This paper reports the results of low temperature surface treatment suitable for the fabrication of mesoscopic semiconductor devices. Interface characteristics were investigated from the current-voltage (Z-V) characteristics of the regrown diodes prepared by the alternative injection of TEG/AsH, as functions of the treatment temperature, time and ASH, pressure. In view of the surface stoichiometry, the surface treatment mechanism is also discussed in combination with the XPS and QMS results. The present low temperature surface treatment is successfully applied to the formation of the external regrown gate of the homojunction gate ISIT. The basic performanc: of the ISIT with the channel length of 1800-100 A was also shown.
After the epitaxial process, non-alloyed Ti/Au metallization was made on the top p++ GaAs layer (p=6X1019 cm-j ) by the conventional lift-off process followed by the low temperature ozone-ashing procedure. Contact resistance achieved was y 2 X 10ph 0. cm-‘.
3. Results and discussion Fig. 1 shows the current-voltage (I-V) characteristics of the regrown GaAs pin diode. In Fig. 1, “hi _ temp” means that the surface treatment was carried out at 620°C under the ASH, pressure of 2 X lop4 Torr for 30 min. The “opt” means the optimized surface treatment condition. The “high _pres” is the surface treatment condition under the ASH, pressure of 1 X lo-’ Torr at 480°C for 30 min. “oo_AsH3” indicates the surface treatment condition without ASH, ambient at 480°C for 30 min. The I-V characteristics of “contin” was obtained by the continuously grown (not regrown) pin diode. MLE growth temperature was fixed to be 420°C in both samples. In view of the existence of the recombination centers in the depletion layer with
2. Experimental Regrown pin diodes were made by the photostimulated molecular layer epitaxy (PMLE) [6] on the chemically treated n-/n+ substrate material followed by pre-treatment in the ultra-high vacuum MLE chamber under various conditions of treatment. The n-/n+ GaAs crystals were commercially available made by the MOCVD method. In the inset of Fig. 1, a schematic drawing of the regrown pin diode structure is shown. epitaxial wafers were chemically The n-/n’ etched by the sulfuric acid-base etchant (H,SO, : H,O, : H,O = 90: 1: 1) followed by the HCl dipping for a few seconds. After drying the iso-propylalchohol (IPA), wafers were set into the loading chamber. The pin diodes were epitaxially regrown on the pre-treated n-/n’ epitaxial wafers by PMLE using TEG/AsH, as the precursors. DESe and DEZn were used for the donor and acceptor impurity source gases, respectively. The i-GaAs was intentionally undoped. Detailed description of the doping MLE is referred to elsewhere [7].
--*--
hi_temp
-opt ---+.---
hi_ptes
.-.. O---- no_AsHB ----t--contin
forward
voltage
[VI
Fig. 1. Current-voltage characteristics of the regrown GaAs pin diodes prepared by the photo-stimulated molecular layer epitaxy (PMLE). “hi temp” means that the surface treatment was carried out at 620°C under the ASH, pressure of 2X 10eJ Torr for 30 min. The “opt” means the optimized surface treatment condition. The “high_ pres” is the surface treatment condition under the ASH, pressure of 1 X lo-” Torr at 480°C for 30 min. “no ASH,” indicates the surface treatment condition without ASH, ambient at 480°C for 30 min. The I-V characteristics of “conrin” was obtained by the continuously grown (not regrown) pin diode. The substrate temperature for regrown is fixed to be 420°C.
Y. Oyama et al. /Applied Surface Science 82 / 83 (1994) 41-45
43
pAMa=2e-4 Torr 30 min.
are= 1.28-4
cm2
AsH3 pressure treatment temperature Fig. 2. Treatment temperature dependencies ward bias voltage I$* of the regrown C&As about the meaning of the value V**.
[OCI of the specific forpin diodes. See text
regrown interface, diode current at a specific forward voltage (Vf*) reflects the density of recombination centers. I$* is also important for our regrown gate construction of ISIT. Theoretical consideration on the diode characteristics with recombination centers at the regrown interface will be referred to elsewhere
[a. Fig. 2 shows the treatment temperature dependencies of the specific forward bias voltage V;“. The exposing ASH, pressure is kept to 2 X 10m4 Torr and the treatment time is 30 min. Vf* shows its maximum value at 480°C and this means that the high temperature treatment seems to degrade the regrown interface. As described later, XPS and QMS results show that the removal of an oxide layer requires high temperature ( N 600°C) treatment without AsH, in vacuum. Therefore, improvement of the regrown interface is induced not only by the removal of the oxide layer but by some other additional effects. Fig. 3 shows the change of V;” as a function of the AsH, pressure during surface treatment. Treatment temperature was 480 and 510°C. Surface treatment time is 30 min. At 48O”C, Vf* shows its maximum value at the AsH, pressure 8 X 10m4 Torr. It should be also noticed that the maximum V;” at 510°C is lower than that at 480°C. The existence of the optimum AsH, pressure to improve the regrown interface suggests that the interface characteristic is controlled not only by the removal of surface oxides but also by the surface stoichiometry.
[Torr]
Fig. 3. Change of V;” of the regrown GaAs pin diodes as a function of the exposing AsH, pressure during surface treatment. Treatment temperature was 480 and 510°C. Surface treatment time is 30 min.
Fig. 4 shows the treatment time dependencies of the specific forward voltage I$*. Exposing AsH, pressure was kept at 2 X 10m4 Torr. From Fig. 4, a higher treatment temperature requires a shorter treatment time. This result also suggests that the mechanism of the surface treatment is explained not only by the removal of the oxide layer but also the deviation from the surface stoichiometry, because it is expected that the longer treatment time and higher treatment temperature induce the removal of the oxide layer more completely. In order to investigate the mechanism of the low temperature surface treatment under AsH, exposure, thermal desorption spectroscopy (TDS) analysis was applied by the QMS equipment. Precise description of the QMS experimental setup is given elsewhere
goo!,,,,LtJzf~~A”~ . 0
60
120
180
time [min.] Fig. 4. Treatment time dependencies of the specific forward voltage I$* of the regrown GaAs pin diodes. Exposing ASH, pressure was kept at 2 X lo-’ Torr.
44
Y. Oyama et al. /Applied
Surface Science 82 /H3 (1994) 4I -4.5
[9]. TDS shows the desorption of Gal0 (154 amu at - 560°C and that of As,0 (166 amu at - 600°C in vacuum from the GaAs surface prepared by sulfuric acid-base etchant (H,SO, : H,O, : H,O = 90 : 1: 1) followed by the HCl dipping for 15 s. However, the surface which was heat-treated prior to the TDS at 510°C for 30 min under the ASH, pressure of 2 X 10-j Torr shows no desorption of oxides by the TDS measurements. This results in that the ASH, exposure induces the removal of oxides at lower treatment temperature. XPS measurements also confirmed these TDS results. XPS measurements detected the As, p3/2 and Ga, p312 signal on the chemically etched surface. These XPS signals were accompanied by the 2-3 eV higher energy sub-band which is considered to be formed from some oxides. After 510°C surface treatment without ASH, exposure, the XPS signal for the Ga oxide vanishes but that of the As oxide remains. However, the surface treatment with ASH, exposure annihilates both the Ga and the As oxides even at 510°C for 30 min. Detailed QMS and XPS results are shown in a separate paper [lo]. From these results, we consider that the mechanism of low temperature surface treatment is based not only on the removal of surface oxides but also on the deviation from the surface stoichiometry. From the TDS and the XPS results, the removal of surface oxides requires - 600°C surface treatment without ASH, exposure; and it is expected that the higher temperature and the higher ASH, pressure enhance the removal of surface oxides, because the ASH, exposure enables the removal of oxides at lower temperature. On the other hand, regrown diode experiments indicates the existence of the optimum treatment temperature and ASH, pressure, resulting in the surface treatment at higher temperature degrading the regrown interface quality. These results suggest that one of the most important factors to be controlled is the deviation from the surface stoichiometry. Low temperature surface treatment was successfully applied to the formation of the regrown external gate of ISIT. The channel leagth of the ISIT varied from 1800-100 A. 100 A channel length reaches to the similar value of the electron wavelength in GaAs. The mean free path of electrons in GaAs is about 1000 A. Therefore, the electron trans-
source p+gate
p++ cap
barrier
n+ drain Fig. 5. Schematic drawing of the cross-sectional homojunction gate GaAs ISIT.
view
of the
port mechanism will be the so-called ballistic one. Fig. 5 shows a schematic drawing of a cross-sectional view of the ISIT. In n-channel ISIT, the top nC-GaAs is the source and the bottom n’-GaAs acts as the drain. The p+-GaAs gate region at the sidewall, which acts as the gate, was epitaxially regrown under the present low temperature surface treatment conditions. The ISIT fabrication was carried out by the two epitaxial processes. At first, an npn structure was grown by the GaAs MLE on (lOO)-oriented n+GaAs:Si (n = 2 X 10” cm--‘) substrate using TEG/AsH, as precursors. Source gases for n- and p-type dopants used were DESe and DEZn, respectively. A heavily Zn-doped p+ layer in the npn sandwich structure forms the barrier to make an off-state in the transistor action. The p+ barrier layer thickness was controlled to be a few atomic layers so the barrier height as to be - 0.8 eV. The second epitaxial process is the regrowth for the external gate formation. Prior to the second epitaxial growth, the present low temperature surface treatment was applied. Conventional high temperature surface treatment induced the annihilation of barrier characteristics of the npn structure. The secondary ion mass spectroscopy (SIMS) measurements show that the barrier characteristics vanishes mainly due to the anomalous diffusion of Se from a heavily Se-doped source region to the pf-barrier layer with a few monolayer thickness. After surface treatment at 480°C with ASH, for 30 min, the n’/i/p+/p’+ external gate structure was epitaxially regrown selectively on the gate mesa region. In the present fabrication, a 5-MLE cycle was applied to form the nfchannel layer at the side-wall, which induces the
Y. Oyama et al. /Applied Surface Science 82 /83
(1994) 41-45
45
4. Conclusion
Fig. 6. Output characteristics of the C&As ISIT with external regrown homojunction gate. Source/drain distance and gate width are 1800 A and 100 pm, respectively. The p+ barrier layer thickness designed is 16 A,. The present low temperature surface treatment is applied to the formation of the external regrown gate region.
saddle point in the potential barrier. Therefore, the present ISIT is the pure edge transistor. A detailed description about the fabrication process will be shown in the cooperative paper [ll]. Fig. 6 shows the output characteristics of 1800 w ISIT with an external regrown homojunction gate with th,e source/drain distance and the gate width of 1800 A and 100 pm, respectively. Th,e p+ barrier layer thickness designed was 16 A. The DC transconductance g, obtained was as high as 1500 mS/mm at 1 A [Zn/Wl drain current density. However, the present value of g, was shown to be limited by the source and gate series resistance induced by the limitation of photolithography and contact resistance at present. After optimization of these problems, at least 10 times higher value of g, is expected. The low temptrature surface treatment was also applied to the 100 A ISIT fabrication. In 100 A ISIT, the thickness of the undoped spacer layer ketween the nf-source and p+-barrier layer was 20 A. Even in such a short source/drain distance, low temperature surface treatment at 480°C prevents the degradation of the npn barrier characteristics. It is expected that the MIS gate construction will greatly improve the device characteristics and the construction of the MIS gate on semi-insulating substrates will also improve the microwave performance; and the optimized surface treatment for regrown interface will be also valid for the MIS gate construction.
In conclusion, low temperature surface treatment suitable for the multi-thin layered structure device fabrication with atomic accuracy was investigated by means of the Z-V measurements of regrown diode characteristics. It was shown that the optimized surface treatment condition under the exposing ASH, improved the regrown interface quality even at lower treatment temperature compared with the conventional high temperature treatment condition. XPS and QMS results suggested that the mechanism of the surface treatment was based not only on the removal of surface oxides but also some other effect most probably the control of the deviation from the surface stoichiometry. Low temperature surface treatment condition with exposing AsH, was syccessfully applied to the short channel (1800-100 A) ISIT fabrication with a few mono-layered pf barrier layer thickness. Basic performance of the homojunction gate ISIT was shown and the extremely high DC transconductance g, of 1500 mS/mm was obtained at ID/W = 1 A. These results will be also valid on the MIS gate ISIT fabrication for superior microwave performance.
References [l] J. Nishizawa, T. Terasaki and J. Shibata, IEEE Trans. Electron Devices, ED-22(4) (1975) 185. 121 M. Ahonen, M. Pessa and T. Suntola, Thin Solid Films 6.5 (1980) 301. [3] J. Nishizawa, H. Abe and T. Kurabayashi, J. Electrochem. Sot. 132 (1983) 1197. [4] I. Shiota, K. Motoya, T. Ohmi, N. Miyamoto and J. Nishizawa, J. Electrochem. Sot. 124 (1976) 155. [s] J. Fan et al., Jpn. J. Appl. Phys. 27 (1988) L1331. [6] J. Nishizawa, H. Abe and T. Kurabayashi and N. Sakurai, J. Vat. Sci. Technol. A 4 (1986) 706. [7] J. Nishizawa, H. Abe and T. Kurabayashi, J. Electrochem. Sot. 136 (1989) 478. [8] J. Nishizawa and P. Plotka, unpublished. [9] J. Nishizawa, H. Sakuraba and Y. Oyama, Thin Solid Films 225 (1993) 1. [lo] J. Nishizawa and H. Sakuraba, unpublished. [ll] P. Plotka, T. Kurabayashi, Y. Oyama and J. Nishizawa, Appl. Surf. Sci. 82/83 (1994) 91.
AZ3 mm
applied surface science
__
ELSEVIER
Applied SurfaceScience 82/83 (1994) 41-45
Selective MLE growth of GaAs and surface treatment for ideal static induction transistor (ISIT) application Yutaka Oyama a,*, Piotr Plotka a, Jun-ichi Nishizawa b aSemiconductor Research Institute, Semiconductor Research Foundation, Kawauchi Aoba-ku, Sendai 980, Japan b Tohoku University, Katahira Aoba-ku, Sendai 980, Japan
Received2 May 1994; acceptedfor publication 9 July 1994
Abstract This paper reports the effects of low temperature surface treatment on the GaAs regrown interface quality prepared by photo-stimulated molecular layer epitaxy. The regrown diode characteristics are investigated as functions of treatment temperature, exposing ASH, pressure and duration. Optimized surface treatment gives a good regrown interface even at low temperatures of N 480°C compared with conventional high temperature treatment at N 600°C. The surface treatment mechanism is also discussed in combination with the results of X-ray photo-emission spectroscopy (XPS) and quadrupole mass analysis (QMS). Low temperature surface treatment is successfully applied to the ISIT fabrication with a channel length of 1800-100 A having a few monolayer p+ barrier layer thickness, which shows the DC transconductance g, as high as 1500 mS/mm with good reproducibility.
1. Introduction The surface just prior to epitaxial growth is the important factor to be controlled, because the epitaxial growth is based on the continuity of the crystal lattice between the substrate and the epitaxial layer. In addition, the external regrown gate and regrown contact layer with a good interface has been urgently required in the fabrication of mesoscopic semiconductor devices. Furthermore, high temperature processes cannot be applied especially to the III-V semiconductor devices with thin multi-layered structures due to its deviation from the stoichiometric composition and the degradation of the thin multilayers with atomic accuracy.
* Correspondingauthor. Fax: + 81 022 223 7289. 0169-4332/94/$07.00 0 1994 Elsevier Science B.V. All rights reserved SSDI 0169.4332(94)00195-2
Nishizawa et al. proposed the idea of the ideal static induction transistor (ISIT) [l] to achieve the tera-Herz operation, in which electrons transport in the crystal without collision with lattices. ISIT requires a multi-layered structure with atomic accuracy. Therefore, Nishizawa applied the idea of atomic layer epitaxy (ALE) after Suntola and co-workers [2] to form a GaAs mono-molecular layer [3] by the alternative injection of the source gases used in the field of MOCVD. Many methods on the surface cleaning process of GaAs have been reported. By the Auger analysis [4], it was already reported that the sulfuric acid-base etchant produces the Ga-rich GaAsO layer at the surface and the pile-up of arsenic was also observed at the interfacial region. It has been reported that the surface oxides can be removed by HF, HCl dipping [4], sulfur treatment [5] and so on. However, the
42
Y. Oyama et al. /Applied
Surface Science X2 / 83 (1994) 41-45
native oxide is required to be removed prior to epitaxial growth. Conventional surface treatment in vacuum is carried out at about 600°C. This may be related to the removal of a layer of GaAs-oxide from our results. However, it is shown that such high temperature treatment cannot be applied to the thin multi-layered structure. This paper reports the results of low temperature surface treatment suitable for the fabrication of mesoscopic semiconductor devices. Interface characteristics were investigated from the current-voltage (Z-V) characteristics of the regrown diodes prepared by the alternative injection of TEG/AsH, as functions of the treatment temperature, time and ASH, pressure. In view of the surface stoichiometry, the surface treatment mechanism is also discussed in combination with the XPS and QMS results. The present low temperature surface treatment is successfully applied to the formation of the external regrown gate of the homojunction gate ISIT. The basic performanc: of the ISIT with the channel length of 1800-100 A was also shown.
After the epitaxial process, non-alloyed Ti/Au metallization was made on the top p++ GaAs layer (p=6X1019 cm-j ) by the conventional lift-off process followed by the low temperature ozone-ashing procedure. Contact resistance achieved was y 2 X 10ph 0. cm-‘.
3. Results and discussion Fig. 1 shows the current-voltage (I-V) characteristics of the regrown GaAs pin diode. In Fig. 1, “hi _ temp” means that the surface treatment was carried out at 620°C under the ASH, pressure of 2 X lop4 Torr for 30 min. The “opt” means the optimized surface treatment condition. The “high _pres” is the surface treatment condition under the ASH, pressure of 1 X lo-’ Torr at 480°C for 30 min. “oo_AsH3” indicates the surface treatment condition without ASH, ambient at 480°C for 30 min. The I-V characteristics of “contin” was obtained by the continuously grown (not regrown) pin diode. MLE growth temperature was fixed to be 420°C in both samples. In view of the existence of the recombination centers in the depletion layer with
2. Experimental Regrown pin diodes were made by the photostimulated molecular layer epitaxy (PMLE) [6] on the chemically treated n-/n+ substrate material followed by pre-treatment in the ultra-high vacuum MLE chamber under various conditions of treatment. The n-/n+ GaAs crystals were commercially available made by the MOCVD method. In the inset of Fig. 1, a schematic drawing of the regrown pin diode structure is shown. epitaxial wafers were chemically The n-/n’ etched by the sulfuric acid-base etchant (H,SO, : H,O, : H,O = 90: 1: 1) followed by the HCl dipping for a few seconds. After drying the iso-propylalchohol (IPA), wafers were set into the loading chamber. The pin diodes were epitaxially regrown on the pre-treated n-/n’ epitaxial wafers by PMLE using TEG/AsH, as the precursors. DESe and DEZn were used for the donor and acceptor impurity source gases, respectively. The i-GaAs was intentionally undoped. Detailed description of the doping MLE is referred to elsewhere [7].
--*--
hi_temp
-opt ---+.---
hi_ptes
.-.. O---- no_AsHB ----t--contin
forward
voltage
[VI
Fig. 1. Current-voltage characteristics of the regrown GaAs pin diodes prepared by the photo-stimulated molecular layer epitaxy (PMLE). “hi temp” means that the surface treatment was carried out at 620°C under the ASH, pressure of 2X 10eJ Torr for 30 min. The “opt” means the optimized surface treatment condition. The “high_ pres” is the surface treatment condition under the ASH, pressure of 1 X lo-” Torr at 480°C for 30 min. “no ASH,” indicates the surface treatment condition without ASH, ambient at 480°C for 30 min. The I-V characteristics of “conrin” was obtained by the continuously grown (not regrown) pin diode. The substrate temperature for regrown is fixed to be 420°C.
Y. Oyama et al. /Applied Surface Science 82 / 83 (1994) 41-45
43
pAMa=2e-4 Torr 30 min.
are= 1.28-4
cm2
AsH3 pressure treatment temperature Fig. 2. Treatment temperature dependencies ward bias voltage I$* of the regrown C&As about the meaning of the value V**.
[OCI of the specific forpin diodes. See text
regrown interface, diode current at a specific forward voltage (Vf*) reflects the density of recombination centers. I$* is also important for our regrown gate construction of ISIT. Theoretical consideration on the diode characteristics with recombination centers at the regrown interface will be referred to elsewhere
[a. Fig. 2 shows the treatment temperature dependencies of the specific forward bias voltage V;“. The exposing ASH, pressure is kept to 2 X 10m4 Torr and the treatment time is 30 min. Vf* shows its maximum value at 480°C and this means that the high temperature treatment seems to degrade the regrown interface. As described later, XPS and QMS results show that the removal of an oxide layer requires high temperature ( N 600°C) treatment without AsH, in vacuum. Therefore, improvement of the regrown interface is induced not only by the removal of the oxide layer but by some other additional effects. Fig. 3 shows the change of V;” as a function of the AsH, pressure during surface treatment. Treatment temperature was 480 and 510°C. Surface treatment time is 30 min. At 48O”C, Vf* shows its maximum value at the AsH, pressure 8 X 10m4 Torr. It should be also noticed that the maximum V;” at 510°C is lower than that at 480°C. The existence of the optimum AsH, pressure to improve the regrown interface suggests that the interface characteristic is controlled not only by the removal of surface oxides but also by the surface stoichiometry.
[Torr]
Fig. 3. Change of V;” of the regrown GaAs pin diodes as a function of the exposing AsH, pressure during surface treatment. Treatment temperature was 480 and 510°C. Surface treatment time is 30 min.
Fig. 4 shows the treatment time dependencies of the specific forward voltage I$*. Exposing AsH, pressure was kept at 2 X 10m4 Torr. From Fig. 4, a higher treatment temperature requires a shorter treatment time. This result also suggests that the mechanism of the surface treatment is explained not only by the removal of the oxide layer but also the deviation from the surface stoichiometry, because it is expected that the longer treatment time and higher treatment temperature induce the removal of the oxide layer more completely. In order to investigate the mechanism of the low temperature surface treatment under AsH, exposure, thermal desorption spectroscopy (TDS) analysis was applied by the QMS equipment. Precise description of the QMS experimental setup is given elsewhere
goo!,,,,LtJzf~~A”~ . 0
60
120
180
time [min.] Fig. 4. Treatment time dependencies of the specific forward voltage I$* of the regrown GaAs pin diodes. Exposing ASH, pressure was kept at 2 X lo-’ Torr.
44
Y. Oyama et al. /Applied
Surface Science 82 /H3 (1994) 4I -4.5
[9]. TDS shows the desorption of Gal0 (154 amu at - 560°C and that of As,0 (166 amu at - 600°C in vacuum from the GaAs surface prepared by sulfuric acid-base etchant (H,SO, : H,O, : H,O = 90 : 1: 1) followed by the HCl dipping for 15 s. However, the surface which was heat-treated prior to the TDS at 510°C for 30 min under the ASH, pressure of 2 X 10-j Torr shows no desorption of oxides by the TDS measurements. This results in that the ASH, exposure induces the removal of oxides at lower treatment temperature. XPS measurements also confirmed these TDS results. XPS measurements detected the As, p3/2 and Ga, p312 signal on the chemically etched surface. These XPS signals were accompanied by the 2-3 eV higher energy sub-band which is considered to be formed from some oxides. After 510°C surface treatment without ASH, exposure, the XPS signal for the Ga oxide vanishes but that of the As oxide remains. However, the surface treatment with ASH, exposure annihilates both the Ga and the As oxides even at 510°C for 30 min. Detailed QMS and XPS results are shown in a separate paper [lo]. From these results, we consider that the mechanism of low temperature surface treatment is based not only on the removal of surface oxides but also on the deviation from the surface stoichiometry. From the TDS and the XPS results, the removal of surface oxides requires - 600°C surface treatment without ASH, exposure; and it is expected that the higher temperature and the higher ASH, pressure enhance the removal of surface oxides, because the ASH, exposure enables the removal of oxides at lower temperature. On the other hand, regrown diode experiments indicates the existence of the optimum treatment temperature and ASH, pressure, resulting in the surface treatment at higher temperature degrading the regrown interface quality. These results suggest that one of the most important factors to be controlled is the deviation from the surface stoichiometry. Low temperature surface treatment was successfully applied to the formation of the regrown external gate of ISIT. The channel leagth of the ISIT varied from 1800-100 A. 100 A channel length reaches to the similar value of the electron wavelength in GaAs. The mean free path of electrons in GaAs is about 1000 A. Therefore, the electron trans-
source p+gate
p++ cap
barrier
n+ drain Fig. 5. Schematic drawing of the cross-sectional homojunction gate GaAs ISIT.
view
of the
port mechanism will be the so-called ballistic one. Fig. 5 shows a schematic drawing of a cross-sectional view of the ISIT. In n-channel ISIT, the top nC-GaAs is the source and the bottom n’-GaAs acts as the drain. The p+-GaAs gate region at the sidewall, which acts as the gate, was epitaxially regrown under the present low temperature surface treatment conditions. The ISIT fabrication was carried out by the two epitaxial processes. At first, an npn structure was grown by the GaAs MLE on (lOO)-oriented n+GaAs:Si (n = 2 X 10” cm--‘) substrate using TEG/AsH, as precursors. Source gases for n- and p-type dopants used were DESe and DEZn, respectively. A heavily Zn-doped p+ layer in the npn sandwich structure forms the barrier to make an off-state in the transistor action. The p+ barrier layer thickness was controlled to be a few atomic layers so the barrier height as to be - 0.8 eV. The second epitaxial process is the regrowth for the external gate formation. Prior to the second epitaxial growth, the present low temperature surface treatment was applied. Conventional high temperature surface treatment induced the annihilation of barrier characteristics of the npn structure. The secondary ion mass spectroscopy (SIMS) measurements show that the barrier characteristics vanishes mainly due to the anomalous diffusion of Se from a heavily Se-doped source region to the pf-barrier layer with a few monolayer thickness. After surface treatment at 480°C with ASH, for 30 min, the n’/i/p+/p’+ external gate structure was epitaxially regrown selectively on the gate mesa region. In the present fabrication, a 5-MLE cycle was applied to form the nfchannel layer at the side-wall, which induces the
Y. Oyama et al. /Applied Surface Science 82 /83
(1994) 41-45
45
4. Conclusion
Fig. 6. Output characteristics of the C&As ISIT with external regrown homojunction gate. Source/drain distance and gate width are 1800 A and 100 pm, respectively. The p+ barrier layer thickness designed is 16 A,. The present low temperature surface treatment is applied to the formation of the external regrown gate region.
saddle point in the potential barrier. Therefore, the present ISIT is the pure edge transistor. A detailed description about the fabrication process will be shown in the cooperative paper [ll]. Fig. 6 shows the output characteristics of 1800 w ISIT with an external regrown homojunction gate with th,e source/drain distance and the gate width of 1800 A and 100 pm, respectively. Th,e p+ barrier layer thickness designed was 16 A. The DC transconductance g, obtained was as high as 1500 mS/mm at 1 A [Zn/Wl drain current density. However, the present value of g, was shown to be limited by the source and gate series resistance induced by the limitation of photolithography and contact resistance at present. After optimization of these problems, at least 10 times higher value of g, is expected. The low temptrature surface treatment was also applied to the 100 A ISIT fabrication. In 100 A ISIT, the thickness of the undoped spacer layer ketween the nf-source and p+-barrier layer was 20 A. Even in such a short source/drain distance, low temperature surface treatment at 480°C prevents the degradation of the npn barrier characteristics. It is expected that the MIS gate construction will greatly improve the device characteristics and the construction of the MIS gate on semi-insulating substrates will also improve the microwave performance; and the optimized surface treatment for regrown interface will be also valid for the MIS gate construction.
In conclusion, low temperature surface treatment suitable for the multi-thin layered structure device fabrication with atomic accuracy was investigated by means of the Z-V measurements of regrown diode characteristics. It was shown that the optimized surface treatment condition under the exposing ASH, improved the regrown interface quality even at lower treatment temperature compared with the conventional high temperature treatment condition. XPS and QMS results suggested that the mechanism of the surface treatment was based not only on the removal of surface oxides but also some other effect most probably the control of the deviation from the surface stoichiometry. Low temperature surface treatment condition with exposing AsH, was syccessfully applied to the short channel (1800-100 A) ISIT fabrication with a few mono-layered pf barrier layer thickness. Basic performance of the homojunction gate ISIT was shown and the extremely high DC transconductance g, of 1500 mS/mm was obtained at ID/W = 1 A. These results will be also valid on the MIS gate ISIT fabrication for superior microwave performance.
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