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YSPICE—a statistical optimization program for analog integrated circuits
World Abstracts on Microelectronics and Reliability technology and the other is for large die with very high input/ output lead counts. These two potential applications are reviewed with particular emphasis on high performance large die with high lead counts. The work of the ASTM ad hoc committee on TAB is described. Problems and alternative methods of interconnection are discussed and trends for the further use of TAB technology are outlined.
1195
eSligllgltl~ PAUL COX, PING YANG, S. S. MAHANT-SHETTI
and PALLAB CHATrERJEE. Solid St. Technol., 154 (August 1985). The VLSI design for volume manufacture requires that accurate device models be available for circuit simulation. It is also imperative that process induced statistical variations of device model parameters be characterized and their effect on circuit performance be predicted. An automated system has been developed to measure the l - V Developing a working mix-and-match lithography system. curves for MOS devices and extract SPICE model JOHN LENT. Semiconductor int., 146 (September 1985). The parameters. This system has been used to characterize a large problems and successes of matching 1X steppers with number of test devices and to obtain statistical information sc.anners. on device model parameters. Variations in device length, width, oxide capacitance and flat band voltage have been Test software development. PETERH. SINGER.Semiconductor shown to be the principal process factors responsible for the int., 76 (September 1985). Test vectors generated during statistical variation of device characteristics. A consistent design verification on CAE systems could potentially be used model has been developed to estimate changes in the device for final test program development, but ATE limitations model parameters as functions of these principal factors. This must be considered. statistical model permits an efficient estimate of the range of circuit performance with a minimum of circuit simulations. The analysis of intersections in sets of polygonal lines for SPYE, a program for Statistical Parametric Yield integrated circuit layout design. LECH MATUSZEWSKI. Estimation, has been developed to accurately predict the Electron Technol., Warsaw 15(1/2), 19 (1982). The algorithm parametric yield of a circuit design or for statistical parafor the analysis of graphical systems composed of polygonal metric specification of standard cells. Predicted performance lines is presented. It produces the data structure describing a variations from SPYE are compared with measured varipicture as a graph embedded within the plane. In the course ations in delay and power consumption for a 7000 gate of the analysis all intersections of lines are efficiently found. NMOS inverter chain. Considering some topological and geometrical properties, update. PIETER BURGGRAAF. reflected in the data structure, allowed to reduce the number Multiinyer resist p ~ of cases in which the intersection condition for a pair of Semiconductor int., 88 (August 1985). Multilayer resist techniques are part of the wafer process arsenal, yet little use segments has to be solved. of these high resolution schemes is found in production. Hierarchical system for layout design and checkin~, ROMAN Materials and processes for manometer lithography. S. JELDNEK.Electron Technol., Warsaw 17(I/2), 89 (1984). The MACKIEand S. P. BEAUMONT.Solid St. Technol., 117 (August hierarchical system for layout design and checking is 1985). Nanolithography is the science of fabrication of strucpresented. The properties of data bases and input languages tures with dimensions below 0.1 microns. Several tools exist are described. They include the layout description language for the purpose, including focused electron beams, focused and the scheme description language which are closely ion beams, and x-ray contact printing. Of these, the focused connected with the organization of checking programs. electron beam is the most widely used and the most highly Checking is divided into three parts: global geometrical developed. A nanolithography process is described using a checking, local geometrical checking and electrical checking. focused electron beam and lift-off, which has the ability to The functions of each of the checking programs are briefly fabricate metal features with 10nm minimum dimensions. discussed. More detailed information is presented in separate Applications for ultrasmall structures include scaling papers. The system is intended for implementation on miniconventional devices to their limits, and fabricating novel computers. The presented approach does not depend upon devices utilising the physics of the very small. the technology, in which the integrated circuit is designed. Approuehes to resists for two-level RIE pattern transfer appliLithegraphy for nltrm-mdmtkrou device smmtures. CHARLES cations. E. REICHMANIS,G. SMOLINSKYand C. W. WILKINSJR. F. COOK JR, TtlOu.~s F. Aucon~ and GERALD J. IAVRA~. Solid St. Technol., 130 (August 1985). Planarization is rapidly Solid St. Technol., 125 (October 1985). New ultra-small becoming a required technology in integrated circuit manudevices such as quantum-well arrays and metal grid radiators, facture. Wafer topography and surface reflectivity problems fabricated from gallium arsenide and its alloys, promise high limit the use of single level resists and have prompted the speed transport, picosecond switching, and millimeter wave development of numerous two- and three-level resist prooscillations for future microelectronic applications. Some of cesses. This review describes current attempts to develop these structures exploit multi-dimensional electron confine- radiation-sensitive oxygen-RIE (Reactive Ion Etching) ment and, as such, require molecular beam epitaxy or resistant materials that can serve as both the imaging layer metallo-organic chemical vapor deposition and ultraand etching barrier for two-level processes employing RIEsubmicron lithography to obtain the requisite hyperabrupt pattern-transfer techniques. A discussion of the materials and interfaces and feature sizes to 200A. One area critical to the their properties is included. fabrication of these structures is the high-resolution lithoYSPICE--a statistical optimization program for analog graphy required to write such small patterns. At the present integrated circuits. WZTOLD STRASZ. Electron Technol., time, there are at least three viable approaches: commercial Warsaw 14(3/4), 151 (1981). This paper presents a computer high resolution e-beam lithography systems, modified program YSPICE that is a design aid for integrated circuits. scanning electron microscopes, or modified scanning transThe program combines Monte Carlo analysis together with mission electron microscopes (STEM). The modification and the simulation of the circuit d.c. operating point and its use of a Phillips EM 420T STEM to generate ultra-small frequency domain characteristics. Parts of the existing device structures is described. SPICE program were used. The Monte Carlo method enables estimation of the production yield and design Treads in resist design and use. PETER H. SINGER. Semiconductor int., 68 (August 1985). Factors driving the develop- centering, i.e. optimum selection of the parameter nominal values. The optimization method used is based upon first and ment of new resist designs include the need for improved second derivatives. The program YSPICE features a simple resolution, photospeed, etch resistance and thermal stability. input language and the built-in statistical models of Statistical device characterization and parametric yield integrated resistors, capacitors and bipolar transistors. MR
26:6-M
1195
eSligllgltl~ PAUL COX, PING YANG, S. S. MAHANT-SHETTI
and PALLAB CHATrERJEE. Solid St. Technol., 154 (August 1985). The VLSI design for volume manufacture requires that accurate device models be available for circuit simulation. It is also imperative that process induced statistical variations of device model parameters be characterized and their effect on circuit performance be predicted. An automated system has been developed to measure the l - V Developing a working mix-and-match lithography system. curves for MOS devices and extract SPICE model JOHN LENT. Semiconductor int., 146 (September 1985). The parameters. This system has been used to characterize a large problems and successes of matching 1X steppers with number of test devices and to obtain statistical information sc.anners. on device model parameters. Variations in device length, width, oxide capacitance and flat band voltage have been Test software development. PETERH. SINGER.Semiconductor shown to be the principal process factors responsible for the int., 76 (September 1985). Test vectors generated during statistical variation of device characteristics. A consistent design verification on CAE systems could potentially be used model has been developed to estimate changes in the device for final test program development, but ATE limitations model parameters as functions of these principal factors. This must be considered. statistical model permits an efficient estimate of the range of circuit performance with a minimum of circuit simulations. The analysis of intersections in sets of polygonal lines for SPYE, a program for Statistical Parametric Yield integrated circuit layout design. LECH MATUSZEWSKI. Estimation, has been developed to accurately predict the Electron Technol., Warsaw 15(1/2), 19 (1982). The algorithm parametric yield of a circuit design or for statistical parafor the analysis of graphical systems composed of polygonal metric specification of standard cells. Predicted performance lines is presented. It produces the data structure describing a variations from SPYE are compared with measured varipicture as a graph embedded within the plane. In the course ations in delay and power consumption for a 7000 gate of the analysis all intersections of lines are efficiently found. NMOS inverter chain. Considering some topological and geometrical properties, update. PIETER BURGGRAAF. reflected in the data structure, allowed to reduce the number Multiinyer resist p ~ of cases in which the intersection condition for a pair of Semiconductor int., 88 (August 1985). Multilayer resist techniques are part of the wafer process arsenal, yet little use segments has to be solved. of these high resolution schemes is found in production. Hierarchical system for layout design and checkin~, ROMAN Materials and processes for manometer lithography. S. JELDNEK.Electron Technol., Warsaw 17(I/2), 89 (1984). The MACKIEand S. P. BEAUMONT.Solid St. Technol., 117 (August hierarchical system for layout design and checking is 1985). Nanolithography is the science of fabrication of strucpresented. The properties of data bases and input languages tures with dimensions below 0.1 microns. Several tools exist are described. They include the layout description language for the purpose, including focused electron beams, focused and the scheme description language which are closely ion beams, and x-ray contact printing. Of these, the focused connected with the organization of checking programs. electron beam is the most widely used and the most highly Checking is divided into three parts: global geometrical developed. A nanolithography process is described using a checking, local geometrical checking and electrical checking. focused electron beam and lift-off, which has the ability to The functions of each of the checking programs are briefly fabricate metal features with 10nm minimum dimensions. discussed. More detailed information is presented in separate Applications for ultrasmall structures include scaling papers. The system is intended for implementation on miniconventional devices to their limits, and fabricating novel computers. The presented approach does not depend upon devices utilising the physics of the very small. the technology, in which the integrated circuit is designed. Approuehes to resists for two-level RIE pattern transfer appliLithegraphy for nltrm-mdmtkrou device smmtures. CHARLES cations. E. REICHMANIS,G. SMOLINSKYand C. W. WILKINSJR. F. COOK JR, TtlOu.~s F. Aucon~ and GERALD J. IAVRA~. Solid St. Technol., 130 (August 1985). Planarization is rapidly Solid St. Technol., 125 (October 1985). New ultra-small becoming a required technology in integrated circuit manudevices such as quantum-well arrays and metal grid radiators, facture. Wafer topography and surface reflectivity problems fabricated from gallium arsenide and its alloys, promise high limit the use of single level resists and have prompted the speed transport, picosecond switching, and millimeter wave development of numerous two- and three-level resist prooscillations for future microelectronic applications. Some of cesses. This review describes current attempts to develop these structures exploit multi-dimensional electron confine- radiation-sensitive oxygen-RIE (Reactive Ion Etching) ment and, as such, require molecular beam epitaxy or resistant materials that can serve as both the imaging layer metallo-organic chemical vapor deposition and ultraand etching barrier for two-level processes employing RIEsubmicron lithography to obtain the requisite hyperabrupt pattern-transfer techniques. A discussion of the materials and interfaces and feature sizes to 200A. One area critical to the their properties is included. fabrication of these structures is the high-resolution lithoYSPICE--a statistical optimization program for analog graphy required to write such small patterns. At the present integrated circuits. WZTOLD STRASZ. Electron Technol., time, there are at least three viable approaches: commercial Warsaw 14(3/4), 151 (1981). This paper presents a computer high resolution e-beam lithography systems, modified program YSPICE that is a design aid for integrated circuits. scanning electron microscopes, or modified scanning transThe program combines Monte Carlo analysis together with mission electron microscopes (STEM). The modification and the simulation of the circuit d.c. operating point and its use of a Phillips EM 420T STEM to generate ultra-small frequency domain characteristics. Parts of the existing device structures is described. SPICE program were used. The Monte Carlo method enables estimation of the production yield and design Treads in resist design and use. PETER H. SINGER. Semiconductor int., 68 (August 1985). Factors driving the develop- centering, i.e. optimum selection of the parameter nominal values. The optimization method used is based upon first and ment of new resist designs include the need for improved second derivatives. The program YSPICE features a simple resolution, photospeed, etch resistance and thermal stability. input language and the built-in statistical models of Statistical device characterization and parametric yield integrated resistors, capacitors and bipolar transistors. MR
26:6-M