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4479297 Method of fabricating three-dimensional semiconductor devices utilizing CeO2 and ion-implantation
Microelectron. Reliab., Vol. 25, No. 6, pp. 1175-1176, 1985.
0026-2714/85S3.00+.00 Pergamon Press Ltd.
Printed in Great Britain.
NEW PATENTS This Section contains abstracts and, where appropriate, illustrations of recently issued United States patents and published patent applications filed from over 30 countries under the Patent Cooperation Treaty. This information was obtained from recent additions to the Pergamon PATSEARCH~ online database in accordance with interest profiles developed by the Editors. Further information about Pergamon PATSEARCH® can be obtained from Pergamon InfoLine Inc., 1340 Old Chain Bridge Road, McLean, Virginia 22101 U.S.A.
Copies of complete patents announced in this Section are available from Pergamon InfoLine Inc. for $8 per copy. Payment with order is required. Orders outside North America add $2 for air postage. Order by patent number for Pergamon InfoLine only.
4479297
4480199
METHOD OF FABRICATING THREE-DIMENSIONAL SEMICONDUCTOR DEVICES UTILIZING CEO2 AND IONIMPLANTATION.
IDENTIFICATION INTEGRATED
Ramesh C Varshney, Robert Strain assigned to Fairchild Camera & Instrument Corp
Yoshihisa Mizutani, Shinichiro Takasu, Tokyo, Japan assigned to Tokyo Shibaura Denki Kabushiki Kaisha
FI
~""'
;
10
"-TTLP,n
A circuit for providing an identification signal indicative of whether or not an integrated circuit has been repaired includes a circuit which operates at potentials outside the normal range of the integrated circuit. The circuit includes at least one transistor T1 serially connected between a TTL pin l0 of the integrated circuit and a fuse F1. The fuse F1 is also connected to a potential source VCC. If the integrated circuit is repaired the fuse F1 is opened, and consequently, application of a potential outside the normal range will cause current to flow if fuse F1 has not been opened, and cause no current to flow if fuse F1 has been opened.
A method for fabricating a three-dimensional multi-layer integrated circuit of single crystalline CeO2 and Si is proposed. This method is characterized in that a single crystalline CeO2 insulation layer, or the like, is formed on a single crystalline Si substrate. An isolation region is formed in the single crystalline Si substrate. The region is transformed into a SiO2 insulation layer by selectively introducing oxygen ions through the single crystalline CeO2 insulation layer and reacting the oxygen ions with the single crystalline Si. An epitaxial growth single crystalline Si layer is formed on the single crystalline CeO2 insulation layer. Predetermined processes, such as forming a single crystalline CeO2 layer, are performed thereafter to form the threedimensional structures of semiconductor elements such as MOS transistors and bipolar transistors with high packing density and reliability. sx 25:6-~
OF REPAIRED CIRCUITS
4481628 APPARATUS FOR TESTING DYNAMIC NOISE IMMUNITY OF DIGITAL INTEGRATED CIRCUITS Rossan Pasquinelli, Sesto S Giovanni, Italy assigned to Honeywell Information Systems Inc Apparatus for testing dynamic noise immunity of digital integrated circuits wherein noise pulses 1175
0026-2714/85S3.00+.00 Pergamon Press Ltd.
Printed in Great Britain.
NEW PATENTS This Section contains abstracts and, where appropriate, illustrations of recently issued United States patents and published patent applications filed from over 30 countries under the Patent Cooperation Treaty. This information was obtained from recent additions to the Pergamon PATSEARCH~ online database in accordance with interest profiles developed by the Editors. Further information about Pergamon PATSEARCH® can be obtained from Pergamon InfoLine Inc., 1340 Old Chain Bridge Road, McLean, Virginia 22101 U.S.A.
Copies of complete patents announced in this Section are available from Pergamon InfoLine Inc. for $8 per copy. Payment with order is required. Orders outside North America add $2 for air postage. Order by patent number for Pergamon InfoLine only.
4479297
4480199
METHOD OF FABRICATING THREE-DIMENSIONAL SEMICONDUCTOR DEVICES UTILIZING CEO2 AND IONIMPLANTATION.
IDENTIFICATION INTEGRATED
Ramesh C Varshney, Robert Strain assigned to Fairchild Camera & Instrument Corp
Yoshihisa Mizutani, Shinichiro Takasu, Tokyo, Japan assigned to Tokyo Shibaura Denki Kabushiki Kaisha
FI
~""'
;
10
"-TTLP,n
A circuit for providing an identification signal indicative of whether or not an integrated circuit has been repaired includes a circuit which operates at potentials outside the normal range of the integrated circuit. The circuit includes at least one transistor T1 serially connected between a TTL pin l0 of the integrated circuit and a fuse F1. The fuse F1 is also connected to a potential source VCC. If the integrated circuit is repaired the fuse F1 is opened, and consequently, application of a potential outside the normal range will cause current to flow if fuse F1 has not been opened, and cause no current to flow if fuse F1 has been opened.
A method for fabricating a three-dimensional multi-layer integrated circuit of single crystalline CeO2 and Si is proposed. This method is characterized in that a single crystalline CeO2 insulation layer, or the like, is formed on a single crystalline Si substrate. An isolation region is formed in the single crystalline Si substrate. The region is transformed into a SiO2 insulation layer by selectively introducing oxygen ions through the single crystalline CeO2 insulation layer and reacting the oxygen ions with the single crystalline Si. An epitaxial growth single crystalline Si layer is formed on the single crystalline CeO2 insulation layer. Predetermined processes, such as forming a single crystalline CeO2 layer, are performed thereafter to form the threedimensional structures of semiconductor elements such as MOS transistors and bipolar transistors with high packing density and reliability. sx 25:6-~
OF REPAIRED CIRCUITS
4481628 APPARATUS FOR TESTING DYNAMIC NOISE IMMUNITY OF DIGITAL INTEGRATED CIRCUITS Rossan Pasquinelli, Sesto S Giovanni, Italy assigned to Honeywell Information Systems Inc Apparatus for testing dynamic noise immunity of digital integrated circuits wherein noise pulses 1175