A closed-form trapped-charge-included drain current compact model for amorphous oxide semiconductor thin-film transistors

Microelectronics Reliability xxx (xxxx) xxx–xxx

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A closed-form trapped-charge-included drain current compact model for amorphous oxide semiconductor thin-film transistors ⁎

Fei Yua, , Chuanzhong Xua, Gongyi Huanga, Wei Lina, Tsair-Chun Liangb a b

College of Information Science and Engineering, Huaqiao University, Xiamen 361021, China Graduate Institute of Electrical Engineering, National Kaohsiung First University of Science and Technology, Taiwan

A R T I C L E I N F O

A B S T R A C T

Keywords: Amorphous oxide semiconductor (AOS) Thin film transistors (TFTs) Drain current model

A closed-form drain current compact model for amorphous oxide semiconductor (AOS) thin-film transistors (TFTs), including the influence from trapped charges, is presented in this paper. Accounting for both channel and interface trapped charges in this model, we explicitly solve the inherent closed-form surface potential by improving the computational efficiency of the effective charge density approach. Furthermore, based on the explicit solution of the surface potential, the expressions of the trapped and inversion charges in the channel film are derived analytically, and the drain current is integrated from the charge sheet model. Then, for the cases of the different operational voltages, the accuracy and practicability of our model are verified by numerical results of the surface potential and experimental data of the drain current in amorphous In-Ga-Zn-O TFTs, respectively. Finally, we give a discussion about the influence of the interface trapped charges on the device reliability. As a result, the model can be easily to explore the drain current behavior of the AOS TFTs for next-generation display circuit application.

1. Introduction Amorphous Oxide Semiconductor (AOS) Thin-Film Transistors (TFTs) [1] in various types of wide bandgap devices, especially amorphous In-Ga-Zn-O (a-IGZO) TFTs [2], are under development for nextgeneration applications of display [3], sensor [4], memory [5], and so on. In order to design high performance circuits for the above applications using AOS TFTs, it is mandatory to propose a physics-based and feasible drain current compact model. Here, amorphous channel in AOS TFTs introduces a key difficulty that trapped charges in the channel [6] and at the gate-dielectric/channel interface [7,8] affect the subthreshold current degradation. Recent literatures [6,9–14] have modeled the drain current of the AOS TFTs, but none of them has considered the effect of interface-trapped-charge on the subthreshold current. M. Ghittorelli et al. [9], Z. Zong et al. [10], and J. Fang et al. [11] ignored the acceptor-like deep trap states in the channel. M. Bae et al. [12], A. Tsormpatzoglou et al. [13], and F. Yu et al. [6] developed DC models of AOS TFTs with the energy-dependent acceptor-like deep trap states through regional approach so that there is a smoothing parameter without clear physics meaning in the smoothing function which is used to connect the simulation results in the different regions. W. Deng et al. [14] gave a closed-form model for a-IGZO TFTs, but the above-mentioned smoothing function is still necessary in the model.

⁎

In this paper, by accounting for the effects of interface trapped charges and channel acceptor-like trap states on the 1-D Poisson's equation, we propose an inherent closed-form surface-potential-based drain current compact model of AOS TFTs by improving the effective charge density approach and adopting the charge sheet model. Our model can accurately reproduce surface potential and drain current characteristics in both sub- and above- threshold regions, respectively, by using a single-piece equation. The modeling results show good agreements with surface potential numerical iteration results and measured drain current characteristics in a wide range of gate and drain voltages. Therefore, this model can be implemented into circuit simulators to predict direct current (DC) properties of AOS TFTs, and especially suitable to explore the sub- and above-threshold current degradation owing to trapped charges for the AOS TFT reliability. 2. Trapped charge interpretation TFTs are three terminal field-effect devices, which are typically fabricated on insulating substrates, like glass or plastic. In fact, AOS TFT channel layers, known as good transparent conducting oxides (such as ZnO [15,16], SnO2 [17], ZnInO [18], and InGaZnO [2,19], etc.), are grown at low temperature from room temperature to > 300 °C in crystalline, poly-crystalline, or amorphous phase by using vacuum- or

Corresponding author. E-mail addresses: [email protected], [email protected] (F. Yu).

https://doi.org/10.1016/j.microrel.2018.02.004 Received 26 October 2017; Received in revised form 21 December 2017; Accepted 5 February 2018 0026-2714/ © 2018 Elsevier Ltd. All rights reserved.

Please cite this article as: Yu, F., Microelectronics Reliability (2018), https://doi.org/10.1016/j.microrel.2018.02.004

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Dit (E ) = gat exp ⎛ ⎝

⎜

E − Ec ⎞ E − Ec ⎞ + gad exp ⎛ + Df . Eat ⎠ ⎝ Ead ⎠ ⎟

⎜

⎟

(4)

Substituting Eq. (4) into Eq. (3), we can obtain the trapped charge density Ntrap as

φ − Vch ⎞ ⎛ φ − Vch ⎟⎞ Ntrap = nat exp ⎜⎛ ⎟ + nad exp ⎜ / E q ⎝ at ⎠ ⎝ Ead/ q ⎠ ⎧ ⎡ 1 + exp ⎪ + Df Eg − kT ln ⎢ ⎢ 1 + exp ⎨ ⎪ ⎢ ⎣ ⎩

( (

) ⎤⎥ ⎫⎪. ) ⎥⎥⎦ ⎬⎪⎭

Ec − Ef − qφ kT Ev − Ef − qφ kT

(5)

The processes of the integrating Eq. (3) were demonstrated in Refs

( ) −E

πkT

[22,23]. On the one hand, nat = gat ⎡ sin (πkT / E ) ⎤ exp E c [22] when at ⎦ at ⎣ πkT −E Eat > qVt, nad = gad ⎡ sin (πkT / E ) ⎤ exp E c [22] when Ead > qVt, gat ad ⎦ ad ⎣ and gad are densities of tail and deep trap states at Ec, Eat and Ead are the inverse slopes of tail and deep trap states, respectively. On the other hand, the result of the integration of the interface trap states Df is shown in the third term [23] of the right hand side (RHS) in Eq. (5).

( )

Fig. 1. Typical device structure of AOS TFTs.

solution-processing deposition techniques. It is noted that AOS TFTs are characterized by a reduced sub-threshold current due to trapped charges compared with crystalline oxide semiconductor and Si transistors. From configuration aspect, most peculiar planar AOS TFTs are bottom-gate (BG) inverted staggered etch-stopper structure [20], which is simplified and shown in Fig. 1. Following the gradual channel approximation, we considered both tail and deep acceptor-like trap densities of states in the channel and uniform trapped charge density at the gate-dielectric/channel interface in the 1-D Poisson's equation of AOS TFTs, i.e.,

According to Eqs. (1), (2), and (3), we can observe that the expression of the total charge density in the channel of AOS TFTs is so complicated that φ cannot be solved analytically from Eq. (1). However, the 1-D Poisson's equation of crystalline oxide semiconductor TFTs is simpler than that of AOS TFTs in mathematical formulation, i.e.,

d 2φ q (Nfree + Ntrap). = dx 2 εAOS

φ − Vch ⎞ d 2φ q n 0 exp ⎛ = , dx 2 εAOS ⎝ Vt ⎠

3. Surface potential calculation method

⎜

(1)

⎜

φ − Vch ⎞ , Vt ⎠ ⎟

(2)

and Ntrap is obtained by multiplying the density of trap states Dit(E) by the trap occupation probability and integrating over the bandgap: Ec

Ntrap =

∫ Ev

Dit (E ) 1 + exp

(

E − Ef + qVch − qφ kT

)

(6)

where only the free charge density can be included in the RHS of [R1C2] Eq. (6), and trapped charge density is negligible due to good crystal quality of crystalline oxide semiconductor TFT channel film. In addition, Eq. (6) is also valid for the above-threshold region of AOS TFTs according to [6]. Therefore, we can solve the surface potential φs_c of crystalline oxide semiconductor TFTs to assume it as an initial estimate about the surface potential φs_a of AOS TFTs.

Here, q is the electron charge, εAOS is the dielectric permittivity of the channel film, and Nfree and Ntrap are free charge density and trapped charge density, respectively. Nfree is expressed as

Nfree = n 0 exp ⎛ ⎝

⎟

d

dE .

⎜

Here, n0 is denoted by n 0 = Nc exp

(

), N

C

( ) dφ

d2φ

φ −V 2 Cox (Vgs − Vfb − φs c )2 = 2qεAOS n 0 Vt exp ⎛ ch ⎞ ⎡exp ⎛ s c ⎞ − 1⎤ ⎢ ⎥ V t ⎠⎣ ⎝ Vt ⎠ ⎝ ⎦

(3) Ef − Ec Vt

dφ 2

( )

Using Gauss' law, relationship dx dx = 2 dx dx 2 , and the boundary conditions (dφ/dx)x=0 = 0 for Eq. (6), we can get the implicit function about φs_c:

is the charge density

⎟

⎜

⎟

(7)

Here, Cox is the gate-dielectric capacitance per unit area with Cox = εox/tox, and εox is the dielectric permittivity of the gate-dielectric film. Considering Vt < < φs_c, we can ignore the effect from “1” on Eq. (7). Analogous to our previous work [6], φs_c can be explicitly derived from Eq. (7) by using the Lambert W function (W0) [24], i.e.,

of states at the conduction band edge EC, Ef is the bulk Fermi level in the neutral channel film of AOS TFTs, Vt is the thermal voltage symbolled as kT/q, Vch is the channel potential, φ is the electrostatic potential depending on x, k is the Boltzmann constant, T is the lattice temperature. In addition, Dit(E) is assumed as the sum of both channel and gatedielectric/channel interface trap states, where channel trap states include exponential distributions of the deep and tail trap states [21] and interface trap states is approximated as uniform [8]:

qn0 εAOS ⎛ Vgs − Vfb − Vch ⎞ ⎤. φs c = Vgs − Vfb − 2Vt W0 ⎡ ⎥ ⎢ 2C 2 Vt exp 2Vt ox ⎠⎦ ⎝ ⎣ ⎜

⎟

(8)

Table I Parameters for simulations. Symbols (units)

Values in Figs. 2 and 3

Values in Figs. 4–6

Symbols (units)

Values in Figs. 2 and 3

Values in Figs. 4–6

Nc (cm−3 eV−1) Df(cm−2) gat (cm−3 eV−1) Eat (eV) gad (cm−3 eV−1) Ead(eV) Vfb (V) tox (nm)

4 × 1018 – 1 × 1018 0.15 1 × 1016 1.0 0 20

4 × 1018 1010 5 × 1018 0.1 5 × 1017 0.2 −3 100

tigzo (nm) W(μm)/L(μm) Ec(eV) Ev(eV) Ef(eV) μ0(cm2v−1 s−1) θ1 θ2

40 – 1.6 −1.6 0.4 – – –

70 200/2 1.6 −1.6 0.53 14 0.01 0.0001

2

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Fig. 2. Comparison between φs_a in Eq. (12) and numerical results, and absolute errors at Vch = 0 V.

Fig. 3. Comparison between φs_a in Eq. (12) and numerical results for the different Vch.

φs_c according to Eq. (9), and can be used to derive the explicit surface potential of AOS TFTs from Eq. (10). A similar approximation is shown to work well in [14], where smoothing function is still used to get the initial estimate of the surface potential. Analogous with the process from Eqs. (6)–(8), the implicit function about the surface potential φs_a of AOS TFTs is derived and approximated as

Furthermore, using φs_c, we give the effective charge density

neff exp

(

φ − Vch Vt

)

to reformulate the total charge density in Eq. (1). φs_c is

the initial estimate about the solution of φs_a, then we can obtain the equation for calculating the neff [cm−3], defined as the effective charge density of states at Ec, yielding

φs c − Vch ⎞ = Nfree (φs c ) + Ntrap (φs c ) Vt ⎠ Nfree (φs c ) + Ntrap (φs c ) . = φ −V exp s c V ch

neff exp ⎛ ⎝ ⎜

⇒ neff

⎟

(

t

)

2 Cox (Vgs − Vfb − φs a )2 = 2qεAOS neff Vt exp ⎛ ⎝ ⎜

(9)

⎜

⎟

(11)

Similarly with our previous work [6], φs_a can be explicitly derived from [R1C2] Eq. (11) by using the Lambert W function (W0) [24] as

Now, we can get the reformulation of Eq. (1) as

φ − Vch ⎞ d 2φ q neff exp ⎛ = . dx 2 εAOS ⎝ Vt ⎠

φs a − Vch ⎞ . Vt ⎠

qneff εAOS ⎛ Vgs − Vfb − Vch ⎞ ⎤ + ω. φs a = Vgs − Vfb − 2Vt W0 ⎡ ⎥ ⎢ 2C 2 Vt exp 2Vt ox ⎠⎦ ⎝ ⎣ ⎜

⎟

(10)

⎟

(12)

According to Eq. (12), we note that φs_a is an inherent closed-form

In addition, we note that neff is assumed as a variable depending on 3

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Fig. 4. Comparison between φs_a in Eq. (12) and numerical results for the different Vch.

Fig. 5. Comparison of output characteristics between Eq. (17) and experimental data [27].

without any semi-empirical parameter resulting from smoothing function. The correction ω is used to improve the accuracy of the surface potential solution. Here, ω is symbolled as

function of the above-threshold layer charge density Qi(φs_a) per unit area as

y yy′ ′ 3y 2 y ′′2 − y 2 y′y (3) ⎞ ω = − ⎜⎛1 + + ⎟ y′ ⎝ 2y′2 6y′4 ⎠

Ids = μeff

where

y

is

a

φ

(13)

function

(

of φ

−V

φs_a

W ⎡ sad − Qi (φs a ) dφs a + ⋅⎢ L ⎢φ ⎣ sas

∫

φs a d

⎤

∫ Vt dQi (φs a) ⎥.

φs a s

⎥ ⎦

(14)

Here, W is the channel width, L is the channel length, and φs_a_s and φs_a_d are solutions of φs_a corresponding to Vch = 0 and Vch = Vds, respectively. μeff is the effective mobility [26] which is also affected by the trapped charges, as roughly expressed by

with

)

ch 2 + Ntrap (φs _a) ⎤, and y = Cox (Vgs − Vfb − φs _a )2 − 2qεsi ⎡n 0 Vt exp s _aV t ⎣ ⎦ (3) y’, y”, and y are the first, the second, and the third derivatives of y versus φs_a, respectively.

μeff =

4. Drain current model According to the charge sheet model [25], with using the drift-diffusion approach and assuming the above-threshold layer along the xaxis in Fig. 1 as zero, the expression of the drain current Ids is obtain as a

Cox (Vgs − Vfb − φs a) − |Qtrap | Cox (Vgs − Vfb − φs a ) μ0 . ⋅ 1 + θ1 (Vgs − Vfb )1/3 + θ2 (Vgs − Vfb )2

(15)

where μ0 are the channel mobility, θ1 and θ2 are degeneration 4

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Fig. 6. Comparison of transfer characteristics between Eq. (17) and experimental data [27].

characteristics. It is noted that the above-threshold layer charge density Qi should be solved to integrate the expression of Ids in our compact model. Qi is derived through the Gauss' law as shown in Eq. (16), where Qtrap is denoted explicitly by −qNtrap(φs_a)tch based on the solution of φs_a. Obviously, this is more efficient than numerical integrations of our previous work [6]. In addition, we discuss about the effect from the interface trapped charges on the Ids-Vgs curves in Fig. 6. As the interface trapped charge density increases, Ids in the inversion region and the ratio of Ion/Ioff decreases, and the subthreshold swing increases. That has a strong influence on the device reliability, as the prediction of our model. In fact, the good quality of both the gate-dielectric/channel interface and gate-dielectric material directly decrease the interface trap density. The small interface trap density can improve the electrostatic performance and stability of the AOS TFTs.

parameters introduced by phonon scattering and surface-roughness scattering due to Vgs, respectively. Qtrap is the charge density per unit area symbolled by Qtrap=−qNtrap(φs_a)tch. By applying Gauss' law, we can obtain the inversion layer charge density per unit area as

Qi (φs a) = −Cox (Vgs − Vfb − φs ) − Qtrap.

(16)

Substituting Eq. (15) and Eq. (16) into Eq. (14) directly, we can analytically derive the drain current as

Ids = μeff

W 1 [Cox (Vgs − Vfb) + Qtrap ] φs a − φs2a + Vt Qi (φs a ) L 2

{

}

φs a d

. φs a s

(17)

5. Verification and discussion In order to validate our model, we use the Matlab tool to compare modeling results with numerical iteration results of the surface potential and measurement data for a-IGZO TFTs, respectively. The fitting parameters used in the calculation are listed in Table I. In addition, the corresponding numerical adaptations referring to [22,27] are needed, before the derivation of the model equations from physics can be used in an actual circuit simulator. In this paper, we use our model to simulate the electrostatic characteristics of a-IGZO TFTs in the relative ideal conditions. On the one side, we give the verification on the surface potential calculation method. At the channel voltage Vch = 0 V, surface potential results of our model is shown in Fig. 2. We can observe that φs_a calculated in Eq. (12) has a good match (maximum absolute error < 2 × 10−16 V) with numerical results of Eq. (1), but φs_c (i.e., the surface potential of crystalline oxide semiconductor TFTs) working as an initial estimate about φs_a is only valid for the above-threshold region. In the sub-threshold region, large errors are introduced by neglecting the trapped charges. In addition, in the cases of the different Vch, we can still obtain the good agreements between Eq. (12) and numerical results in Fig. 3. On the other side, to assure the practical application of our model, we show the verification on the drain current model by using the measurement data of a-IGZO TFTs [27], which have an inverted staggered bottom gate with a-IGZO active layer deposited by rf magnetron sputtering at room temperature. Fig. 4 shows the situation about φs_a vs. Vgs for the different Vch. Moreover, Figs. 5 and 6 show that the precise matches are obtained with the measured output and transfer

6. Conclusions An inherent closed-form drain current compact model for AOS TFTs accounting for trapped charges is proposed in this paper. Firstly, we improved the effective charge density approach to interpret the trapped charge density in the 1-D Poisson's equation. Secondly, we developed the surface potential calculation method of AOS TFTs, which is the inherent closed-form expression. Thirdly, based on the explicit solution of the surface potential, we analytically solved trapped charges per unit area to get the above-threshold charges per unit area and explicitly integrate the expression of the drain current. Finally, we verified this compact model and discussed about effect on the DC characteristics and the device reliability from the interface trapped charges. Simulating results show that such a model can be used in computer-aided-design simulators for display circuit application due to its high -accuracy and -efficiency.

Acknowledgment This work was funded partially by the Scientific Research Funds for the Young Teachers of Fujian Province under grant JAT170034, and partially by the Scientific Research Funds of Huaqiao University under grant 600005-Z16X0114.

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