A dedicated CAMAC crate controller for Z80-microcomputers

Nuclear Instruments and Methods in Physics Research 223 (1984) 107-112 North-Holland, Amsterdam

107

A DEDICATED CAMAC CRATE CONTROLLER FOR Z80-MICROCOMPUTERS P. K L O P F a n d W. S T ( J B E R Commission of the European Communities, CBNM Geel, Belgium

Received 15 August 1983

A low cost but versatile dedicated CAMAC crate controller for control of single crates by Z80-microcomputersis described. Main feature is its sophisticated interrupt system. Programming hints are given and adaptation possibilities to other 8-bit and 16-bit microcomputers are discussed.

1. Introduction Some time ago it has been demonstrated by a practical example that microcomputers of the personal computer type can be used with advantage to control single-crate CAMAC systems [1]. To minimize hardware design and construction work the described system uses a type L2 CAMAC crate controller which makes possible an extremely simple interface to the microcomputer. However, from technical and economical viewpoints this is not a good solution, because the L2-controller is complicated and, therefore, quite expensive. So later on it was decided to build a dedicated crate controller for use with the TRS-80 microcomputer and in general with all microcomputers containing a Zilog Z80 microprocessor. With small modifications it should be possible to use also other types of microprocessors. The first intention was to modify an existing design for the Commodore PET microcomputer [2,3], but gradually this work developed into a design of its own. The main feature of the new crate controller is its efficient interrupt system, which leads to an improvement of both the microcomputer and the CAMAC system.

2. General description CAMAC is a standardized interface system [4,5] which serves as a bridge bet~veen an (unspecified) computer and the "real world". A dedicated crate controller within this system is an interface between a specified computer and the CAMAC dataway, the bus system in a CAMAC crate. Our C C C - C / I F (CAMAC Crate Controller Computer Interface) is such a dedicated crate controller. It is a double-width CAMAC module which must be plugged into the two utmost right stations of 0167-5087/84/$03.00 © Elsevier Science Publishers B.V. (North-Holland Physics Publishing Division)

the CAMAC crate. The task of this crate controller is mainly to fan out the 8-bit bidirectional data bus of the microcomputer to the 24-bit unidirectional write data lines of the CAMAC dataway, to fan in the 24-bit unidirectional read data lines to the 8-bit data bus, to control the dataway function code lines from the computer data bus, and to decode the module address and subaddress from the computer address bus. In addition, the dataway timing strobes S1 and $2 must be generated, and appearing Look-At-Me demands must be forwarded to the microcomputer. As an extra feature the possibility to use auxiliary controllers in the crate has been provided. To this end a simple priority arbitration logic and a multiplexer for the encoded N-lines is incorporated. Thus, as seen from the CAMAC dataway, our dedicated crate controller looks like a somewhat stripped version of the standard crate-controller type A2 [6]. As already mentioned the C C C - C / I F has been designed as an interface between a CAMAC crate and the TRS-80 microcomputer made by Radio Shack (Tandy) [7]. Nevertheless, not only TRS-80 models I, II, III and TRS-80 compatible computers like the LNW-80 can be used, but virtually all microcomputers based on a Z80 microprocessor, as e.g. the Sinclair ZX Spectrum and various Eurocard computers. Connection to one of these computers is only a matter of choosing the appropriate cable and connector. (However, on the TRS8 0 / I I I an extra bus connector must be installed to get access to all relevant computer bus lines). For this connection a 52-contact double density D-connector has been provided on the rear of the C C C - C / I F . There is also a connector for the 40-wire auxiliary controller bus. On the front panel we find 3 coaxial connectors for the auxiliary controller priority arbitration chain as well as several indication LEDs.

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3. Hardware details To emphasize the similarities as well as the differences with the A2 crate controller a block diagram of our C C C - C / I F has been drawn in the style of the official CAMAC publication (fig. 1). So we see at one glance that the station number register as well as the LAM grader connector with its associated circuits have been omitted. It was felt that the possibility of multiple station addressing is not very important in most CAMAC systems, and the LAM-circuitry has been replaced by something better, i.e. a universal interrupt controller. But before coming to this interrupt system we should first have a look on the computer bus side of the crate controller (cf. also fig. 1). To the microcomputer our dedicated crate controller looks like a peripheral containing 8 addressable inputoutput registers on port addresses 8 to 15, as well as like a piece of 512 bytes of "wri.te-only memory". Port and memory addresses can be changed by wire jumpers over the whole available addressing range, i.e. 256 port addresses or 64K memory addresses, respectively. When using a computer with fixed read-only memory (ROM) like the TRS-80 it is advisable to place the "write-only memory" addresses within the ROM-address range, which is possible without mutual interference. What is now this strange "write-only memory"? It is simply a register which can be loaded by a computer memory cycle and which reacts equally well on 512 consecutive memory addresses because its address decoder ignores the 9 least significant bits of the 16-bit memory address. This 16-bit register will be loaded from the 8 computer data lines with the 5-bit CAMAC function code F and 2 additional bits which are normally 0, and at the same time with the 9 least significant bits of the 16-bit memory address. The latter will be used as the CAMAC module address N (5 bits) and the CAMAC subaddress A (4 bits). Thus the complete CAMAC NAF-code can be transferred by one instruction, e.g. in BASIC a POKE B + 16. N + A,F would be sufficient to execute a dataless CAMAC command (B = begin address of "write-only memory", chosen by wire jumpers). The 2 additional data bits just mentioned determine how the crate controller gets access to the CAMAC dataway in concurrence with auxiliary crate controllers and how it releases the dataway. Both 0 means that the Request/Grant mode is used for access priority arbitration and that the dataway is released after every CAMAC cycle. ACL = 1 means that the Auxiliary Controller Lockout mode is used for access, and MAINTAIN RI = 1 causes the controller to hold the dataway occupied till a CAMAC command with MAINTAIN RI = 0 is issued. The dataway cycle is started automatically after loading the NAF code register. If the F code is a READ

109

command then the 24 bits of CAMAC data are loaded in parallel into a read data register composed of 3 bytes. These 3 bytes have 3 port addresses and their contents c a n be read one after the other via the 8-bit computer data bus. If only one byte contains useful data, the other bytes need not be read. If the F-code is a WRITE command then the data contained in a 24obit write data register will be output onto the CAMAC dataway. It is clear that this register must have been loaded previously by the computer. This must be done bytewise by OUT commands to the 3 port addresses used also for the read data register. There is also a 1-byte CAMAC status register on an additional port address, which stores the status of dataway lines X, Q, I and the LAM demand line D at the time of dataway strobe $1 for further evaluation by the computer. This evaluation may or may not be carried out, but it is mandatory that the status register be read every time a CAMAC operation is finished. This will enable the CAMAC interrupt (LAM) system, which becomes automatically disabled at the beginning of each computer CAMAC operation. The 8-bit status register can also be loaded by the computer, which is useful for test purposes. The crate controller stores the complete NAF-code temporarily in a buffer register. Therefore, the microcomputer can fetch already its next instruction during the dataway CAMAC cyle. Normally the crate controller will be ready after about 1 /ts, but this time may be lenghtened considerably if there is a "HOLD"signal on the P2 dataway line or if the dataway is temporarily occupied by an auxiliary Controller in the crate. If during this time the microcomputer wants access to the crate controller, the latter will pull down the computer's WAIT line till the dataway cycle has been executed.

4. The interrupt system It must be admitted that the interrupt (LAM) system of CAMAC is quite poor. The same is true for the TRS-80/III. So both will be improved considerably by two integrated Universal Interrupt Controllers Am 9519 used in our dedicated crate controller. They manage the masking, priority resolution and vectoring of up to 16 interrupts [8,9]. This quantity is sufficient for medium size CAMAC systems. Any 16 of the 24 LAM-lines in the crate can be connected at will by wire jumpers to the interrupt inputs, which all have different but fixed interrupt priority. A LAM-interrupt of a certain priority will prevent lower-priority interrupts from reaching the computer before itself has been serviced, but servicing will be interrupted by higher-priority interrupts. Thus we have a 16 level deep, fully nested interrupt system. Any

110

P. Klopf, W. St~cber / Dedicated CAMAC crate controller

interrupt line can be independently enabled or disabled by software. This block of 16 interrupt levels may be embedded anywhere in the Z80 interrupt daisy chain [10]. This is not applicable to the T R S - 8 0 / I , but for this computer the internal interrupt system for clock and floppy disk has been retained. The internal and our new interrupt system run concurrently, internal interrupts having higher priority by hardware. When the interrupt controller has accepted a LAMinterrupt and passes it on to the computer interrupt line, the computer responds by one or several interrupt acknowledge pulses on its I N T A K line. This in turn triggers the interrupt controller to transmit one or several data bytes to the computer which cause a (indirect) jump to the appropriate interrupt service routine. How this works in detail depends on the interrupt mode of the computer. The Z80 processor can work in one of three different interrupt modes and the interrupt processor will support all of them. After a cold start the processor will automatically be in mode 0 ( = 8080 mode) but can easily be switched to mode 1 or 2 by program. Thus the decision is up to the programmer. As the T R S - 8 0 / I handles its internal interrupts in mode 0, it seems to be a natural choice to stay in mode 0 when a crate controller is attached to the computer. But to make the software more portable to other Z80-systems it is advisable to use the more elegant mode 2. This does not require any change to the internal interrupt service routine of the TRS-80, because only the way to access this routine is changed. If as a reaction to an internal interrupt request the TRS-80 issues an I N T A K signal, the hardware does nothing, which is sensed by the processor as "all ones" or FF hex on the data lines. In mode 0 this will be interpreted as the instruction RST 38, and in mode 2 as an interrupt vector byte. If the two memory bytes pointed to by the mode 2 interrupt vector contain 0038 hex then the internal interrupt routine will be accessed correctly. The interrupt controller must be preprogrammed to the desired functioning, its internal status must be readable, and it must be loaded with the interrupt vector bytes. Therefore each controller IC needs 2 in-out port addresses, which make up for the 4 remaining port addresses of the already mentioned 8. Fig. 2 shows a sample program in assembly language, which will initialize the two interrupt controllers and will load them with 16 consecutive interrupt vectors for mode 2 interrupts. As is c o m m o n practice for large ICs the two interrupt controller chips are mounted on IC sockets. Thus in small systems having less than 9 LAM connections simply one of the controller ICs can be left out, and a

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P. K/opf, W. St~ber / Dedicated CAMAC crate controller

system with no LAM interrupt needs no interrupt controller at all. The latter is even true for one single LAM connection, which may be jumpered directly to the interrupt controller output line (D in fig. 1).

5. Programming hints In contrast to the former solution with an L2 controller there is no absolute necessity to use special software. The whole program can be written in BASIC because the crate controller can be preprogrammed and operated by O U T / I N P and POKE statements. (Of course, interrupt routines must be written in assembly language as BASIC does not support interrupts.) The following example shows how a 24-bit dataword may be written into the computer and stored as a floating point variable D. 1000 POKE NA, F :'load NAF register (NA = B + N*16 + A). 1010 D1 = INP (8) :'fetch lowest CAMAC byte. 1020 D2 = INP (9) :'fetch middle CAMAC byte. 1030 D3 = INP (10) :'fetch most significant CAMAC byte. 1040 D4 = INP (11) :'fetch CAMAC status byte. 1050 D = D3.65536 + D2.256 + D1 :'build FP number. 1060 RETURN It is possible to get a shorter routine by replacing lines 1010, 1020, 1030 and 1050 by 1030 D = 65536 * INP (10) + 256* INP (9)+ INP (8), but this would aggravate a problem encountered already with the original routine, viz. possible loss of interrupts. As already mentioned the CAMAC interrupt system will be disabled when the POKE statement is executed and will be re-enabled by fetching the status byte. Even if we combine the statements of lines 1000-1040 on one multiple statement line to get some extra speed, the interrupt system will be disabled for at least 20 ms when using a TRS-80 with a 1.774 MHz processor clock. Though for a 4 MHz computer like the LNW-80 the disable time will be "only" 8.9 ms, these times are too long in many cases. There are several ways to cope with this problem, which will be pointed out here in an order of increasing software involvement of the user. (1) Compilation. A compiled BASIC program runs much faster than interpreted BASIC. This is especially true for the simple BASIC statements of lines 1000-1040. After compilation by an Accel 3 compiler [11] the interrupt disable time was reduced from 20 ms to 189/xs. (2) U S R statement. By the USR (X) statement the computer is forced to leave BASIC temporarily and jump to a user-written machine language routine. The code of this routine can be optimized for minimum interrupt disable time as is shown in the following

111

example, where it is assumed that processor registers A, C, DE have been loaded with the appropriate values LD(DE), A ; move NAF-code(READ) to CAMAC. IN L, (C) ; fetch LS data byte and store in reg. L. INC C ; update data byte address. IN H, (C) ; fetch second data byte. INC C IN D, (C) ; fetch MS data byte. INC C ; prepare status byte address. IN A, (C) ; load accumulator with status byte. This routine section is executed in 37.2 #s (16.5 #s on an LNW-80) and the interrupt disable time is even somewhat shorter. The arguments N, A, F can be transferred to the USR (X) routine by POKEing them into known memory addresses, and the data bytes D1, D2, D3 may be transferred by PEEKing. The CAMAC status byte may be passed by the routine to the variable S if we state S = USR (X). But if we have decided to write a user-routine we should go one step further and transfer arguments and data directly by the routine from and to BASIC variables. This is possible if we know the memory addresses of certain BASIC variables, which is easy when using the VARPTR statement, or, more elegantly, when forcing the BASIC variables of interest to be on top of the variable list table [12]. The latter may simply be effected by executing them in the first program line, as e.g. 0 DEFINT N, A, F, S : N = 0 : A = 0 : F = 0 : T = 0 . All CAMAC datawords may be transferred through the variable T to other variables. A 24-bit binary CAMAC data word just fits in the 3-byte mantissa of a single precision floating point number. Of course, the data bytes in registers L, H, D must first be shifted to normalized form and then also be provided with the appropriate exponent. For this work the normalization routine in ROM may be called (entry 0767). It is evident that data types other than 24-bit floating point can be treated in an analogous manner. Some caution must be exercised with subscripted variables (arrays) because their memory addresses may change during a program run. (3) Special C A M A C statement. A CAMAC statement such as provided for the L2 controller would be the most convenient solution for the BASIC programmer. However, special statements are not supported by the TRS-80 BASIC and must, therefore, be created by programming tricks. This diminishes the portability of programs and prevents BASIC compilation. For these reasons creation of a special CAMAC statement is not recommended.

6. Connection to other microcomputers Different types of microcomputers have quite different instruction sets, but nevertheless most of them have

112

P. K/opf W. Stf~ber / Dedicated CA MAC crate controller

quite similar bus structures and bus signals. Therefore, our TRS-80 dedicated crate controller will work directly with most 8080 microcomputer types. After minimal changes it will work also with 8085 microcomputers having multiplexed address and data lines. After programming the interrupt controllers for use with 8080/85 processors the C A M A C interrupt system will work as perfect as with Z80 processors. Connection to 8-bit microprocessors which are not "cognate" to the 80-types is also not difficult, but there will be some problems concerning the interrupt system. These computers cannot use the information stored in the response memory of the interrupt controller for an automatic j u m p to the appropriate service routine. So we must provide a hardware facility to read out this information by a general interrupt service routine. For example, when using an A P P L E It microcomputer it would suffice to connect the I A C K input pin of the Am 9519 interrupt controller to the D E V I C E SELECT line on an Apple peripheral connector. Then it would be possible to " m i l k " one or more of the interrupt information bytes out of the interrupt controller by LDX or J M P Indirect instructions. By this procedure all the benefits of the interrupt controller (except the automatic j u m p to service routine) are retained, which means a dramatic improvement of the Apple interrupt handling. If the crate controller is connected to a 16-bit microcomputer, two additional problems arise: the vast addressing space of these machines and their I6-bit structure, which forces even numbered bytes to be on other data lines than odd numbered bytes. Processors of the 8086-family e.g. deliver 20-bit memory addresses and 16-bit 1 / O addresses as well as a 16-bit data bus. Our crate controller can decode only I6-bit memory addresses and 8-bit 1 / O addresses and has only an 8-bit data bus. Though the latter problem seems to be the more serious one, it can be solved by very simple means: connect (by the cable between computer and crate controller) address bit 0 of the controller to address bit 1 of the computer, address bit 1 of the controller to address bit 2 of the computer etc., and connect the data bits of the crate controller to the corresponding 8 low-byte bits of the computer. If the program is written so that only even addresses are used for byte transfers to and from the controller it will execute correctly. These tricks are not necessary if the processor is a pseudo-16-bit type having an 8-bit data bus like the 8088 in the IBM-PC. The problem of the extra address bits must be solved by extra address decoders. These need not necessarily be added externally because every computer has various " c h i p select" decoders which eventually may be used also to gate our crate controller on and off. There may also arise additional problems with the interrupt system, because 16-bit microcomputers may have a more sophisticated interrupt structure with own interrupt controllers, which may not be compatible with the interrupt controllers in the crate controller. In this case the

C A M A C interrupt information must be read by program in a similar way as has been proposed for the Apple computer. After all, it is clear that our 8-bit crate controller can be used in connection with 16-bit microcomputers but that this is not an optimum solution. A specially designed 16-bit crate controller would be better, particularly concerning speed. It could e.g. make use of the vast addressing capability of 16-bit microcomputers by transferring the 5-bit C A M A C F-code not as data but in the address. In this way a single memory read or write machine code instruction would suffice to transfer a 16-bit C A M A C data word. If 24-bit words had to be read the C A M A C status byte could be transferred automatically in the same word with the third byte by a second instruction. To increase the adaptability to different types of microprocessors, the C A M A C interrupt system could be on an easily exchangeable small third board within the crate controller. 7. Conclusion The dedicated crate controller presented here is working without problems since december 1982, It combines the flexibility of C A M A C in data acquisition as well as in experiment and machine control, in an economical way, with the inexpensive computing power of 8-bit microcomputers, especially Z80-based types, its built-in interrupt features improve both C A M A C and the microcomputer. So it is possible to connect C A M A C to the most inexpensive computer types, as e.g. the Sinclair ZX 81. But this combination would highlight the main disadvantage of C A M A C : the price.

References [1] Klopf, van Rhee and Sti~ber, Nucl. Instr. and Meth. 187 (1981) 435. [2] Endo, Kawamoto and Taniguchi, Proc. Conf. on Real time data handling and process control (North-Holland, Amsterdam, t980)p. 613. [3] Taniguchi and Shiino, INS-TH-129, University of Tokyo (June 1980). [4] ESONE Committee, EUR 4100e (1972). [5] ESONE Committee, EUR 4600e (1972). [6] ESONE Committee, EUR 6500en. [7] Radio-Shack, TRS-80 microcomputer technical reference handbook, Tandy Corporation, Fort Worth, Texas, USA. [8] J.H. Kroeger, AM-PUB071, Advanced Micro Devices lnc., Sunnyvale, Cal. (1978). [9] Datasheet Am 9519 universal interrupt controller, Advanced Micro Devices Inc. [10] Z80-CPU and Z80-PI0 technical manual, ZILOG Inc.. Cupertino, Cal. [11] ACCEL 3 compiler for TRS-80 BASIC, Southern Software, c / o ALGORIX, San Francisco. [12] J. Farvour, IJG Computer Services, Upland, Ca, 1SBN 0-936200-01-4.