A low flicker noise direct conversion receiver for IEEE 802.11g wireless LAN using differential active inductor

Microelectronics Journal 42 (2011) 283–290

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A low flicker noise direct conversion receiver for IEEE 802.11g wireless LAN using differential active inductor M.A. Abdelghany n, R.K. Pokharel, H. Kanaya, Keiji Yoshida Graduate School of Information Science and Electrical Engineering, Kyushu University, Motooka 744, Nishi-ku, Fukuoka 819-0395, Japan

a r t i c l e in f o

abstract

Article history: Received 26 July 2010 Received in revised form 14 December 2010 Accepted 21 December 2010 Available online 8 January 2011

In this paper, a low flicker-noise, 2.4 GHz direct onversion receiver (DCR) has been designed. A dynamic current injection (DCI) technique has been utilized in addition with a tuning inductor in the mixing stage. The tuning inductor has been replaced by a differential active inductor circuit, which gives the same inductance, with less chip size and high quality factor. The DCR has been designed in a TSMC 0.18 mm 1P6M CMOS process for wireless LAN 802.11g applications. The proposed DCR achieves 6.7 dB SSB-NF, 34 dB conversion gain,  13.5 dBm IIP3, and flicker noise (1/f) corner frequency of 30 kHz with 137.5 mW power consumption from 1.8 V supply voltage. & 2010 Elsevier Ltd. All rights reserved.

Keywords: Direct conversion receiver Wireless LAN 802.11g CMOS analog integrated circuits Flicker noise differential active inductor

1. Introduction The IEEE 802.11g specification, which was ratified only in June 2003, has become the most widely deployed wireless local area network (WLAN) standard today. Its popularity is due in a large part to its support for higher data rates while maintaining backward compatibility with legacy IEEE 802.11b WLANs [1]. An IEEE 802.11g device achieves higher data rates when communicating with other 802.11g devices using orthogonal frequency division multiplexing (OFDM) modulation [2]. In order to realize WLAN 802.11g standard with CMOS analog integrated circuits, suitable receiver architecture should be selected. Direct conversion architecture is one of the best candidates to realize highly integrated solutions for wireless applications. Direct conversion is the natural approach to downconverting a signal from RF to baseband. It translates the band of interest directly to the baseband, with zero intermediate frequency (Zero-IF), and employs low-pass filtering to suppress nearby interferers. Among this the DCR has a few drawbacks: flicker noise, DC offset, even-order distortion, and LO leakage [3]. Flicker noise is a critical issue in DCR design as it almost degrades the signal-tonoise ratio (SNR) and total noise figure, which result in the degradation of overall receiver sensitivity. 1/f character means that the noise spectral density is inversely proportional to frequency. As the flicker noise power spectral density is also inversely proportional to frequency, the flicker noise

n

Corresponding author. Tel.: + 81 92 802 3745; fax: + 81 92 802 3720. E-mail address: [email protected] (M.A. Abdelghany).

0026-2692/$ - see front matter & 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2010.12.005

is called 1/f noise. A CMOS transistor, which is a surface device, has a much higher flicker noise than bipolar, which is a bulk device, possibly due to the random trapping in the oxide-silicon conduction of CMOS. Since the downconverted spectrum of the received signal is located around zero frequency in DCR, the 1/f noise in CMOS transistors may inherently affect the low frequency baseband signal. In consequence, the SNR at the receiver output increased, which results in receiver NF degradation [3]. In DCR circuit, most of the flicker noise contribution comes from the mixer stage, which should be designed carefully to reduce the output flicker noise. Many designs have been proposed to reduce the output flicker noise of the mixer. Static current injection has been proposed in [4,14], which was realized by injecting a continuous current in order to reduce the noise current pulses appearing at the output, which results in increasing the impedance of the LO switching stage seen by the RF transconductor, and allows more current to be shunted by the tail capacitance at this node. Dynamic current injection has been proposed in [13] in which a proposed circuit is used to inject a current pulse only at the switching instances rather than the continuous current proposed in [14], which gives more efficient flicker noise reduction, but still the tail capacitance existence gives a path to RF signal to be leaked to ground. The same design of [13] has been used by Yoon et al. [16] and a shunt tuning inductor has been added to resonate with this tail capacitance (Cp) at the node between the LO switches and RF transconductance stage. This design in [16] gives good results but it sacrifices the chip size because of the use of a bulky spiral inductor. This inductor used in [16] consumes more chip area, which results in large chip size, besides a relatively small quality factor.

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In this paper, a novel mixer circuit design is proposed using a differential active inductor (DAI) as a tuning inductor to further improve the mixer performance without adding more spiral inductors, which consume more die area. The benefits of DAI also include high quality factor, controllable inductance, and efficiently reduced flicker noise contribution of the mixer output baseband signal. This paper describes a front-end receiver integrated in a single chip using 0.18 mm CMOS process. The chip combines LNA, active balun, mixer, and baseband (BB) low-pass filter (LPF) integrated together in one chip.

VDD

RFout

RFin

2. Receiver architecture The basic block-diagram for proposed DCR receiver is illustrated in Fig. 1. The receiver comprises a low noise amplifier (LNA) followed by an active balun used to convert single ended LNA output to a differential signal suitable to feed the double balanced Gilbert cell mixer. The quadrature I and Q channels are necessary in typical phaseand frequency-modulated signals because the two sidebands of the RF spectrum contain different information. If they overlap with each other without being separated into two phases result in irreversible corruption [3]. Two mixers have been used to downconvert the RF signal to a quadrature BB signal. The mixer is followed by an on-chip low-pass filter to produce the necessary filtering and decrease LO and RF leakages to the output baseband signal. LO signal is supplied to the receiver externally, but the quadrature LO signal is generated on-chip using a second-order polyphase filter. A detailed description of each block follows.

Fig. 2. LNA circuit.

5

20

4.5

10

0

4

3.5

-10

3

-20

2.1. Low noise amplifier (LNA) Fig. 2 shows a simplified schematic of a very well-known LNA topology that uses a cascade structure with inductive degeneration formed by L3, resulting in a complex input impedance that can be matched to 50 O source impedance with an on-chip matching inductor L1. Resistive feedback using R2 helps to improve the stability factor (K) to provide unconditional stable amplification and reduce the gain sensitivity [6,7]. Fig. 3 shows the simulation

2.5

-30

S(2,1), dB S(1,1), dB

Noise Figure, dB 2

-40 1

1.5

2

2.5 Freq, GHz

3

3.5

4

Fig. 3. Noise figure, gain, and input return loss of the LNA (simulation).

I-Mixer results for the LNA design; it can be found that the LNA has a maximum gain of 15 dB in the band of interest; using a matching circuit the return loss is quite good at 2.4 GHz frequency, about  22 dB, and the LNA gives around 2.7 dB of noise figure.

Dynamic Current Injection Circuit

LPF

Antenna

IF_I 2.2. Active balun

180° Active Balun

LNA

0°

Poly-phase Filter

270°

LO

90° LPF IF_Q

Dynamic Current Injection Circuit

Q-Mixer Fig. 1. Proposed front-end receiver.

Single ended input LNAs are commonly used because antennas and RF filters usually produce single ended signals. On the other hand, differential signaling in the receive chain is preferred in order to reduce second-order distortion and to reject power supply and substrate noise. Thus, at some point in the receive chain a balun is needed to convert the single ended RF signal into a differential signal [8]. Fig. 4 shows the circuit diagram for the active balun. The input signal is amplified via two paths, a non-inverting common gate (CG) path, which consists of M3 and R3 with L4 as load, and an inverting common source (CS) path, which consists of M4 with inductive load L5. The voltage gains of these two paths are designed to be equal, which gives the balun function.

M.A. Abdelghany et al. / Microelectronics Journal 42 (2011) 283–290

VDD

285

VDD

0°

LO_0°

RFout +

LO

RFout -

LO_270°

LO_90° 180°

Vb2

RFin

LO_180° Fig. 6. Two stages in cascade of an RC polyphase filter. Fig. 4. Active balun circuit. VDD

0 Deg

0.0

-5 Deg

-0.5

-1.0 2

4

6

8

10

12

Minj1

Vinj

Minj2

Minj3 LPF on-chip

-10 Deg 0

Poly Resistor Load

5 Deg

0.5

Phase Mismatch (Degree)

Amplitude Mismatch (dB)

Amplitude Mismatch Phase Mismatch

Poly Resistor Load

10 Deg

1.0

VIF+ VIF-

Dynamic Current Injection Circuit

14

Frequency, GHz Fig. 5. Amplitude and phase mismatch of the active balun circuit.

The phase difference of the active balun can be calculated as follows [9]: ! gm oCgs Z02 1 ð1Þ ð+S21 ÞCS ð+S21 ÞCG ¼ tan 2 Z2 1 þ gm Z0 þ o2 Cgs 0 where Z0 is the characteristic impedance termination (50 O). By proper sizing and biasing of M3 and M4, the phase mismatch can be minimized for the band of interest. This balun has broad band performance and low power consumption. Fig. 5 shows the phase and amplitude mismatch over the full band. It is clear that the active balun circuit exhibits less than 0.3 dB of amplitude mismatch and less than 21 of phase mismatch around the 2.4 GHz band. 2.3. RC polyphase filter Direct conversion receivers need a local oscillator with quadrature outputs to complete the demodulation process. Quadrature phases may be generated by different circuit topologies; one of the simplest circuits is the cascaded four-branch RC polyphase filter [10,11] as shown in Fig. 6. When the circuit is driven at the input by two out-of-phase signals, the circuit reinforces one sequence of the two phases of oscillation, say clockwise, and attenuates the other counterclockwise sequence. With quite mild tolerances on its components, it is possible to derive quadrature phases from this network with orderof-magnitude improvements in phase accuracy, which is sufficient

M7

VLO+

M8

M9

M10

VLOLtune

CP M5

VRF+

VbiasRF

Differential Active Inductor

CP M6

Ibias

VRF-

VbiasRF

Fig. 7. Proposed Gilbert mixer with DCI circuit and DAI placement.

to drive the quadrature mixers in the receiver chain [10]. In the proposed receiver system, the differential local oscillator signals have been generated by off-chip phase splitter and these signals are injected to on-chip RC polyphase filter to generate the necessary quadrature signals. The RC poly-phase filters have been recently used in this way in a monolithic down-conversion mixer to attain effectively a 0.51 phase error and 0.5 dB amplitude error [10].

2.4. Double balanced Gilbert cell mixer A commonly used active mixer in CMOS systems is the Gilbert mixer. Double balanced mixer is just a combination of two single balanced Gilbert cell connected in parallel as shown in Fig. 7. This

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comprises an input differential transconductance stage formed by M5 and M6, a pair of mixer switching cores formed by M9–M12, and an output load formed by two poly-resistors. Mixer design with low flicker noise output will be shown in detail in the next section.

3. Low flicker noise double balanced Gilbert cell mixer Flicker noise is one of the critical issues in the direct conversion receiver, especially in the mixer stage. While the other RF circuits are not affected by flicker noise, such as low noise amplifiers (LNA) since their operating frequency is much higher than the flicker noise corner frequency, in the mixer circuit the case is different because flicker noise lies in the output band of the mixer, especially Zero-IF receivers, which convert the RF signal to BB directly [12]. Flicker noise in the mixer circuit has three sources: RF input stage, LO switching stage, and the load stage. Regarding the load, a polyresistor load, which is free of flicker noise, has been used in the proposed mixer; by this means, we can avoid any flicker noise contribution from the load stage. The RF input stage does not produce, to the first order, flicker noise to the mixer output, as the flicker noise that comes from the RF input stage is up-converted by a LO frequency, and filtered out by the baseband LPF [4]. Therefore, the flicker noise performances of the mixer are primarily determined by LO switching pair devices. 3.1. Flicker noise mechanisms in Gilbert cell mixers Two mechanisms have been reported in [4] that explain how flicker noise is generated in the mixer switching stage. The first one is the direct mechanism. In ideal mixers, the transconductance stage converts the RF input voltage to RF current, which should be switched from one side to the other by the switching transistors. Switching should occur at the zero crossing instances. By referring the switches flicker noise to the input and due to the finite slope of the switching LO signal, it results in an advancing or retarding of the switching instants. There switching instance deviations result in a noise current pulse train that appears at the output with double LO frequency. The DC average of noise pulse train in the output flicker noise current can be calculated as follows [4]: ð4IVn Þ ðSTÞ

ð2Þ

ð3Þ

where I is the bias current for the RF transconductance stage, T is the LO period, Vn is the input referred flicker noise of the switching pair, S is the slope of the LO signal at the switching instant, Weff and Leff are the effective width and length of the switching transistors, respectively, Cox is the oxide capacitance, f is frequency, and Kf is a process parameter [4]. From (2), in order to decrease the output flicker noise current pulses, it is required to increase the slope of the LO signal normalized to its frequency [ST] or reducing the flicker noise component of the switching FETs [Vn], which is inversely proportional to the device area, as shown in (3). Increasing the size of the switching pair may result in the reduction of the input referred to as flicker noise; at the same time the large switching size increases the parasitic tail capacitance Cp at the node between the LO switches and RF transconductance stage, as shown in Fig. 7, resulting in the flicker noise indirectly translating to the output, which is defined as indirect mechanism—the second mechanism that generates flicker noise [4,13]. Assuming that the LO signal slope is infinite, the average of the output noise current generated by the indirect mechanism is [4] io,nðindÞ ¼

 2 Cp oLO 2Cp Vn  2 T 2 þ C o gms p LO

ð4Þ

where Cp is the tail capacitance of the node between the LO switches and the RF transconductance stage, and gms is the transconductance of the LO switches. According to (4), the tail capacitance should be small enough to decrease the effect of the indirect mechanism. In order to decrease the flicker noise in CMOS active mixers, the bias current of the local oscillator (LO) switches should be small enough to lower the height of the noise pulses. The static current injection technique was proposed to reduce the bias current of the LO switches [14]. However, the impedance of the LO switches seen from the RF stage is increased as we reduce the bias current of the LO switches. In addition, RF leakage current flows through the injection circuit, which decreases conversion gain and also allows more RF current to be shunted by the tail capacitance (Cp) at the node between the LO switches and RF transconductance stage. Dynamic current injection (DCI) is proposed in Refs. [13,15,16]. VDD

VDD

M15

Poly Resistor Load

io,nðdirÞ ¼

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi kf Vn ¼ 2 Weff Leff Cox f

M16

Vinj

Vb2 M13

Minj1

M14 Minj3 M12

Vin+

I1

M11

I2

Vin-

Ltune

Fig. 8. Placement of DAI and its equivalent circuit.

LPF on-chip VIF+ VIF-

M.A. Abdelghany et al. / Microelectronics Journal 42 (2011) 283–290

DCI technique has been used in the proposed mixer in order to reduce direct flicker noise generation. As shown in Fig. 7, three PMOS, Minj1 through Minj3, are used to inject a dynamic current equal to the bias current of each pair of switches only at the switching event. Vinj is used to control the height of the injected current pulses. A parallel tuning inductor Ltune has been employed to tune out the parasitic tail capacitances (Cp) to alleviate the indirect flicker noise source. The usage of the tuning inductor is important to cancel out the effect of the tail capacitor in order to reduce the RF leakage through this capacitor, but using a spiral inductor will sacrifice the chip size to place a bulky inductor. In our proposed mixer circuit, this tuning inductor has been replaced by a differential active inductor (DAI), as shown in Fig. 8. This DAI consumes small chip area, compared to the spiral one, and has many other benefits, including high quality factor and tunable inductance. This will be discussed in the next section. DAI is connected to the mixer through two coupling capacitors to prevent the mixer and the DAI bias point deviation from the desired point.

4. Differential active inductor (DAI) and its measurement results

between two positive nodes. Many DAI circuits have been proposed [5], but unfortunately, most of these designs contain a large number of transistors, which result in more power consumption and more noise will be added to the circuit. Lu et al. [18] gave us a nice design for DAI with a small number of transistors, as shown in Fig. 8; they used this DAI in a VCO circuit [18]. Now, this design has been tested and employed in the proposed mixer circuit as shown in Fig. 8. Fig. 9 shows the small-signal equivalent circuit of the differential tunable active inductor, and its simplified circuit model of the active inductor. 4.1. Small-signal analysis Fig. 9(a) shows the simplified small-signal equivalent circuit of the DAI. M11 and M12 form a cross coupled pair, while M13 and M14 are connected in common drain configuration. M11–M14 are saturated at the bias point, but M15 and M16 can operate either in saturation region or in triode region, depending on the control voltage Vb2. Assuming that M15 and M16 biased to triode region, then they can be replaced by gds15 and gds16, respectively. Input impedance can be expressed by Zin ¼

CMOS active inductors are active networks that mainly consist of MOS transistors. Resistors are sometimes used as feedback elements to improve the performance of active inductors. Under certain DC biasing conditions and signal-swing constraints, these networks exhibit an inductive characteristic in a specific frequency range [5]. As compared with their spiral counterparts, CMOS active inductors offer some attractive advantages: low silicon consumption, large and tunable self-resonant frequency, large and tunable inductance, large and tunable quality factor, and compatibility with digital CMOS technologies [5]. Active inductor is now becoming a highly attractive choice for CMOS wireless communication systems [17]. Mainly, there are two types of active inductor: single ended and differential active inductor. In our proposal, we intended to use the differential one, as it will be a replacement of spiral inductor connected

Cgs13

+ Vgs12

2½joðCgs12 þ Cgs13 Þgm12 þgm15  gds15 ½gm12 þgm13 þ joðCgs12 þCgs13 Þ

ð5Þ

For 2gm12 þ gm13 4 gds15 the input impedance of the DAI can be approximated by the small-signal model, as shown in Fig. 9(b), where Leq ¼

2ðCgs12 þCgs13 Þ gds15 ð2gm12 þgm13 gds15 Þ

ð6Þ

Rs ¼

2ðgds15 þgm12 Þ gds15 ð2gm12 þ gm13 gds15 Þ

ð7Þ

Gp ¼

gds15 2

ð8Þ

From (6), we can conclude that the equivalent circuit inductance can be controlled by controlling the circuit parameters. An effective way to tune the inductance is change gds15 and gds16 by the gate

gds15

Cgs12

-

+ Vgs13

287

gm11Vgs11

gm14Vgs14

-

Vin+

gm13Vgs13

gm12Vgs12

- Cgs11 - Cgs14 Vgs11 Vgs14 gds16 + +

L GP

Zin

Rs

Iin Vin+

Iin

Vin-

Vin-

Zin Fig. 9. (a) Small-signal equivalent circuit of the differential active inductor and (b) the simplified circuit model of the active inductor.

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30 NF without tuning inductor NF with spiral inductor NF with DAI

Noise Figure, NF

25

20

15

10

3

Vb2 = 0.2v 5 3 10

Vb2 = 0.3v

2.5

4

5

10

2

8

10

10

Fig. 11. Noise figure simulation of the proposed DCR.

1.5 35

1

0 1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

Frequency, GHz 140

Conversion Gain, dB

Inductance, nH

7

10

Frequency, Hz

0.5

30

25

Vb2 = 0.2v

Conversion gain with DCI Conversion gain without DCI

Vb2 = 0.3v

120

20 2.3 x 109

Vb2 = 0.4v

2.35 x 109

2.4 x 109

100

Quality Factor

6

10

Vb2 = 0.4v

2.45 x 109

2.5 x 109

Frequency, Hz

80

Fig. 12. Conversion gain versus RF frequency.

60 40

20

20

0

0 1.0

IIP3= -13.5 dBm

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

-20 1 dB/dB

Frequency, GHz Fig. 10. (a) Microphotograph of the DAI circuit fabricated in TSMC 0.18 mm 1P6M process [chip size 102  93 mm2], (b) measured inductance, and (c) measured quality factor.

voltage Vb2 [19]. Also, the quality factor (Q), can be expressed by

oðCgs12 þ Cgs13 Þð2gm12 þ gm13 gds15 Þ Q¼ ðgm12 þ gm13 Þðgds15 gm12 Þ þ o2 ðCgs12 þ Cgs13 Þ2

-40

-60

-80

3 dB/dB

ð9Þ

Fig. 10 shows a die photo and measurement results for both equivalent inductance and quality factor of the DAI circuit. The inductor S-parameters had been extracted from raw data measured using a network analyzer by de-embedding of the pads parasitic, then the inductance calculated by L¼ Imag(1/Y11)/2pf, and Quality factor calculated by Q¼Imag(1/Y11)/real(1/Y11) [20]. From Fig. 10, it is clear that how the DAI inductance can be tuned using Vb2, and how large the quality factor can be achieved, as

-100 -60

-50

-40

-30

-20

-10

0

Input RF power, dBm Fig. 13. Third order intercept point (IIP3) of the proposed receiver.

compared to spiral inductor. All of these benefits come with a low power consumption of 1 mW of the DAI, which means not much chip area and not much power consumption are needed.

M.A. Abdelghany et al. / Microelectronics Journal 42 (2011) 283–290

289

Fig. 14. (a) Mixer layout with DCI and DAI, (b) mixer layout with DCI and spiral inductor, and (c) proposed DCR layout.

5. Proposed DCR simulation results The proposed DCR shown in Fig. 1 has been designed and simulated in TSMC 1P6M 0.18 mm technology, using a Cadence Spectres simulator.

A comparison between NF characteristics of three different cases is shown in Fig. 11. In the first case if we ignore the using of tuning inductor but DCI technique is still used, we obtain a flicker noise corner frequency around 200 kHz. Second, if we use a spiral inductor to tune out the parasitic capacitor (Cp), we can notice how

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Table 1 Performance comparison of the proposed receiver with other reported receivers. Ref.

Technology (mm)

Frequency (GHz)

Gain (dB)

IIP3 (dBm)

NF (dB)

Power (mW)

Flicker noise (kHz)

[19] [21] [22] [23] This Work

0.18 0.13 0.24 0.6 0.18

5.0 4.9–5.5 5 2.4 2.4

15–93 27 12 34 34

 4.8  12 2 9  13.5

4 3.3 (DSB) 5.2 8.3 6.7

150 36 12.4 80 137.5

30 110 NA NA 30

Acknowledgments

Table 2 Summary of the receiver performance. Operating frequency Noise figure (SSB) IIP3 conversion gain input return loss 1/f corner frequency Power dissipation Chip size Technology

2.4 GHz (WLAN 802.11g) 6.7 dB  13.5 dBm 34 dB 4  20 dB 30 kHz 137.5 mW 1830  1450 mm2 TSMC 0.18 mm

This work was partly supported by a Grant-in-Aid for Scientific Research from JSPS (KAKENHI) and Fukuoka project in the Cooperative Link of Unique Science and Technology for Economy Revitalization (CLUSTER) from Ministry of Education, Culture, Sports, and Science and Technology (MEXT). This work was also partly supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with CADENCE Corporation and Agilent. References

the corner frequency decreased significantly to a value around 30 kHz. Better result can be achieved using DAI as shown in Fig. 11. One more advantage is the controllability of the inductance in DAI circuit, which enables us to use an external voltage to get the optimum inductance value, which can be detected by lower corner frequency achieved. This reduction of corner frequency is gained using a very small chip size consumed by the injection and DAI circuitries, compared to the large spiral inductor [16]. On adding the DAI circuit, some noise will be generated from the active inductor circuit itself, but it has no significant effect because this noise is up-converted by the LO frequency, and filtered out by the baseband LPF; it can be shown from Fig. 11 that the white noises in three cases are almost the same with no extra white noise being added by the DAI circuit. Fig. 12 shows a comparison between the conversion gain of the DCR before and after using the DCI with DAI; it is clear that the gain is improved by 8 dB; this is because the effect of the tail capacitor has been canceled out and there is no more RF leakage through this capacitor. The proposed receiver achieves an input third order intercept point (IIP3) of  13.5 dBm, as shown in Fig. 13. The receiver draws 76.4 mA from 1.8 V supply voltage but only 0.2 mA has been consumed by the DAI. Fig. 14(a) shows the proposed mixer layout with DAI circuit. The DAI layout size is 89  86 mm2 compared to the spiral inductor in Fig. 14(b), which occupies a chip size of 210  210 mm2. Fig. 14(c) shows the front-end receiver layout with total chip area, with on-chip LPF, of 1830  1450 mm2, including the input, output, and biasing pads for measurements purpose. A performance comparison of the proposed receiver with the other reported receivers is shown in Table 1. It shows how the proposed receiver exhibits a low flicker noise corner frequency and high gain as compared to the other reported receivers. Table 2 shows the summary of the proposed receiver performance.

6. Conclusion A low flicker noise direct conversion receiver for WLAN 11.802g has been proposed and simulated using TSMC 0.18 mm technology. The receiver shows a third order intercept point of  13.5 dBm with 137.5 mW power consumption and 30 kHz flicker noise corner frequency using a dynamic current injection and differential active inductor techniques. The receiver achieves a 34 dB conversion gain and 6.7 dB SSB-NF. The receiver chip size is 1830  1450 mm2.

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