A Review on Online Testability for Reversible Logic

Available online at www.sciencedirect.com

ScienceDirect Procedia Computer Science 70 (2015) 384 – 391

* th

4 International Conference on Eco-friendly Computing and Communication Systems

A Review on Online Testability for Reversible Logic Hari Mohan Gaura , Ashutosh Kumar Singhb, Umesh Ghanekara a

Department of Electronics and Communication Engineering, NIT, Kurukshetra 116119, India b Department of Computer Applications, NIT, Kurukshetra 116119, India

Abstract Reversible logic is the key to enter into the new era of incredibly compact electronic devices with ultra low power consumption. Testing of these devices is another significant issue. As a new technology, new fault models are finding their confinements where testing ensures the true functioning of these devices. Several online testing strategies were proposed to spot these fault models, which are scaled on various performance parameters. This paper reveals a comparative review on online testability of reversible. Collective information of fault models, performance parameters and online testing strategies from the literature is presented. The aim is to bridge the knowledge gap for new researchers in this area rather than searching entire space. The detailed explanation of these strategies is provided by classifying them into two broad categories based on their designing principles. A comparison of experimental results on available number of benchmarks and some combinational logic circuits is presented in tabular form for better understanding. © 2014 The Authors. Published by Elsevier B.V.

© 2015 The Authors. Published by Elsevier B.V. This is an open access article under the CC BY-NC-ND license Peer-review under responsibility of organizing committee of the International Conference on Eco-friendly Computing and (http://creativecommons.org/licenses/by-nc-nd/4.0/). Communication (ICECCS Peer-review underSystems responsibility of the2015). Organizing Committee of ICECCS 2015 Keywords: Reversible Logic; Online Testing; Fault Models; Performance Measures

1. Introduction High power consumption is a major drawback of all portable electronic devices like display devices, mobile phones, electronic gadgets etc. At present all state-of-art chip architecture software design on power optimization is

* H. M. Gaur. Tel.: +91-8950156201. E-mail address: [email protected]

1877-0509 © 2015 The Authors. Published by Elsevier B.V. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/). Peer-review under responsibility of the Organizing Committee of ICECCS 2015 doi:10.1016/j.procs.2015.10.041

Hari Mohan Gaur et al. / Procedia Computer Science 70 (2015) 384 – 391

385

often done. Reversible logic is changing the whole scenario by drastically reducing the power requirements. It ensures nearly energy-free computation1 by preventing the power dissipation due to loss of information as in irreversible operations2. Researchers are showing their remarkable efforts in designing combinational and sequential logic functions in this emerging field to reach the boundaries of logic design with ultra low power consumption. The low power designs of important building blocks of processing unit like multiplexer/de-multiplexer3, adder/subtractor4 and ALU5 are the best examples over their irreversible one. Testing must be incorporated to validate these designs. Testing guarantees the true functioning of these devices, and thus it is very important to achieve desired results. Moreover the property of producing bijective functions reduces the complexities in testable design using reversible logic by providing fully controllable and observable operations as compared to testing of irreversible logic circuits. The Testing of any system as well as of reversible logic circuits can be categorized into online and offline approaches. Further differentiation can be made on the basis of different methodologies for testability. Designing with testable gates6-12 and designing by modification13-17 are found most favourable in the case of online testing. As a new technology, some open challenges come into the picture. Major challenges pertaining online testability include design complexity due to the high density of gates, very low signal levels, variety of fault models and technology problems like garbage output and ancilla input, fanout and feedback. In this review paper, we first summarize basics of reversible logic, fault, fault models and performance parameters associated with online testing in section 2. Second, we demonstrate various testing approaches pertaining to online testing of reversible logic circuits from the literature by categorizing them into two broad categories in section 3 and section 4. And finally a comparative study of these approaches on available benchmarks and combinational circuits is summarized on behalf of mentioned performance in section 5. 2. Basic Notations and Definitions 2.1. Reversible Function and Reversible Gate A logic function with n Boolean variables is a reversible function if it maps distinct input to distinct output, i.e. there should be n × n bijective function mapping between input and output without any repetition. A reversible gate realizes a reversible function. If a k input and k output gate produces distinct output for its distinct input functions is called as a k×k reversible gate. There is one to one mapping between input and output vectors and therefore the input state can be reconstructed from its output state. Some commonly used are Multi-Controlled Tofolli gates, MultiControlled Fredkin gates, Peres and Inverse Peres gates18. 2.2. Fault and Fault Models Faults are any kind of imperfection in a circuit which affects the functional behavior of a system. They are classified into two main categories19. First are permanent faults and second are non-permanent faults. The online approach finds its application to detect permanent as well as non-permanent faults. A fault model describes the type of fault occurred in a circuit and identifies the target of testing. In this review paper, we focused only on structural fault models in reversible logic circuits. A brief definition of fault models is written below. 2.2.1 Missing Gate Fault This fault refers to complete disappearance of a reversible gate from a circuit. These are transient fault models that appear in a circuit due to short or mistuned input pulses20. They may occur as single or multiple missing gate faults. 2.2.2 Cross-Point Fault This fault model is related to the extra/missing connection to/from wires of a gate in a circuit at cross-points or control points21. These are referred as the appearance and disappearance faults respectively.

386

Hari Mohan Gaur et al. / Procedia Computer Science 70 (2015) 384 – 391

2.2.3 Cell Fault This type of fault occurred due malfunctioning of any gate in a reversible circuit, such that it produces an incorrect output20. They may appear in a circuit in any form. These faults are based on the fault modeling of cellular logic arrays22 and that is why they are called as cell faults. 2.2.4 Stuck-at Fault Like traditional stuck-at fault model, this type of fault occurred in a circuit when one or more wire(s) gets stuck or fixed on a single value 0 or 1 and are called as single or multiple stuck-at 0 or stuck-at 1 faults respectively19. 2.2.5 Bridging Fault Again, similar to the traditional fault model, this type of fault takes place when two or more than two adjacent lines in a circuit get physically bridged or shorted by means of wired AND/OR interconnections19. They are called as single or multiple intra-level bridging faults. Whenever any type of fault occurred in a circuit, it will result in change of single or multiple values of bits on any wire in the circuit. They are termed as a single or multiple bit faults depending on number of fault sites. A Bit fault model23 is exclusively meant for online testing of reversible logic circuits and its detection will identify all discussed fault models. It may be a single bit fault or multiple bit faults. It is also mentioned in article23 where interconnections between different types of fault models were discussed. 2.3. Performance Parameters It has been noticed in the literature, the proposed testable design techniques in reversible logic circuits are justified by means of certain parameters. On the basis of these measures; the quality and performance can be evaluated. These performance measures are defined as follows: 2.2.1 Gate Count The total number of basic reversible gates required to realize a reversible circuit resembles its gate count and is the straightforward function to find the cost of a reversible circuit24. Sometimes gate count is analyzed on the basis of basic building blocks used to realize a reversible circuit to implement function e.g. R1 gate3. 2.2.2 Quantum Cost The quantum cost of a quantum circuit is defined as the sum of elementary quantum gates18 (NOT, CNOT, Controlled V and Controlled V+ gates) used to realize a circuit24, 25. For more information, please refer the online content26. 2.2.3 Garbage It is referred as additional output added to the circuit so as to maintain the equality between the number of outputs and number of inputs whose values are not important to realize a circuit27. 2.2.4 Ancilla Inputs In the designing of a reversible circuit from an irreversible function, certain constant inputs are required whose values are set constant 0 or 1 are referred as ancilla inputs28. Direct fanout is not permitted with reversible logic. An

Hari Mohan Gaur et al. / Procedia Computer Science 70 (2015) 384 – 391

additional Fynman gate is used for this purpose with one constant input wire to produce the same output or its complement depending on constant input value. This is sometimes referred as branch cost. Above mentioned parameters have a direct relation to the area/size; if these parameters increase they raise the size of the design and hence the power dissipation will increase, consequently they should be minimized. The quantum cost has proportional relation with gate count, ancilla input is an extra source of input power and garbage represents power loss. There are some technology dependent measures like delay28 which tells the computation rapidity and the fault coverage19 shows the quality of design. 3. Designing with Testable Gates Testing of reversible circuit exists since a decade and the researchers are showing their curiosity on the idea pertaining testing in emerging field of reversible logic. The smart way to achieve online testability is to design new online testable gates keeping minimum number of inputs, quantum cost and garbage output as a very few have proposed the same. These new gates do have some additional input and output other than functional ones to check whether a circuit performing correctly or not during its operation. 3.1 R1 and R2 Testable Gates The online testable 4×4 reversible gates R1 & R2 in addition with a new reversible gate R were introduced in the year 20046. The purpose of R1 gate is to produce the logical functions with a parity output bit, and gate R2 is to pass output of gate R1 directly to its output in addition with one more output parity bit. The testable block TB is formed by combining these R1 and R2, which conclude two test input and two test output. For the correct operation of the TB, the testable output must hold complementary values for complementary test input, which can be checked by using proposed dual rail checker circuit composed of the eight reversible R gate. Non complementary output of TB implies fault within the reversible gates R1 or R2. The testable realization of a set of benchmarks was done and the results were analyzed on the basis of number gates (R1/R2/R) used to synthesize a circuit which includes a total number of TBs and R gates used to implement required number of rail checker circuits as number of gates and garbage output. The idea was extended by the authors where proposed gates are implemented in CMOS technology7 using VHDL. Results conclude power dissipation in microwatts and total number of transistors required to realize a benchmark circuit. 3.2 R1 and R2 Testable Gates with IRC An efficient rail check named improved rail check (IRC) circuit was proposed8 in advancement of former approach that prove competent in terms of reduction of quantum cost and garbage output. The design consists of only a Fredkin gate and a Feynman gate rather than using R gates where a single test output depicts faulty operations in a circuit. A set of testable benchmark circuits and some sequential logic blocks were realized and performance was evaluated on the basis of total number of gates used and garbage outputs. 3.3 Online Testable CTSG Himanshu Thapliyal et al proposed a 4×4 reversible gate, namely OTG9, which can perform all Boolean functions efficiently in terms of computation complexity with respect to earlier proposed R1 gate. OTG is used in combination with 4×4 Feynman gate to form a testable block CTSG in order to achieve testability. The test output of CTSG should hold complementary logic values for the correct operation otherwise there will be a fault in OTG or in Feynman gate for different test input in accordance with the necessity of any logical function implementation. A number of testable combinational logic circuits like full adder, ripple carry adder and carry skip adder were synthesized using CTSG and the fault is verified using an improved two pair two rail checker proposed in their article. The implementations were justified in terms of number of OTG gate used, garbage output and unit delay.

387

388

Hari Mohan Gaur et al. / Procedia Computer Science 70 (2015) 384 – 391

3.4 Dual Rail I/O Testable Gates In 2010 Farazmand et al proposed an idea10 which reduces the design complexity by eliminating the necessity of separate rail checker circuit. He projected self testable reversible gates as NAND and fanout branch by means of dual rail coding scheme. These gates have the ability to implement Boolean functions and they also provide branching capability as it is not in consent of reversible logic which is required for synthesizing any circuit. Experiments were conducted on some set of benchmarks. In this method checker circuit is used only at the final output results in a large reduction of area in terms of branch cost. The method proved more efficient in terms of fault coverage and claimed cent percent coverage of single faults. 3.5 Testable Gates with Decision Line Further, in 2011 Zamani et al introduced the idea of modification of gates11 in such a manner that they produced necessary information at its output rather than parity generation method for the detection missing and repeated gate fault. The method comes in formation by including a detection line in his proposed gates whose value will inverse at every gate stage and error can be detected by knowing number of stages present in a circuit. The proposed reversible gates are Logic Gate LG, Fanout/Inversion Gate FIG and D-collector Gate DCG. The 4×4 LG gate is used to implement a Boolean function and 3×3 FIG gate is used to make fanout/inversion branch. The error can be detected on the basis of the final output of detection line which will be different for both even and odd number of stages in a circuit. This information is collected and analyzed by using 3×3 DCG gate with inputs Deven and Dodd for even and odd number of stages respectively for assigned control input. The erroneous output is identified by Alarm output of DCG. The realization of some set of benchmark circuit is done using this approach and performance is analyzed on the basis of garbage and delay. 3.6 Concurrent Error Detection Using the bijective property in reversible logic, inputs are regenerated at the outputs if the output signal is again applied at the inputs of a reversible circuit. The problem of testing was resolved by establishing the idea of detecting multi-bit error named as inverse and compare method12. The method shows the reduction of area/size by minimizing the requirement of excessive garbage output in design for testability. The problem of fanout was avoided by the use of Feynman gate. The implementation of concurrently testable full adder is proposed by using OTG6 and its inverse gate IOTG where outputs are taken from the intermediate Feynman gates. The fault can be detected by comparing primary inputs to OTG and outputs of IOTG resulting zero garbage and delay of 3 units using 3 gates only with quantum cost of 20. 4. Designing by Modification Another way of achieving online testability in reversible logic circuits is to design by modification of existing standard circuits. In this approach, the original circuit is modified by adding a number of reversible gates and wires with constant inputs in order to attain online testability. 4.1 Derived Gate Method In this regard Mahammed et al proposed a two step procedure of conversion of a gate into its testable one from its standard gate13. The authors also proposed a new reversible gate URG that realize four basic logic functions efficiently in terms of quantum cost. In first step a n × n reversible gate R into a deduced reversible gate (n+1) × (n+1) DRa without changing the original functionality of the circuit by adding a test input and a parity output. In second step DRa is cascaded with (n+1) × (n+1) identity reversible gate DRb with another test input and a parity output to form (n+2) × (n+2) testable reversible cell TRC. The identity gate DRb passes output of DRa directly to its output except another test input line and generate another parity bit. The detection of fault can be done by assigning logic values to both input parity bits and check corresponding output parity bits. If test inputs are assigned same

Hari Mohan Gaur et al. / Procedia Computer Science 70 (2015) 384 – 391

389

logic values, then output parity bits should be same or vice versa for non erroneous operation of TRC. Moreover a testable cell TC was also proposed to detect faults consisting of multiple TRCs. Authors illustrated their method by implementing a testable Fredkin based 2×4 decoder and proven efficient in terms of its CMOS characteristics with 2.249×10-9μW dynamic power using 1496 number of transistors with a critical delay of 13.2ns. 4.2 ETG for ESOP based Tofolli Circuits Another idea for testable design with existing circuit14 was proposed by N M Nayeem et al in 2011. The idea was meant for exclusive sum of product (ESOP) based Toffoli circuits which ensures the detection of single bit fault in a reversible circuit with a negligibly increment in garbage on the cost of small increase quantum cost. The process of conversion of an ESOP circuit in its testable form is followed by three steps. In first step every n-bit Toffoli gate in the circuit (n+1)-bit Extended Toffoli Gate (ETG) connected to additional parity line without disturbing original circuit. In the second step, CNOT gates are included from all the output lines to the parity line and in third step CNOT gates added from each input lines to parity line ahead and behind complete circuit. This requires addition of CNOT gates equals more than twice the number of input line which enhanced the quantum cost but garbage output is same as that of original circuit. The fault can be detected if the value of output parity bit changes from 0 to 1 during its operation. The performance of this method was predicted in terms of quantum cost and garbage output by performing experiments on some benchmark circuits depicting garbage output and quantum cost. 4.3 ETG for All Tofolli Circuits The approach in section 4.2 is extended by authors in the article15 for any type of Toffoli circuit. An online testable circuit is constructed from its original circuit in a similar manner by neglecting the second step in previous method. First a Toffoli gate is converted into ETG connected to additional parity line and then CNOT gates are inserted from all lines to parity lines before and after the original circuit. This requires only twice the number of lines additional CNOT gates. The fault is detected in the same manner by logic value at output of parity line. The detailed study is specified in the article16 where a large number of benchmarks have been developed and comparative study for proposed method is analyzed. 4.4 DFT Methodology In this regard Sen et al also proposed a DFT methodology17 using concurrent error detection scheme. The authors demonstrate the idea of converting a reversible gate into its online testable form, ensuring detection of nearly all multiple bit faults by introducing a DFT process algorithm based on parity generation which renovates a standard reversible gate into its online testable one. This result in three error detecting bits used to test a circuit to detect and locate the faults. Synthesis of a testable 3×3 Toffoli gate and a Peres gate was given where fault can notice by three error detecting bits. These bits should hold a null value for a fault free circuit operation. The results were evaluated by performing experiments on existing reversible gates, three benchmarks, a full adder and a full subtractor circuit which are synthesized by using proposed online testable Peres gate. 5. Comparison Analysis There are various types of methods seen in two broad classifications, designing with testable gates and designing by modification of existing circuits. These methods were claimed to cover new family of fault models by detecting single or multiple bit fault(s). These methods were justified on the basis of performance parameters: quantum cost (QC), Garbage (GO), number of gates used (NoG), and ancilla inputs (AI), which clearly directs toward up downs in area/size and consequently increment and decrement of power dissipation in designing with testability for reversible logic. Quantum cost was not reported by most of the researchers, but number of gates has proportional relation with it. The comparison of implemented online testable combinational circuits can be seen in Table 1 with performance measures. Table 2 summarizes a comparison of all covered benchmarking circuits26 incorporated with online

390

Hari Mohan Gaur et al. / Procedia Computer Science 70 (2015) 384 – 391

testability. It can be seen from the tables that the performance parameters QC and GO are comparatively small with R1 and R2 gates6, 7 and CTSG9 and GO is minimum in ETG based designs14-16 which shows more suitable online testable designs for reversible logic circuits. Table 1. Comparison Table for Online Testable Combinational Logic Circuits Circuit Full adder without propagate Full Adder with propagate 4-bit ripple carry adder 4-bit carry slip adder Full substractor

Vasudevan6, 7 QC GO NoG 3 4 2 4 -

QC -

Thapiyal9 GO NoG 2 2 8 4 17 22 -

QC 30 -

Thapiyal12 GO NoG 3 8 -

QC -

Sen17 GO NoG 14 21

Table 2. Comparison Table for all discussed Approaches

Moreover, the bijective property of reversible logic circuits that they contain same number of inputs and outputs is found most favorable for online testability. The property can be used to generate or preserve information of input and output vectors in form of parity easily. This property is used to design online testable gates and testable cells like R1 & R2 gates6, 7 and CTSG9. Also a reversible gate or a circuit was modified in order to generate parity bit by adding extra wire and CNOT gates13-16 and with concurrent error detection technique12, 17 to generate error detecting information. Despite of significant progress in online testability of reversible logic, talks and debates are still remaining to develop new methods of synthesizing testable reversible circuits with minimum quantum cost, garbage outputs and ancilla inputs to replace the existing ones. References 1. Bennett CH. Logical reversibility of computation. IBM J. Res. Development 1973;17(6):525–532. 2. Landauer R. Irreversibility and heat generation in the computing process. IBM J. Res. Develop 1961;5(3):183–191. 3. Gopal L, Raj N, Gopalai AA, Singh AK. Design of Reversible Multiplexer/De-multiplexer. In: IEEE Int. Conf. on Control System, Computing and Engineering. 2014. p. 416-420. 4. Gopal L, Chowdhury AK, Gopalai AA, Singh AK, Madon B. Reversible Logic Gate Implementation as Switch Controlled Reversible Full Adder/Subtractor. In: IEEE Int. Conf. on Control System, Computing and Engineering. 2014. p. 1-4. 5. Gopal L, Mahayadin NSM, Chowdhury AK, Gopalai AA, Singh AK. Design and Synthesis of Reversible Arithmatic and Logic Unit (ALU). In: IEEE Int. Conf. on Computer, Communication and Control Technilogy. 2014. p. 289-293. 6. Vasudevan DP, Lala PK, Parkerson JP. Online testable reversible logic circuit design using NAND blocks. In: Proc. 19th IEEE Int. Symp. Defect Fault Tolerance VLSI Syst. 2004. p. 324–331. 7. Vasudevan DP, Lala PK, Di J, Parkerson JP. Reversible logic design with online testability. IEEE Trans. Instrum. Meas 2006;55(2):406–414.

Hari Mohan Gaur et al. / Procedia Computer Science 70 (2015) 384 – 391

391

8. Hasan M, Tauhidul Islam AKM, Chowdhury AR. Design and Analysis of Online Testability of Reversible Sequential Circuits. In: Proc. 12th IEEE Int. Conf. Computer and Information Technology. 2009. p. 180–185. 9. Thapliyal H, Vinod AP. Designing Efficient Online Testable Reversible Adders with New Reversible Gate. In: Proc. IEEE Int. Symp. Circuits and Syst. 2007. p. 1085–1088. 10. Farazmand N, Zamani M, Tahoori MB. Online Fault Testing of Reversible Logic Using Dual Rail Coding. In: Proc. 16th IEEE Int. Symp. On-Line Testing. 2010. p. 204–205. 11. Zamani M, Tahoori MB. Online Missing/Repeated Gate Faults Detection in Reversible Circuits. In: Proc. IEEE Int. Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Syst. 2011. p. 435–442. 12. Thapliyal H, Ranganathan N. Reversible Logic Based Concurrent Error Detection Methodology for Emerging Nanocircuit. In: Proc. 10th IEEE Int. Conf. Nano Technology. 2004. p. 217–222. 13. Noor Mahammad SK, Veezhinathan K. Constructing online testable circuits using Reversible logic. IEEE Trans. Instrum. Meas 2010:59(1):101–109. 14. Nayeem NM, Rice JE. A Sinple Approach for Designing Testable Reversible Circuits. In: Proc. IEEE Pacific Rim Conf. Comm. And Signal Processing. 2011. p. 85–90. 15. Nayeem NM, Rice JE. Online Fault Detection in Reversible Logic. In: Proc. IEEE symp. Defect and Fault Tolerance in VLSI and Nanotechnology syst. 2011. p. 426–434. 16. Nayeem NM, Rice JE. Online Testable Approaches in Reversible Logic. Springer J. Electron Test 2013;29(6):763–778. 17. Sen B, Das J, Sikdar BK. A DFT Methodology Targerting Online Testing of Reversible Circuit. In: IEEE Int. Conf. Devices, Circuits and Syst. 2012. p. 689–693. 18. Chua SC, Singh AK. Heuristic Synthesis of Reversible Logic – A Comparative Study. Int. J. Advances in Electrical and Electronics Engineering 2014;12(3): 210-225. 19. Hurst SL. VLSI Testing - digital and mixed analogue/digital techniques. The Institution of Electrical Engineers, London, United Kingdom, 1998. 20. Polian , Hayes JP, Fiehn T, Becker B. A Family of Logical Fault Models for Reversible Circuits. In: Proc. 3rd IEEE Int. workshop Design and Test. 2008. p. 51–56. 21. Zhong J, Muzio JC. Analyzing Fault Models for Reversible Logic Circuits. In: IEEE Cong. Evolutionary Computation. 2006. p. 2422 – 2427. 22. Kautz WH. Testing for Faults in Combinational Cellular Logic Arrays. In: Proc. IEEE Conf. Record of the Eighth Annual Symp. Switching and Automata Theory. 1967. p. 161– 174. 23. Rice JE. An Overview of Fault Models and Testing Approaches for Reversible Logic. In: IEEE Pacific Rim Conf. Communications, Computes and Signal Processing. 2013. p. 125–130. 24. Golubitsky O, Maslov D. A Study of Optimal 4-bit Reversible Toffoli Circuits and Their Synthesis. IEEE Trans. Computers 2012;61(9):1341-1353. 25. Barenco A, Bennett CH, Cleve R, DiVincenzo DP, Margolus N, Shor P, Sleator T, Smolin JA, Weinfurter H. Elementary gates for quantum computation. J. Phys Rev A 1995;52(5):3457–3467. 26. Maslov D, Dueck G, Scott N. Reversible Logic Synthesis Benchmarks 2004. Available www.cs.uvic.ca/~dmaslov. (last access: May 2015). 27. Maslov D, Dueck GW. Garbage in Reversible Designs of Multiple Output Functions. Availabe: http://cs.unb.ca/profs/gdueck/reversible/multiple.pdf. (last access: May 2015). 28. Mohammadi M, Eshghi M. On Figures of Merit in Reversible Logic Designs. Springer J. Quantum Info. Processing 2009;8(4):297-318.