s low-power 0.35 μm CMOS pipelined ADC for DVB-H

INTEGRATION, the VLSI journal 45 (2012) 222–227

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An 8-bit 19 MS/s low-power 0.35 mm CMOS pipelined ADC for DVB-H ˜ oz, R.G. Carvajal, J.R. Garcia, F. Marquez B. Palomo n, F. Mun Department of Electronic Engineering, University of Seville, Spain

a r t i c l e i n f o

a b s t r a c t

Article history: Received 6 May 2011 Received in revised form 25 October 2011 Accepted 26 October 2011 Available online 4 November 2011

This paper proposes an 8b 19 MHz CMOS pipelined analog-to-digital converter (ADC) for DVB-H. In order to reduce the power consumption a combination of techniques has been used, such as op-amp sharing, low-power amplifiers with gain boosting and an aggressive capacitor scaling. The prototype ADC fabricated in 0.35 mm CMOS demonstrates a maximum differential nonlinearity (DNL) of 0.63 least significant bit (LSB) and a maximum integral nonlinearity (INL) of 0.58 LSB with a peak signal-to-noiseand-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of 42.76 and 51.57 dB at 19 MHz. The ADC with an active area of 4.78 mm2 consumes less than 4 mW at the mentioned sampling frequency. & 2011 Elsevier B.V. All rights reserved.

Keywords: Pipelined ADC CMOS analog integrated circuits Low power Low voltage Opamp-sharing

1. Introduction During the last few years much effort has been devoted towards the reduction of the supply power of mixed signal CMOS systems. This is primarily due to the increasing importance of battery-powered electronics, and the continued down-scaling of device sizes. Pipelining has been accepted as one of the best approaches to implement high-speed medium-to-high resolution analog-to-digital converters with minimum power consumption. Digital video broadcasting (DVB) system becomes very attractive for applications in wireless mobile communication devices, such as laptop computers, mobile phone and vehicles [1]. Recently, digital video broadcasting-handheld (DVB-H) has made it possible to deliver broadcast television or other multimedia services to a mobile or handheld device [2] The block diagram of a DVB analog front-end is shown in Fig. 1. The tuner selects the channel converting the OFDM RF signal to a first intermediate frequency around 35 MHz after which it is bandpass filtered by a SAW-filter stage. The SAW filter is followed by a controllable gain amplifier (AGC) in order to adapt the signal level. Finally the resulting signal is converted into a digital signal using an ADC. The proposed receiver implements a subsampling technique as this is the most efficient solution from a power consumption point of view. This technique performs, at the same time, the

n

Corresponding author. Tel.: þ34 954487472; fax: þ34 954487373. E-mail addresses: [email protected] (B. Palomo), ˜ oz), [email protected] (R.G. Carvajal), [email protected] (F. Mun [email protected] (J.R. Garcia), [email protected] (F. Marquez). 0167-9260/$ - see front matter & 2011 Elsevier B.V. All rights reserved. doi:10.1016/j.vlsi.2011.10.003

mixing and sampling process, taking advantage of the band folding inherent to the sampling process. For an intermediate frequency value of 34 MHz and the maximum signal bandwidth defined in the DVB standard (8 MHz), the optimum value for the sampling frequency is next to 19 MHz. Attending to the Mobile and Portable DVB-T Radio Access Interface (MBRAI) from EICTA, the SNR for the demodulation process should be 27 dB in the worst case. An 8 bit ADC achieves the specification, including a security margin in order to anticipate interfering components influence. This paper is organized as follows: the pipelined ADC 1.5-bit per stage architecture is shown in Section 2. Section 3 enumerates and details the low power techniques applied to the ADC in order to achieve such a low consumption. Section 4 describes the circuit implementation and the measurement results. The paper is concluded in Section 5.

2. ADC Architecture A 1.5-bit-per-stage architecture has been used in the pipelined ADC because it shows both the lower power consumption and smallest area compared with architectures based on higher resolution stages. The power efficiency of the 1.5 bit configuration [3–5] rely on that the amplifiers operate at a low closed-loop gain leading to a best settling time for minimum power consumption. A block diagram of the pipeline 1.5-bit/stage architecture is shown in Fig. 2. It consists of a cascade of seven stages. Each stage resolves two bits with a sub-ADC, subtracts the converted value, which only can take values  Vref,Vref or 0 (where Vref is differential reference voltage), from its inputs, and amplifies the

B. Palomo et al. / INTEGRATION, the VLSI journal 45 (2012) 222–227

223

RF AGC Parte analógica a banda base

Tuner SAW

Señal RF

AGC

ADC

Conversión a frecuencia intermedia

Fig. 1. DVB analog front-end.

ni bits

n1 bits

MRlarge2

n7 bits

MRlarge1 Stage 1

Stage i

Stage 7

Vclk

Vclkn

Vclk MpassN

Dout (i) ADC i

Vclk

Vclkn DAC i

Vin

Vcda (i) Vres(i) +

Vclkn VG

S/H

Vin (i)

Ccoup MpassP

Vout (i)

Vout Mswitch

Chold

2X

Fig. 3. Rail-to-rail sample-and-hold with bootstrapped switch. Fig. 2. Pipeline-ADC 1.5-bit/stage architecture.

3.2. Capacitor scaling resulting residue by a gain of two. The last stage of the pipeline does not need to generate a residue and, then, it does not require an op-amp. The resulting 14 bits are combined with digital correction to yield eight bits at the output of the ADC. Due to the digital correction, comparators offset up to 7Vref/4 can be tolerated without degradation of the overall SNDR using the mentioned technique. A fully differential solution has been implemented to maximize the power supply rejection ratio (PSRR) and to minimize even harmonic distortion.

3. Low power techniques This section describes different power saving techniques, whose combination lead to a very low power solution for the pipelined ADC presented. 3.1. Sample and hold amplifier The sample and hold amplifier (SHA) at the input of the pipelined converter usually takes one third of the overall converter power consumption [6]. The dedicated SHA has been removed in our design and the sampling operation is performed by the switched-capacitor residue amplifier (based on a Multiplying Digital to Analog Converter MDAC) of the first stage. In this case, special care needs to be paid to the input switches involved in the sampling process, and a Quasi-Floating-Gate based bootstrapped analog switch has been implemented to improve its linearity. In this way a resistance independent on the input signal is achieved in the ‘‘on’’ state, as a constant voltage is applied across the gate to source terminals of the NMOS transistor switch. As it can be observed in Fig. 3, a Quasi-Floating-Gate supply voltage boosting has been introduced to the former bootstrapped switch [7] in order to make rail-to-rail input signals possible for a further low-voltage implementation.

One of the main factors that set the power consumption of a pipeline converter is the value of the sampling and feedback capacitor in the MDAC. In a medium resolution pipelined ADC, the capacitor size is limited by matching instead of thermal noise [8]. In one hand, capacitor mismatch is worsened as capacitors in the MDAC are reduced. On the other hand, a large capacitor size translates to higher power consumption and lower speed. The linearity of the first stage in a pipelined converter needs to be at least in the order of the overall converter precision. The linearity of the rest of the stages can be relaxed as we progress through the signal chain at the same rate of the bits that already have been converted. Taking this into consideration, each stage capacitors may be scaled down as we advance in the signal chain. An analytical study [9] concludes that the minimum of the power consumption is achieved if sampling capacitors scaling factor is equal to the gain of the residue amplification stage. In our case, sampling capacitor sizes will be divided by two between successive stages. Capacitors in the MDAC are poly1-poly2, which are built up of poly 2 (top-plate), insulator (thin oxide) and poly 1 (bottom-plate). The minimum size for capacitors has been chosen by studying the pipelined converter resolution as mismatch between capacitors varies. 3.3. Operational amplifier topology The operational amplifier is the most critical block in the design, as it is the main contributor to the power consumption. System-level simulations, including the main non-idealities of the converter, have been done in order to determine the specifications for this building block. According to these, a DC gain greater than 70 dB and a gain bandwidth greater than 100 MHz will be required. As low consumption is required, the telescopic-cascode topology has been selected (Fig. 4), as it features only two branches whose currents are related to the load capacitance. In addition, these kinds of amplifiers also provide an excellent Gain Bandwidth Product (GBW) and a low noise. In order to achieve

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B. Palomo et al. / INTEGRATION, the VLSI journal 45 (2012) 222–227

Vcm Vsp MP

MP Vsp

LATCH Vcp

A

MPC

MPC Vo-

A

LATCH

M8

Vop

Vc2

Vo+

M7

Von

Vcp

LATCH A

MNC

MNC

LATCH

A Vc1

W2/L M1

V i+

MNi

MNi

Vip

V i-

W2/L

M2

W1/L

M3 Vrefn

Vrefp

M4

W1/L

Vin

Vb

M5 MN

MN

M6

Vb

Fig. 4. A telescopic-cascode op-amp with low-voltage gain boosting. Fig. 5. A differential pair dynamic comparator. Table 1 Summary of the Op-amp simulated performances. Parameter

Value

DC gain (dB) Unity gain frequency (MHz) Phase margin (Deg.) Signal range: Inp–Out (V) PSRR (dB) CMRR (dB) Power dissipation (mW) Supply voltage (V) Technology (mm AMS-CMOS)

80 430 78 0.9–1.9 96.19 92.68 1.35 2.5 0.35

Note that the quiescent current consumption is zero due to the absence of preamplifiers. Nevertheless, due to the absence of preamplifiers, a special attention should have to be paid to the kickback noise in this kind of comparators. The digital correction circuitry relaxes the specifications of the comparators in our design, so the kickback noise is not a problem and such a simple latch can be used. The dynamic power consumption is only 0.055 mW per comparator, which results in a power consumption of less than 1 mW in the whole pipelined converter. 3.5. Operational amplifier sharing technique

enough DC gain, the gain-boosting technique [10] has been applied to the cascode transistors of the telescopic amplifier. To obtain a large signal swing at the output of the amplifier, a wide swing gain boosting circuitry has been chosen. Post-layout simulation results show that, when loaded with 500 fF, the op-amp can achieve a DC gain of 80 dB and a unity gain-bandwidth product of 430 MHz. Table 1 describes the performances of the op-amp, which fits the required specifications. 3.4. Dynamic comparator The sub-ADC in each pipeline stage consists of two fully differential comparators. The sub-ADC thresholds are þ Vref/4 and Vref/4, and the differential input signal range is ( Vref, þ Vref). In order to reduce the power consumption, a dynamic latchtype comparator [11] without pre-amplifiers has been selected (Fig. 5). The comparator threshold voltages are set by sizing M1, M2, M3 and M4, which are biased in triode region according to the following equations:   1 W1 W2 ðV ip V th Þ þ ðV ref n V th Þ ¼ Kn ð1Þ R1 L L   1 W1 W2 ðV in V th Þ þ ðV ref p V th Þ ¼ Kn R2 L L

ð2Þ

And the relationship between the threshold voltages and the widths of transistors is given by ðV ip V in Þ ¼

W2 ðV V ref n Þ W 1 ref p

ð3Þ

Significant power saving can be achieved if one operational amplifier is shared between two consecutive stages of the pipelined converter, as shown in Fig. 5. Note that the operational amplifier of a stage is not active during its sampling phase, so that it can be used for the residue calculation phase of the next stage. By means of this technique the number of operational amplifiers in the converter can be reduced to a half, and 8 bits can be converted with only three operational amplifiers. The operational amplifier sharing technique is illustrated in Fig. 6. During the first clock phase in the conversion process (F1), the first stage (in the bottom part of figure), performs the sampling phase and the 1.5 bit conversion of the input signal. At the same time its operational amplifier is used in the second stage (in the upper part of figure) where the residue calculation takes place. During the second clock phase (F2), the operational amplifier of Fig. 5 is used in the first stage to calculate the residue, which appears in Vout at the end of this phase. At the same time Vout is being sampled by the sampling circuitry of the second stage [12]. The transfer function of the 1.5 bit/stage pipeline ADC is given by 8  > 1 þ CCfs V in V ref if V in 4 V ref =4 > > > >  < 1 þ CCfs V in if V ref =4 r V in r þ =4 ð4Þ V out >   > > > C s > : 1 þ C f V in V ref if V in rV ref =4 where Cs is chosen to be equal to Cf to provide a gain of two. The main drawback of the amplifier sharing technique comes from the fact that the amplifiers are now active in every phase, so that they have no a spare phase available to implement an offset correction technique. To alleviate this problem the FSI (Feedback

B. Palomo et al. / INTEGRATION, the VLSI journal 45 (2012) 222–227

Vref

225

Table 2 Summary of the experimental ADC performances.

Vref

Vref Vref

Parameter

Value

Vdd(V) Technology (mm CMOS AMS) (double poly capacitors) Resolution (ENOB) Conversion rate (MS/s) Input range (V differential) Core power dissipation (mW) DNL (LSB) INL (LSB) SNDR (dB) (@1.1 MHz,0 dBFS) SFDR (dB) (@1.1 MHz,0 dBFS) THD (dB) (@1.1 MHz,0 dBFS) Total area (mm2) FOM (pJ)

2.5 0.35 7.30 19 71 E4  0.59/0.63  0.19/0.58 42.76 51.57  58.48 4.78 1.88

Fig. 6. Operational amplifier sharing technique scheme. DNL vs. code

0.8

0.6

0.4

STAGE 3&4 STAGE 5&6 SUB CAD

CLOCK GEN

DNL (LSB)

STAGE 1&2

0.2

0

-0.2

Fig. 7. Layout of the ADC. -0.4

Signal Polarity Inverting) technique has been used in this paper. In the FSI technique the op-amp terminals are inverted in every phase, so the sum of the combined errors due to flicker noise (1/f), offset and finite gain of the kth-sample at the output of the amplifier will be reduced in a 60 per cent [6].

-0.6 0

100

150

200

Code

Fig. 8. Measured differential non-linearity (62,516 points).

4. Experimental results

INL vs. code 0.6 0.5 0.4 0.3 INL (LSB)

The converter has been implemented using a 0.35 mm conventional CMOS technology (AMSC35). Fig. 7 shows a microphotograph of the ADC, which uses conventional layout techniques for switched-capacitor circuits in a differential configuration. A symmetrical layout has been implemented using a commoncentroid technique for matched components. Analog and clock wires never cross to avoid high-frequency noise coupling. None of the capacitors in the design is under 100 fF to avoid parasitic capacitors influence. The prototype ADC occupies an active die area of 4.78 mm2 and dissipates 4 mW at 2.5 V and 19 MS/s. Table 2 summarizes the experimental performances of the proposed ADC. The static performance of the ADC is given by a measured maximum differential non-linearity (DNL) of 0.63 LSB, and a maximum integral non-linearity (INL) was of 0.58 LSB. Figs. 8 and 9 show the measured DNL and INL, respectively. Different measurements have been performed to characterize the dynamic performance. The dynamic performance of the ADC was for a 1.1 MHz single input tone with a clock frequency of 19 MHz, as illustrated in Fig. 10. The peak signal-to-noise-anddistortion ratio (SNDR) was measured with different input frequencies up to 9.4 MHz as shown in Fig. 11. The spurious-free dynamic range (SFDR) and the total harmonic distortion (THD) in Fig. 12 are measured with increasing input frequencies at a typical sampling frequency of 19 MHz. The SNDR, SFDR and THD are maintained over 42.76, 51.57 and 58.48, respectively.

50

0.2 0.1 0 -0.1 -0.2 0

50

100

150

200

code

Fig. 9. Measured integral non-linearity (62,516 points).

To compare the overall performances of different reported ADCs, a unique figure-of-merit (FOM) is of interest. In this paper the normalized power consumption FOM has been used, which is defined as the power consumption (in Watt) divided by the product of the effective-quantization-levels and the sampling

B. Palomo et al. / INTEGRATION, the VLSI journal 45 (2012) 222–227

80

4.5

60

4

40

3.5

[14]

[15]

3

20

FOM (pJ)

Densidad espectral de potencia (dB)

226

0

2.5 [16]

2

[17]

[18]

-20

1.5

[19]

-40

1

[13]

[20]

[This work]

[22]

[23]

-60 10 5

6

10 Frecuencia (Hz)

10

7

[25]

0.5 [29]

[28]

Fig. 10. Measured power spectral density for a 1 V, 1.1 MHz, sinusoidal input signal with a clock frequency of 19 MHz (62,532 points).

0 7.5

8

8.5

[6] [21] [24] [26] [30]

9

[27] 9.5

10

ENOB (bits) Fig. 13. FOM versus ENOB for recently reported 8-bit and 10-bit ADCs (Refs. [6,13–30]).

rate (in Hz).

50 45

FOM ¼

40

ð7Þ

Fig. 13 shows the value of the FOM defined above for different state-of-the-art, 8-bit and 10-bit pipelined ADCs versus the effective number of bits (ENOB). Note that the ADC proposed in this paper features one of the lowest normalized power consumption FOMs.

35 SNDR (dB)

P dis 2ENOB f samp

30 25 20 15

5. Conclusions

10 5 0

1

2

3

4

5 6 Frecuencia (Hz)

7

8

9

10 x 10

6

Fig. 11. Measured SNDR vs. input frequency (62,532 points).

This work describes an 8b 19 MS/s CMOS pipelined ADC implemented in a 0.35 mm standard digital CMOS technology for low power applications. The measured prototype ADC shows a maximum SNDR and SFDR of 42.76 and 51.57 dB at 19 MS/s, respectively. The ADC with an active die area of 4.78 mm2 consumes 4 mW at 19 Ms/s and 2.5 V supply. The novelty of the paper is in the skillful combination of different power saving techniques to achieve an ADC, which features one of lowest normalized power consumption FOMs in the literature.

THD,SFDR,SNDR vs. sampling frequency 60

Acknowledgments

58

Authors would like to acknowledge financial support from the Spanish Ministry of Science and the Andalucia Regional Government under projects TEC2005-08091-C03-03/MIC, FIT 3301002006-43 and TIC2006-01500, respectively.

56 54

dB

52

References

50 48 46 44 42

1

1.2

1.4

1.6

1.8 2 2.2 2.4 Sampling Frequency (Hz)

2.6

2.8

3 x 10

6

Fig. 12. Measured (  THD) (‘  ’),SFDR (‘þ’) and SNDR (‘o’) vs. input frequency (62,532 points).

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B. Palomo was born in Dos Hermanas, Seville, Spain. He received the telecommunications engineering degree from the University of Seville, Seville, Spain, in 2002. Since that year, he has been with the Department of Electronic Engineering, School of Engineering, University of Seville, where he has been a reader since 2005 and is currently pursuing the Ph.D degree. In 2003, he was a trainee at Natlab, Philips Research, Eindhoven, The Netherlands. His research interests are related to low-voltage low-power analog circuit design, analog–digital conversion, and analog and mixed-signal processing.

227

˜ oz (M’05) was born in El Saucejo, Sevilla, Spain. F. Mun He received the telecommunications engineering and Ph.D. degrees from the University of Seville, Seville, Spain, in 1998 and 2002, respectively. Since 1997, he has been with the Department of Electronic Engineering, School of Engineering, University of Seville, where he has been an Associate Professor since 1999. In 2000 and 2002, he was a Visiting Researcher at Natlab, Philips Research, Eindhoven, The Netherlands, and in 2003, in the Klipsch School of Electrical Engineering, New Mexico State University, Las Cruces. His research interests are related to low-voltage low-power analog circuit design, analog–digital and digital–analog conversion, and analog and mixed-signal processing.

R.G. Carvajal (M’99–SM’04) was born in Seville, Spain. He received the electrical engineering and Ph.D. degrees (with honors) from the University of Seville, Seville, Spain, in 1995 and 1999, respectively. Since 1996, he has been with the Department of Electronic Engineering, School of Engineering, University of Seville, where he has been an Associate Professor (from 1996 to 2002), and Professor (since 2002). He was Invited Researcher at the Klipsch School of Electrical Engineering, New Mexico State University (NMSU), Las Cruces, in the summers of 1999 and 2001–2004, and also in the Electrical Engineering Department of Texas A&M University in 1997. He also holds the position of Adjunct Professor at the Klipsch School of Electrical Engineering, NMSU. He has published more than 60 papers in international journals and more than 130 in international conferences. His research interests are related to low-voltage low-power analog circuit design, analog–digital and digital–analog conversion, and analog and mixed-signal processing.

J.R. Garcia was born in Seville, Spain, in 1981. He received its Telecommunication Engineer degree and Master degree in Electronics, Signal Processing and Communication from University of Seville, in 2007 and 2008 respectively.He is currently working in the Electronics Engineering Department, University of Seville, as PhD Student with a FPU Scholarship from 2008, out a national public selection. His research interests include A/D and D/A converters, data acquisition systems, testing wideband multi-standard receivers, high speed instrumentation, PCB design, signal processing and clock generating (VCO, PLL and DDS).

F. Marquez was born in Sevilla, Spain. He received the Telecommunication Engineering degree from the University of Seville, Seville, Spain, in 2006. Since 2005, he has been working with the Department of Electronic Engineering, School of Engineering, University of Seville, where he is currently working towards his PhD. His interests are related to Mixed-Signal design of low voltage low-power communication receivers, with special emphasis on High-speed Analog to digital conversion.