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s 17.7 nW 9.1ENOB reference-insensitive SAR ADC in 0.18 μm CMOS
Microelectronics Journal 73 (2018) 24–29
Contents lists available at ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
A 10bit 20 kS/s 17.7 nW 9.1ENOB reference-insensitive SAR ADC in 0.18 μm CMOS Yuhua Liang, Zhangming Zhu * School of Microelectronics, Xidian University, Xi'an, 710071, China
A R T I C L E I N F O
A B S T R A C T
Keywords: SAR ADC Low power Switching scheme
This paper presents a 10bit 20 kS/s 9.1ENOB SAR ADC employing an energy-efficient and highly-linear capacitor switching strategy in 0.18 μm CMOS process. The SAR ADC with this proposed strategy features better linearity due to the use of a relatively lower assistant reference, the value of which is equivalent to a quarter of the input swing. In addition, the accuracy of the assistant reference has no impact on the ADC performance, since only this assistant reference will be involved with the capacitive DACs during the conversion period. The ADC is powered by the supplies of 0.6 V/0.15 V. The capacitive DACs are supplied by the 0.15 V assistant reference, while the other blocks are powered by the 0.6 V reference. In this case, the ADC consumes 11.7 nW overall, resulting in a figure-of-merit (FOM) of 1.6fJ/conversion-step. At a 20-kS/s output rate, the measured results show the proposed SAR ADC performs a peak signal-to-noise-and-distortion ratio (SNDR) of 56.5 dB, a peak spurious-free-dynamicrange (SFDR) of 66.7 dB. The core area of the designed ADC is and 370 310 μm2.
1. Introduction Owing to the advantages of simple structure, minimal usage of analog block and energy-efficiency, SAR ADCs are the optimal choice in many low-power application areas. Moreover, SAR ADCs feature high compatibility with the increasingly scaling-down semiconductor manufacturing process and can work at low supply voltages. These advantages endow SAR ADCs with the possibility to become a trend as the semiconductor manufacturing process develops. Among the function blocks in an SAR ADC, the capacitive DACs are always a major contributor to the power consumption. And the employed switching strategy is a major factor of the power consumed by the capacitive DACs. During the past several years, researchers all over the world endeavored themselves to improve the power efficiency of the SAR ADCs with efficient switching schemes [1–7]. It is noted that the effectiveness of the schemes in Refs. [6,7] are inferior to that of what proposed in Ref. [5]. Compared with the scheme proposed in Ref. [5], the switching energy of the proposed scheme can be reduced by 51% approximately. When the reset energy is taken into consideration, a reduction of 83.4% is achieved in total. It is known that the linearity of the SAR ADC depends on both the matching property of the DACs and the employed switching strategy.
Thanks to the utilization of 1/4Vref (rather than Vcm ¼ 1/2Vref or Vref) in the conversion period, the linearity of an SAR ADC that adopts the proposed approach can be improved significantly. On condition of the same unit capacitor, the standard deviation of the maximum differentialnon-linearity (DNL) for the proposed strategy can be reduced to a quarter of that for the set-and-down strategy. Observing the quantization process of the Vcm-involved strategies [2–5], we arrive at the conclusion that any mismatch between Vcm and Vref can degrade the ADC performance. Provided that the proposed strategy is employed, only the assistant reference 1/4Vref will be involved in the conversion course. Therefore, not only can the power efficiency be improved, but also the ADC performance is immune to the inaccuracy of the assistant reference. To verify the advantages of the proposed switching strategy, a 10bit 0.6Vpp 20 kS/s SAR ADC is fabricated in 0.18 μm CMOS technology. The capacitive DACs are powered by the 0.15 V assistant reference, which is a quarter of the swing of the inputs. Detailed descriptions and discussions will be given in the following sections. 2. Architecture design The diagram of the proposed SAR ADC is shown in Fig. 1. It is composed of two differential binary-weighted capacitive DACs, two
* Corresponding author. E-mail address: [email protected] (Z. Zhu). https://doi.org/10.1016/j.mejo.2018.01.006 Received 4 January 2017; Received in revised form 7 November 2017; Accepted 8 January 2018 0026-2692/© 2018 Elsevier Ltd. All rights reserved.
Y. Liang, Z. Zhu
Microelectronics Journal 73 (2018) 24–29
bootstrapped switches, a synchronous SAR digital logic circuit, and a dynamic latch comparator. The binary-weighted architecture is always a popular choice for DAC design since the matching requirement can be met more easily, compared with the split architecture [8]. The dynamic latch comparator compares the successive-approximation voltages on differential capacitor arrays and determines the values of the output code bit-by-bit. After decoding the comparator output, the SAR logic controls the switches to realize the employed switching strategy. For an N-bit SAR ADC, completion of one conversion always requires N comparisons. In addition, a differential architecture is employed to suppress the common-mode noise. 3. Proposed switching strategy 3.1. Proposed switching procedure and linearity The proposed switching strategy for a 3bit SAR ADC is illustrated in Fig. 2. VK, here, representing the assistant reference here, is equal to 1/ 4Vref (Vref represents the traditional reference voltage, and all blocks but the capacitive DACs are supplied by Vref). Though equal to Vref in the ideal case, the input swing of Vip/Vin is actually scaled down in a small degree owing to the existence of the parasitic capacitance). (1) In the sampling phase, the inputs are sampled on the top plates of the capacitors. Meanwhile, the MSB capacitors and (MSB-1) capacitors, CP2, CP1, CN2 and CN1, are also connected to the inputs, while the remaining capacitors, CP0 and CN0, are connected to ground (‘0’). Subsequently, the inputs are disconnected from the capacitive DAC, and the bottom plates of the capacitors from the MSB one to the LSB one are loaded with [‘0’, VK, VK]. At this moment, the voltages on the differential DACs are 1/ 4(Vipþ1/2Vref) and 1/4(Vinþ1/2Vref). (2) Since the comparison between 1/4(Vipþ1/2Vref) and 1/4(Vinþ1/2Vref) is equivalent to that between Vip and Vin, the first comparison can be performed directly to determine the MSB bit B2 on the arrival of the clock triggering edge. Note that no switching energy is consumed for the B2 decision. (3) According to the value of B2, the connections of the capacitors are updated. If B2 ¼ ‘1’, the bottom plate of CN2 is switched from ‘0’ to VK, while all the other capacitors remain unchanged. This operation would increase the voltage at the negative side by 1/8Vref, but consume no energy. Therefore, the voltages on the differential DACs are updated to 1/4(Vipþ1/ 2Vref) and 1/4(Vin þ Vref). And the comparison between 1/4(Vipþ1/ 2Vref) and 1/4(Vin þ Vref) is equivalent to that between Vip and (Vinþ1/2Vref). The case of B2 ¼ ‘0’ is dealt with in a similar way. The moment the second triggering edge comes, the second comparison is performed and B1 is set. If B1 ¼ ‘1’, the bottom plate of CP1 is switched from VK to ‘0’, while all the other capacitors remain unchanged. This operation would lower the voltage at the positive side by 1/16Vref. Taking B2¼ B1¼ ‘1’ for example, the voltages on the differential DACs are changed to 1/4(Vipþ1/4Vref) and 1/4(Vin þ Vref). Hence, the
Fig. 2. Proposed switching strategy for 3-bit SAR ADC.
comparison between 1/4(Vipþ1/4Vref) and 1/4(Vin þ Vref) is equivalent to that between Vip and (Vinþ1/2Vrefþ1/4Vref). The case of B1 ¼ ‘0’ is dealt with in a similar way. No switching energy is consumed for the B1 decision either. (4) Once the third triggering edge arrives, the third comparison is activated and the LSB bit B0 is determined. Based on the above analysis, the conclusion that no energy is consumed during the first two comparison cycles can be drawn. In addition, the switching energy consumed by the capacitor can be calculated as follows Eswitching ¼ CVfinal ΔV
(1)
where C is the capacitance of the concerned capacitor, Vfinal represents the reference voltage to which the bottom plate of the concerned capacitor is connected to after switching action, and ΔV is the voltage change across the concerned capacitor. According to (1), the smaller the voltage across the capacitor changes and the lower the involved reference voltage is, the lower switching energy will be required. It can be seen from Fig. 2 that only one capacitor is switched, either from ‘0’ to VK or from VK to ‘0’ in every comparison cycle. Therefore, the proposed switching strategy can be energy-efficient.
Fig. 1. Architecture of the proposed SAR ADC. 25
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Microelectronics Journal 73 (2018) 24–29
simultaneous. In this design, for the purpose of low power and circuit simplification, a binary-weighted capacitive DAC without any calibration/correction is used. Hence, the matching requirement is satisfied by the capacitors themselves. It can be seen from the switching procedure shown in Fig. 2 that the worst case DNL would occur at 1/2FS. By this analogy, a similar conclusion would be drawn for the N-bit resolution case. It can be seen from Fig. 2 that during the transaction between ‘100’ and ‘011’, the voltages across 2 (2N1-1) Cu-elements, are changed by VK at this time, when the greatest number of capacitors are involved. With the fully differential structure, LSB turns out to be Vref/2N1. Assuming the unit capacitor satisfies a nominal value of Cu and a standard deviation of σ(Cu), the maximum DNL error σDNL-MAX can be deduced as follows [5]:
σDNLMAX;the proposed
Fig. 3. Comparison of switching energy versus output for 10-bit SAR ADC.
(3)
A similar conclusion can be drawn for the switching strategy proposed in Ref. [5]:
3.2. Average switching energy and reset energy In the above sub-section, the reason why the average switching energy of the proposed strategy can be improved has been analyzed. However, the so-called reset energy is also consumed once the sampling phase arrives, when the voltages across all the capacitors are reset to the initial states. Since the bottom plates of the capacitors are connected to either the inputs or ‘0’, according to (1), no charge will be supplied by the assistant reference. Consequently, no reset energy is required when the proposed strategy is employed. To demonstrate the energy efficiency of the proposed switching strategy in quantity, a behavioral level simulation for a 10bit SAR ADC that adopts the proposed strategy is performed in MATLAB. And the simulation results of the proposed strategy, together with those of [4,5], are shown in Fig. 3. Obviously, the energy efficiency of the proposed strategy is more energy-efficient. Table 1 summarizes the average switching energy, the average reset energy and percentages of energy saving for each switching strategy. (1) The average switching energy for a 10bit SAR ADC with the strategy proposed in Ref. [5] is 15.8CVref2. However, with the proposed switching strategy, it can be reduced to 7.8CVref2. That is, a reduction of 51% in average switching energy can be achieved. (2) As for the reset energy, no reset energy is required if the proposed strategy is employed. Taking the reset energy into consideration, the total average energy saving (the average switching energy plus the average reset energy) of the proposed strategy can be improved by 83.4%, with respect to that of what proposed in Ref. [5]. Hence, the proposed switching strategy achieves the best power efficiency and reaches the state-of-the-art level. Provided that occurrence of each output code is equiprobable, the average switching energy for an N-bit SAR ADC with the proposed switching strategy can be deduced as: Eaverage ¼
pffiffiffiffiffiffiffiffiffi 2N4 σu LSB Cu
N2 X Ni7 2 2 CVref
σDNLMAX;½5
pffiffiffiffiffiffiffiffiffi 2N1 σu Cu
(4)
A comparison between (3) and (4) leads to the conclusion that the standard deviation of the maximum DNL for the proposed strategy can be pffiffiffi reduced by a factor of 2 2 with respect to that for the switching strategy proposed in Ref. [5]. Provided that the mismatch of the unit capacitor satisfies σ(ΔC/ C) ¼ 1%, the standard deviation of the maximum DNL can be calculated to be 0.057LSB. To verify the correctness of the above derivation, the linearity performance of a 10bit ADC that employs the proposed strategy has been simulated by MATLAB, and the simulation results are presented in Fig. 4. It can be seen that the simulated standard deviation of the maximum DNL is 0.059LSB, which is roughly in accordance with the derived result. Fig. 4 also shows the root-mean-square (RMS) values of the DNL errors and integral-non-linearity (INL) errors for each output code. The maximum root-mean-square (RMS) values of the DNL error and INL error are 0.160 LSB and 0.170LSB, respectively.
3.4. Disadvantages and compromise of the proposed switching strategy Observing from the illustration in Fig. 2, one can arrive at the conclusion that only a differential voltage difference of 1/4LSB will be resulted in for the decision of the LSB bit. So the comparator inputreferred noise should be lower than 1/4LSB. To achieve the low power goal, the supply voltage is reduced so low that the input pair of the comparator is always operated in the weak-inversion region. Consequently, the input-referred noise is inversely proportional with the capacitive loads at the output nodes of the comparator [9]. Therefore, given the power consumed by the comparator, there is a compromise between the comparator input-referred noise and the comparison speed. In this work, the comparator input referred noise is suppressed to be about 0.2 mV, lower than 1/4LSB. Supposing that the assistant reference is chosen to be 1/8ref, even 1/16Vref, etc, though the power consumed by the capacitive DACs can be saved further, the comparator input-referred noise will be required to be much lower. Consequently, either the power consumed by the comparator should be increased, or the capacitive load at the comparator output nodes should be increased with the limited comparator speed, which will limit the ADC throughput in
(2)
i¼1
3.3. Linearity With respect to the SAR ADC, both capacitor mismatch and the employed switching strategy affect the ADC linearity. Though increasing the capacitor areas can significantly improve the matching property, more energy will be consumed and a larger chip area will be occupied Table 1 Switching energy comparison. Switching strategy
Average switching energy
Average switching energy saving
Average reset energy
Total average energy saving
Proposed in Ref. [5] MCS [4] The proposed
15.8CV2ref 84.7CV2ref 7.8CV2ref
Reference – 51%
31.2CV2ref 0 0
Reference – 83.4%
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Microelectronics Journal 73 (2018) 24–29
Fig. 4. Linearity of the proposed strategy for 10-bit SAR ADC.
procedure of the comparator inputs can be illustrated as shown in Fig. 5. It can be seen that the maximum variation of the common-mode input VCOM is equal to 1/16Vref, namely, 37.5 mV. Though the comparator offset is closely related to VCOM, the influence of the comparator offset on the ADC linearity can be neglected, almost making no difference towards the ENOB of the ADC [5]. That the comparator common-mode input stays constant approximately in the conversion phase also means that the least number of charges supplied by the assistant reference will be required. Consequently, the voltage drop of the reference output will be greatly limited, and the negative impact of the assistant reference on the ADC performance will be reduced significantly.
turn. Thus, there also exists a compromise among the voltage value of the assistant reference, the comparator input-referred noise level, the power consumed by the capacitive DACs, the power consumed by the comparator and the ADC throughput. 4. Circuit implementation 4.1. Capacitive DAC and bootstrapped switch In this process, the metal-insulator-metal (MIM) capacitor type is provided. To guarantee high yield, it should be ensured that 3σDNL-MAX is no more than 1/2LSB. According to (3), the capacitance of the unit capacitor can be derived as Cu 18 2N4 KC ⋅K2σ
4.3. SAR logic (5) In order to save power and reduce the circuit complexity, synchronous control logic is always the preferred choice in low-power low-speed ADCs. Now that the bootstrap switch, the comparator and the ADC parameters (the sampling rate and the reference voltage) in this work are identical to those in Ref. [5], a comparison of the power breakdown between this work and [5] will be persuasive to evidence the efficiency of the proposed strategy. In this work, power consumed by the digital logic circuit consumes 8.3 nW, around 47% of the total power. By contrast, the power consumed by the digital logic circuit in Ref. [5] is 8.17 nW, a bit
where KC is the capacitor density parameter, and Kσ is the matching coefficient. In technology, KC and Kσ are 1fF/μm2 and 4.35%μm, respectively. Therefore, a 4 fF unit capacitor will satisfy the matching requirement. To break through the process limitation, the user-defined MIM capacitor is used in order to realize the 4 fF unit capacitor. As Fig. 1 shows, each DAC consists of 512 unit capacitors. Therefore, the capacitive load of each bootstrapped switch is about 2 pF. According to [10], the on-resistance is required to be 280 KΩ at most. The structure of the bootstrapped switch in this work is identical to that employed in Ref. [5]. 4.2. Comparator The dynamic comparator proposed in Ref. [5] is adopted in this work. On the premise that the proposed strategy is employed, the switching
Fig. 5. Waveform of the switching procedure.
Fig. 6. Die photograph of the proposed SAR ADC. 27
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Microelectronics Journal 73 (2018) 24–29
where α, C, VDD and fCLK are the dynamic factor, load capacitance, supply voltage and clock frequency, respectively. So switching power is closely related to the supply voltage and clock frequency. In deep sub-micron technology, the amount of static power would catch up with the dynamic power. Static power is consumed mainly by the leakage current. Increasing channel length, replacing the gate transistors with stacked pairs [11], and using high-Vth transistors are always effective solutions to reduce the leakage current. 5. Measured results The prototype SAR ADC is implemented in 0.18 μm CMOS technology. Fig. 6 shows the die photograph of the proposed ADC and its active area is 370 310 μm2. The capacitive DACs operate on a 0.15 V power supply, while the other blocks are supplied by the 0.6 V reference supply. A breakdown of power for each building block in the ADC is shown in Fig. 7 in detail. It can be seen that the power consumed by the capacitive DACs is reduced to 4.4 nW, about 25% of the total power. The measured DNL and INL values of the proposed ADC are shown in Fig. 8 (a) and (b), respectively. The peak DNL error is þ0.38/-0.3 LSB, while the peak INL error is þ0.3/-0.47 LSB. Fig. 9(a) presents the measured FFT spectrum at 20 kS/s. It can be seen that a SNDR of 56.5 dB and a SFDR of 66.7 dB are achieved. Fig. 9(b) shows the SFDR and SNDR of the proposed ADC with respect to the input frequency fin. At 20 kS/s, the proposed ADC consumes17.7 nW in total, resulting in a figure-of-merit (FOM) of 1.6fJ/conversion-step. Table 2 summarizes the performance of the proposed ADC and shows a comparison to other state-of-the-art SAR ADCs [5–7],[12,13]. It can be seen clearly that the proposed SAR ADC achieves the best results.
Fig. 7. Power consumption for each function block.
lower than that of this work. Considering that the total power of the proposed ADC is reduced to 17.7 nW, accounting for nearly 46.6% of that of [5], one can draw the conclusion that: (1) the proposed solution is very effective in saving power consumed by the DACs; (2) the ongoing research emphasis on the low-power SAR ADC should be on how to reduce the power consumed by digital cells. Power consumed by digital cells consists of static power and dynamic power. And dynamic power is mainly consumed when the switchingstate is changed, namely, switching power. Switching power can be expressed as: PSWITCH ¼ α⋅C⋅VDD2 ⋅f CLK
(6)
Fig. 8. Linearity measurement.
Fig. 9. Measured dynamic performance.
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Microelectronics Journal 73 (2018) 24–29
Table 2 Performance summary and comparison.
Technology Resolution (bit) Supply (V) Sampling rate (KHz) Power (nW) DNL/INL(LSB) ENOB (bits) FOM (fJ/Con.-step)
[5] TCAS.I0 2015
[6] TCAS.II0 2015
[7] TCAS.II0 2016
[12] TCAS.I0 2016
[13] TCAS.II0 2016
This work
180 nm 10 0.6 20 38 0.46/0.44 9.4 2.8
110 nm 10 1 20 100 0.44/0.58 9.1 9.1
180 nm 10 0.8 200 200 0.5/1 9.05 1.88
180 nm 10 0.6 200 2010 0.29/0.8 9.3 15.51
65 nm 8 0.4 1 0.717 0.35/0.36 7.81 3.19
180 nm 10 0.6/0.15 20 17.7 0.38/0.47 9.1 1.6
6. Conclusions
[3] Guan-Ying Huang, et al., 10-bit 30-MS/s SAR ADC using a switchback switching method, IEEE Trans. Very Large Scale Integration (VLSI) Syst. 21 (2013) 584–588. [4] V. Hariprasath, J. Guerber, S.-H. Lee, U.-K. Moon, Merged capacitor switching based SAR ADC with highest switching energy-efficiency, Electron. Lett. 46 (2010) 620–621. [5] Zhangming Zhu, Yuhua Liang, A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in 0.18μm CMOS for medical implant devices, IEEE Trans. Circuits Syst. I: Reg. Papers 62 (2015) 2167–2176. [6] Hokyu Lee, et al., A 100-nW 9.1-ENOB 20-kS/s SARADC for portable pulse oximeter, IEEE Trans. Circuits Syst. II Exp. Briefs 62 (2015) 357–361. [7] Yulin Zhang, et al., A 10-bit, 200-kS/s, 250-nA self-clocked coarse-fine SAR ADC, IEEE Trans. Circuits Syst. II Exp. Briefs 63 (2016) 924–928. [8] Ji-Yong Um, et al., A digital-domain calibration of split-capacitor DAC for a differential SAR ADC without additional analog circuits, IEEE Trans. Circuits Syst. I: Reg. Papers 60 (2013) 2845–2856. [9] M. Van Elzakker, et al., A 10-bit charge-redistribution ADC consuming 1.9 W at 1 ms/s, IEEE J. Solid State Circ. 45 (2010) 1007–1015. [10] Dai Zhang, et al., A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13μm CMOS for medical implant devices, IEEE J. Solid State Circ. 47 (2012) 1585–1593. [11] S. Narendra, et al., Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-um CMOS, IEEE J. Solid State Circ. 39 (2004) 501–510. [12] Yan Song, et al., A 0.6-V 10-bit 200-kS/s fully differential SAR ADC with incremental converting algorithm for energy efficient applications, IEEE Trans. Circuits Syst. I: Reg. Papers 63 (2016) 449–458. [13] Prakash Harikumar, et al., A 0.4 V, sub-nW, 8-bit 1 kS/s SAR ADC in 65 nm CMOS for wireless sensor applications, IEEE Trans. Circuits Syst. II Exp. Briefs 63 (2016) 743–747.
A 10bit 20 kS/s 9.1ENOB SAR ADC employing an energy-efficient and highly-linear capacitor switching strategy is designed in 0.18 μm CMOS process. At the supplies of 0.6 V/0.15 V, the ADC consumes 11.7 nW overall, resulting in a figure-of-merit (FOM) of 1.6fJ/conversion-step. The SNDR and the SFDR of the proposed ADC are 56.5dBand 66.7 dB, respectively. The core area of the designed ADC is and 370 310 μm2. Acknowledgments This work was supported by the National Natural Science Foundation of China (61604111, 61625403), the China Postdoctoral Science Foundation (2016M602772). References [1] Chun-Cheng Liu, et al., A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process, in: IEEE Symp. VLSI Circuits Dig., 2009, pp. 236–237. [2] Yan Zhu, et al., A 10-bit 100MS/s reference-free SAR ADC in 90 nm CMOS, IEEE J. Solid State Circ. 45 (2010) 1111–1121.
29
Contents lists available at ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
A 10bit 20 kS/s 17.7 nW 9.1ENOB reference-insensitive SAR ADC in 0.18 μm CMOS Yuhua Liang, Zhangming Zhu * School of Microelectronics, Xidian University, Xi'an, 710071, China
A R T I C L E I N F O
A B S T R A C T
Keywords: SAR ADC Low power Switching scheme
This paper presents a 10bit 20 kS/s 9.1ENOB SAR ADC employing an energy-efficient and highly-linear capacitor switching strategy in 0.18 μm CMOS process. The SAR ADC with this proposed strategy features better linearity due to the use of a relatively lower assistant reference, the value of which is equivalent to a quarter of the input swing. In addition, the accuracy of the assistant reference has no impact on the ADC performance, since only this assistant reference will be involved with the capacitive DACs during the conversion period. The ADC is powered by the supplies of 0.6 V/0.15 V. The capacitive DACs are supplied by the 0.15 V assistant reference, while the other blocks are powered by the 0.6 V reference. In this case, the ADC consumes 11.7 nW overall, resulting in a figure-of-merit (FOM) of 1.6fJ/conversion-step. At a 20-kS/s output rate, the measured results show the proposed SAR ADC performs a peak signal-to-noise-and-distortion ratio (SNDR) of 56.5 dB, a peak spurious-free-dynamicrange (SFDR) of 66.7 dB. The core area of the designed ADC is and 370 310 μm2.
1. Introduction Owing to the advantages of simple structure, minimal usage of analog block and energy-efficiency, SAR ADCs are the optimal choice in many low-power application areas. Moreover, SAR ADCs feature high compatibility with the increasingly scaling-down semiconductor manufacturing process and can work at low supply voltages. These advantages endow SAR ADCs with the possibility to become a trend as the semiconductor manufacturing process develops. Among the function blocks in an SAR ADC, the capacitive DACs are always a major contributor to the power consumption. And the employed switching strategy is a major factor of the power consumed by the capacitive DACs. During the past several years, researchers all over the world endeavored themselves to improve the power efficiency of the SAR ADCs with efficient switching schemes [1–7]. It is noted that the effectiveness of the schemes in Refs. [6,7] are inferior to that of what proposed in Ref. [5]. Compared with the scheme proposed in Ref. [5], the switching energy of the proposed scheme can be reduced by 51% approximately. When the reset energy is taken into consideration, a reduction of 83.4% is achieved in total. It is known that the linearity of the SAR ADC depends on both the matching property of the DACs and the employed switching strategy.
Thanks to the utilization of 1/4Vref (rather than Vcm ¼ 1/2Vref or Vref) in the conversion period, the linearity of an SAR ADC that adopts the proposed approach can be improved significantly. On condition of the same unit capacitor, the standard deviation of the maximum differentialnon-linearity (DNL) for the proposed strategy can be reduced to a quarter of that for the set-and-down strategy. Observing the quantization process of the Vcm-involved strategies [2–5], we arrive at the conclusion that any mismatch between Vcm and Vref can degrade the ADC performance. Provided that the proposed strategy is employed, only the assistant reference 1/4Vref will be involved in the conversion course. Therefore, not only can the power efficiency be improved, but also the ADC performance is immune to the inaccuracy of the assistant reference. To verify the advantages of the proposed switching strategy, a 10bit 0.6Vpp 20 kS/s SAR ADC is fabricated in 0.18 μm CMOS technology. The capacitive DACs are powered by the 0.15 V assistant reference, which is a quarter of the swing of the inputs. Detailed descriptions and discussions will be given in the following sections. 2. Architecture design The diagram of the proposed SAR ADC is shown in Fig. 1. It is composed of two differential binary-weighted capacitive DACs, two
* Corresponding author. E-mail address: [email protected] (Z. Zhu). https://doi.org/10.1016/j.mejo.2018.01.006 Received 4 January 2017; Received in revised form 7 November 2017; Accepted 8 January 2018 0026-2692/© 2018 Elsevier Ltd. All rights reserved.
Y. Liang, Z. Zhu
Microelectronics Journal 73 (2018) 24–29
bootstrapped switches, a synchronous SAR digital logic circuit, and a dynamic latch comparator. The binary-weighted architecture is always a popular choice for DAC design since the matching requirement can be met more easily, compared with the split architecture [8]. The dynamic latch comparator compares the successive-approximation voltages on differential capacitor arrays and determines the values of the output code bit-by-bit. After decoding the comparator output, the SAR logic controls the switches to realize the employed switching strategy. For an N-bit SAR ADC, completion of one conversion always requires N comparisons. In addition, a differential architecture is employed to suppress the common-mode noise. 3. Proposed switching strategy 3.1. Proposed switching procedure and linearity The proposed switching strategy for a 3bit SAR ADC is illustrated in Fig. 2. VK, here, representing the assistant reference here, is equal to 1/ 4Vref (Vref represents the traditional reference voltage, and all blocks but the capacitive DACs are supplied by Vref). Though equal to Vref in the ideal case, the input swing of Vip/Vin is actually scaled down in a small degree owing to the existence of the parasitic capacitance). (1) In the sampling phase, the inputs are sampled on the top plates of the capacitors. Meanwhile, the MSB capacitors and (MSB-1) capacitors, CP2, CP1, CN2 and CN1, are also connected to the inputs, while the remaining capacitors, CP0 and CN0, are connected to ground (‘0’). Subsequently, the inputs are disconnected from the capacitive DAC, and the bottom plates of the capacitors from the MSB one to the LSB one are loaded with [‘0’, VK, VK]. At this moment, the voltages on the differential DACs are 1/ 4(Vipþ1/2Vref) and 1/4(Vinþ1/2Vref). (2) Since the comparison between 1/4(Vipþ1/2Vref) and 1/4(Vinþ1/2Vref) is equivalent to that between Vip and Vin, the first comparison can be performed directly to determine the MSB bit B2 on the arrival of the clock triggering edge. Note that no switching energy is consumed for the B2 decision. (3) According to the value of B2, the connections of the capacitors are updated. If B2 ¼ ‘1’, the bottom plate of CN2 is switched from ‘0’ to VK, while all the other capacitors remain unchanged. This operation would increase the voltage at the negative side by 1/8Vref, but consume no energy. Therefore, the voltages on the differential DACs are updated to 1/4(Vipþ1/ 2Vref) and 1/4(Vin þ Vref). And the comparison between 1/4(Vipþ1/ 2Vref) and 1/4(Vin þ Vref) is equivalent to that between Vip and (Vinþ1/2Vref). The case of B2 ¼ ‘0’ is dealt with in a similar way. The moment the second triggering edge comes, the second comparison is performed and B1 is set. If B1 ¼ ‘1’, the bottom plate of CP1 is switched from VK to ‘0’, while all the other capacitors remain unchanged. This operation would lower the voltage at the positive side by 1/16Vref. Taking B2¼ B1¼ ‘1’ for example, the voltages on the differential DACs are changed to 1/4(Vipþ1/4Vref) and 1/4(Vin þ Vref). Hence, the
Fig. 2. Proposed switching strategy for 3-bit SAR ADC.
comparison between 1/4(Vipþ1/4Vref) and 1/4(Vin þ Vref) is equivalent to that between Vip and (Vinþ1/2Vrefþ1/4Vref). The case of B1 ¼ ‘0’ is dealt with in a similar way. No switching energy is consumed for the B1 decision either. (4) Once the third triggering edge arrives, the third comparison is activated and the LSB bit B0 is determined. Based on the above analysis, the conclusion that no energy is consumed during the first two comparison cycles can be drawn. In addition, the switching energy consumed by the capacitor can be calculated as follows Eswitching ¼ CVfinal ΔV
(1)
where C is the capacitance of the concerned capacitor, Vfinal represents the reference voltage to which the bottom plate of the concerned capacitor is connected to after switching action, and ΔV is the voltage change across the concerned capacitor. According to (1), the smaller the voltage across the capacitor changes and the lower the involved reference voltage is, the lower switching energy will be required. It can be seen from Fig. 2 that only one capacitor is switched, either from ‘0’ to VK or from VK to ‘0’ in every comparison cycle. Therefore, the proposed switching strategy can be energy-efficient.
Fig. 1. Architecture of the proposed SAR ADC. 25
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simultaneous. In this design, for the purpose of low power and circuit simplification, a binary-weighted capacitive DAC without any calibration/correction is used. Hence, the matching requirement is satisfied by the capacitors themselves. It can be seen from the switching procedure shown in Fig. 2 that the worst case DNL would occur at 1/2FS. By this analogy, a similar conclusion would be drawn for the N-bit resolution case. It can be seen from Fig. 2 that during the transaction between ‘100’ and ‘011’, the voltages across 2 (2N1-1) Cu-elements, are changed by VK at this time, when the greatest number of capacitors are involved. With the fully differential structure, LSB turns out to be Vref/2N1. Assuming the unit capacitor satisfies a nominal value of Cu and a standard deviation of σ(Cu), the maximum DNL error σDNL-MAX can be deduced as follows [5]:
σDNLMAX;the proposed
Fig. 3. Comparison of switching energy versus output for 10-bit SAR ADC.
(3)
A similar conclusion can be drawn for the switching strategy proposed in Ref. [5]:
3.2. Average switching energy and reset energy In the above sub-section, the reason why the average switching energy of the proposed strategy can be improved has been analyzed. However, the so-called reset energy is also consumed once the sampling phase arrives, when the voltages across all the capacitors are reset to the initial states. Since the bottom plates of the capacitors are connected to either the inputs or ‘0’, according to (1), no charge will be supplied by the assistant reference. Consequently, no reset energy is required when the proposed strategy is employed. To demonstrate the energy efficiency of the proposed switching strategy in quantity, a behavioral level simulation for a 10bit SAR ADC that adopts the proposed strategy is performed in MATLAB. And the simulation results of the proposed strategy, together with those of [4,5], are shown in Fig. 3. Obviously, the energy efficiency of the proposed strategy is more energy-efficient. Table 1 summarizes the average switching energy, the average reset energy and percentages of energy saving for each switching strategy. (1) The average switching energy for a 10bit SAR ADC with the strategy proposed in Ref. [5] is 15.8CVref2. However, with the proposed switching strategy, it can be reduced to 7.8CVref2. That is, a reduction of 51% in average switching energy can be achieved. (2) As for the reset energy, no reset energy is required if the proposed strategy is employed. Taking the reset energy into consideration, the total average energy saving (the average switching energy plus the average reset energy) of the proposed strategy can be improved by 83.4%, with respect to that of what proposed in Ref. [5]. Hence, the proposed switching strategy achieves the best power efficiency and reaches the state-of-the-art level. Provided that occurrence of each output code is equiprobable, the average switching energy for an N-bit SAR ADC with the proposed switching strategy can be deduced as: Eaverage ¼
pffiffiffiffiffiffiffiffiffi 2N4 σu LSB Cu
N2 X Ni7 2 2 CVref
σDNLMAX;½5
pffiffiffiffiffiffiffiffiffi 2N1 σu Cu
(4)
A comparison between (3) and (4) leads to the conclusion that the standard deviation of the maximum DNL for the proposed strategy can be pffiffiffi reduced by a factor of 2 2 with respect to that for the switching strategy proposed in Ref. [5]. Provided that the mismatch of the unit capacitor satisfies σ(ΔC/ C) ¼ 1%, the standard deviation of the maximum DNL can be calculated to be 0.057LSB. To verify the correctness of the above derivation, the linearity performance of a 10bit ADC that employs the proposed strategy has been simulated by MATLAB, and the simulation results are presented in Fig. 4. It can be seen that the simulated standard deviation of the maximum DNL is 0.059LSB, which is roughly in accordance with the derived result. Fig. 4 also shows the root-mean-square (RMS) values of the DNL errors and integral-non-linearity (INL) errors for each output code. The maximum root-mean-square (RMS) values of the DNL error and INL error are 0.160 LSB and 0.170LSB, respectively.
3.4. Disadvantages and compromise of the proposed switching strategy Observing from the illustration in Fig. 2, one can arrive at the conclusion that only a differential voltage difference of 1/4LSB will be resulted in for the decision of the LSB bit. So the comparator inputreferred noise should be lower than 1/4LSB. To achieve the low power goal, the supply voltage is reduced so low that the input pair of the comparator is always operated in the weak-inversion region. Consequently, the input-referred noise is inversely proportional with the capacitive loads at the output nodes of the comparator [9]. Therefore, given the power consumed by the comparator, there is a compromise between the comparator input-referred noise and the comparison speed. In this work, the comparator input referred noise is suppressed to be about 0.2 mV, lower than 1/4LSB. Supposing that the assistant reference is chosen to be 1/8ref, even 1/16Vref, etc, though the power consumed by the capacitive DACs can be saved further, the comparator input-referred noise will be required to be much lower. Consequently, either the power consumed by the comparator should be increased, or the capacitive load at the comparator output nodes should be increased with the limited comparator speed, which will limit the ADC throughput in
(2)
i¼1
3.3. Linearity With respect to the SAR ADC, both capacitor mismatch and the employed switching strategy affect the ADC linearity. Though increasing the capacitor areas can significantly improve the matching property, more energy will be consumed and a larger chip area will be occupied Table 1 Switching energy comparison. Switching strategy
Average switching energy
Average switching energy saving
Average reset energy
Total average energy saving
Proposed in Ref. [5] MCS [4] The proposed
15.8CV2ref 84.7CV2ref 7.8CV2ref
Reference – 51%
31.2CV2ref 0 0
Reference – 83.4%
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Fig. 4. Linearity of the proposed strategy for 10-bit SAR ADC.
procedure of the comparator inputs can be illustrated as shown in Fig. 5. It can be seen that the maximum variation of the common-mode input VCOM is equal to 1/16Vref, namely, 37.5 mV. Though the comparator offset is closely related to VCOM, the influence of the comparator offset on the ADC linearity can be neglected, almost making no difference towards the ENOB of the ADC [5]. That the comparator common-mode input stays constant approximately in the conversion phase also means that the least number of charges supplied by the assistant reference will be required. Consequently, the voltage drop of the reference output will be greatly limited, and the negative impact of the assistant reference on the ADC performance will be reduced significantly.
turn. Thus, there also exists a compromise among the voltage value of the assistant reference, the comparator input-referred noise level, the power consumed by the capacitive DACs, the power consumed by the comparator and the ADC throughput. 4. Circuit implementation 4.1. Capacitive DAC and bootstrapped switch In this process, the metal-insulator-metal (MIM) capacitor type is provided. To guarantee high yield, it should be ensured that 3σDNL-MAX is no more than 1/2LSB. According to (3), the capacitance of the unit capacitor can be derived as Cu 18 2N4 KC ⋅K2σ
4.3. SAR logic (5) In order to save power and reduce the circuit complexity, synchronous control logic is always the preferred choice in low-power low-speed ADCs. Now that the bootstrap switch, the comparator and the ADC parameters (the sampling rate and the reference voltage) in this work are identical to those in Ref. [5], a comparison of the power breakdown between this work and [5] will be persuasive to evidence the efficiency of the proposed strategy. In this work, power consumed by the digital logic circuit consumes 8.3 nW, around 47% of the total power. By contrast, the power consumed by the digital logic circuit in Ref. [5] is 8.17 nW, a bit
where KC is the capacitor density parameter, and Kσ is the matching coefficient. In technology, KC and Kσ are 1fF/μm2 and 4.35%μm, respectively. Therefore, a 4 fF unit capacitor will satisfy the matching requirement. To break through the process limitation, the user-defined MIM capacitor is used in order to realize the 4 fF unit capacitor. As Fig. 1 shows, each DAC consists of 512 unit capacitors. Therefore, the capacitive load of each bootstrapped switch is about 2 pF. According to [10], the on-resistance is required to be 280 KΩ at most. The structure of the bootstrapped switch in this work is identical to that employed in Ref. [5]. 4.2. Comparator The dynamic comparator proposed in Ref. [5] is adopted in this work. On the premise that the proposed strategy is employed, the switching
Fig. 5. Waveform of the switching procedure.
Fig. 6. Die photograph of the proposed SAR ADC. 27
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where α, C, VDD and fCLK are the dynamic factor, load capacitance, supply voltage and clock frequency, respectively. So switching power is closely related to the supply voltage and clock frequency. In deep sub-micron technology, the amount of static power would catch up with the dynamic power. Static power is consumed mainly by the leakage current. Increasing channel length, replacing the gate transistors with stacked pairs [11], and using high-Vth transistors are always effective solutions to reduce the leakage current. 5. Measured results The prototype SAR ADC is implemented in 0.18 μm CMOS technology. Fig. 6 shows the die photograph of the proposed ADC and its active area is 370 310 μm2. The capacitive DACs operate on a 0.15 V power supply, while the other blocks are supplied by the 0.6 V reference supply. A breakdown of power for each building block in the ADC is shown in Fig. 7 in detail. It can be seen that the power consumed by the capacitive DACs is reduced to 4.4 nW, about 25% of the total power. The measured DNL and INL values of the proposed ADC are shown in Fig. 8 (a) and (b), respectively. The peak DNL error is þ0.38/-0.3 LSB, while the peak INL error is þ0.3/-0.47 LSB. Fig. 9(a) presents the measured FFT spectrum at 20 kS/s. It can be seen that a SNDR of 56.5 dB and a SFDR of 66.7 dB are achieved. Fig. 9(b) shows the SFDR and SNDR of the proposed ADC with respect to the input frequency fin. At 20 kS/s, the proposed ADC consumes17.7 nW in total, resulting in a figure-of-merit (FOM) of 1.6fJ/conversion-step. Table 2 summarizes the performance of the proposed ADC and shows a comparison to other state-of-the-art SAR ADCs [5–7],[12,13]. It can be seen clearly that the proposed SAR ADC achieves the best results.
Fig. 7. Power consumption for each function block.
lower than that of this work. Considering that the total power of the proposed ADC is reduced to 17.7 nW, accounting for nearly 46.6% of that of [5], one can draw the conclusion that: (1) the proposed solution is very effective in saving power consumed by the DACs; (2) the ongoing research emphasis on the low-power SAR ADC should be on how to reduce the power consumed by digital cells. Power consumed by digital cells consists of static power and dynamic power. And dynamic power is mainly consumed when the switchingstate is changed, namely, switching power. Switching power can be expressed as: PSWITCH ¼ α⋅C⋅VDD2 ⋅f CLK
(6)
Fig. 8. Linearity measurement.
Fig. 9. Measured dynamic performance.
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Table 2 Performance summary and comparison.
Technology Resolution (bit) Supply (V) Sampling rate (KHz) Power (nW) DNL/INL(LSB) ENOB (bits) FOM (fJ/Con.-step)
[5] TCAS.I0 2015
[6] TCAS.II0 2015
[7] TCAS.II0 2016
[12] TCAS.I0 2016
[13] TCAS.II0 2016
This work
180 nm 10 0.6 20 38 0.46/0.44 9.4 2.8
110 nm 10 1 20 100 0.44/0.58 9.1 9.1
180 nm 10 0.8 200 200 0.5/1 9.05 1.88
180 nm 10 0.6 200 2010 0.29/0.8 9.3 15.51
65 nm 8 0.4 1 0.717 0.35/0.36 7.81 3.19
180 nm 10 0.6/0.15 20 17.7 0.38/0.47 9.1 1.6
6. Conclusions
[3] Guan-Ying Huang, et al., 10-bit 30-MS/s SAR ADC using a switchback switching method, IEEE Trans. Very Large Scale Integration (VLSI) Syst. 21 (2013) 584–588. [4] V. Hariprasath, J. Guerber, S.-H. Lee, U.-K. Moon, Merged capacitor switching based SAR ADC with highest switching energy-efficiency, Electron. Lett. 46 (2010) 620–621. [5] Zhangming Zhu, Yuhua Liang, A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in 0.18μm CMOS for medical implant devices, IEEE Trans. Circuits Syst. I: Reg. Papers 62 (2015) 2167–2176. [6] Hokyu Lee, et al., A 100-nW 9.1-ENOB 20-kS/s SARADC for portable pulse oximeter, IEEE Trans. Circuits Syst. II Exp. Briefs 62 (2015) 357–361. [7] Yulin Zhang, et al., A 10-bit, 200-kS/s, 250-nA self-clocked coarse-fine SAR ADC, IEEE Trans. Circuits Syst. II Exp. Briefs 63 (2016) 924–928. [8] Ji-Yong Um, et al., A digital-domain calibration of split-capacitor DAC for a differential SAR ADC without additional analog circuits, IEEE Trans. Circuits Syst. I: Reg. Papers 60 (2013) 2845–2856. [9] M. Van Elzakker, et al., A 10-bit charge-redistribution ADC consuming 1.9 W at 1 ms/s, IEEE J. Solid State Circ. 45 (2010) 1007–1015. [10] Dai Zhang, et al., A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13μm CMOS for medical implant devices, IEEE J. Solid State Circ. 47 (2012) 1585–1593. [11] S. Narendra, et al., Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-um CMOS, IEEE J. Solid State Circ. 39 (2004) 501–510. [12] Yan Song, et al., A 0.6-V 10-bit 200-kS/s fully differential SAR ADC with incremental converting algorithm for energy efficient applications, IEEE Trans. Circuits Syst. I: Reg. Papers 63 (2016) 449–458. [13] Prakash Harikumar, et al., A 0.4 V, sub-nW, 8-bit 1 kS/s SAR ADC in 65 nm CMOS for wireless sensor applications, IEEE Trans. Circuits Syst. II Exp. Briefs 63 (2016) 743–747.
A 10bit 20 kS/s 9.1ENOB SAR ADC employing an energy-efficient and highly-linear capacitor switching strategy is designed in 0.18 μm CMOS process. At the supplies of 0.6 V/0.15 V, the ADC consumes 11.7 nW overall, resulting in a figure-of-merit (FOM) of 1.6fJ/conversion-step. The SNDR and the SFDR of the proposed ADC are 56.5dBand 66.7 dB, respectively. The core area of the designed ADC is and 370 310 μm2. Acknowledgments This work was supported by the National Natural Science Foundation of China (61604111, 61625403), the China Postdoctoral Science Foundation (2016M602772). References [1] Chun-Cheng Liu, et al., A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process, in: IEEE Symp. VLSI Circuits Dig., 2009, pp. 236–237. [2] Yan Zhu, et al., A 10-bit 100MS/s reference-free SAR ADC in 90 nm CMOS, IEEE J. Solid State Circ. 45 (2010) 1111–1121.
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