- Email: [email protected]
s asynchronous SAR ADC with pre-settling procedure in 65 nm CMOS
Microelectronics Journal 45 (2014) 880–885
Contents lists available at ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
A single-channel 8-bit 660 MS/s asynchronous SAR ADC with pre-settling procedure in 65 nm CMOS Zhangming Zhu n, Minjie Liu, Qiyu Wang, Yintang Yang School of Microelectronics, Xidian University, Xi'an 710071, China
art ic l e i nf o
a b s t r a c t
Article history: Received 15 September 2013 Received in revised form 24 April 2014 Accepted 25 April 2014 Available online 23 May 2014
A single-channel 8-bit low-power high-speed SAR ADC with a novel pre-settling procedure is presented in this paper. The proposed procedure relaxes the settling time significantly and improves the speed of the ADC. Moreover, the asynchronous technique avoids the high frequency internal clocks and further increases the speed of the SAR ADC. Based on SMIC 65 nm 1.2-V CMOS technology, the simulation results demonstrate that DNL and INL are 0.4/0.4 LSBs and 0.9/0.8 LSBs, respectively. At 660 MS/s sampling rate, the ADC consumes 7.6 mW from a 1.2 V supply. The proposed SAR ADC's SNDR and SFDR are 49.5 dB and 64.2 dB, respectively. & 2014 Elsevier Ltd. All rights reserved.
Keywords: Successive approximation register (SAR) A/D converter High speed CMOS Asynchronous logic circuits Pre-setting procedure
1. Introduction Achieving a moderate resolution, high speed and low power, successive approximation register (SAR) ADCs are usually employed in communication systems such as UWB, mm-wave and serial link transceivers. Because of the improvement of the CMOS process, hundreds of megabytes of sample speed can be attained in 6 to 10 bits [1,2] by SAR ADCs. Additionally, SAR ADCs take advantage of time interleaved [3] due to its excellent energy efficiency. The two major limitations of the speed of SAR ADCs are the settling time of the DAC and the speed of the comparator. Obviously, conventional SAR ADCs have a logarithmic dependence on resolution, but they consume multiple clock cycle to implement the conversion algorithm. Thus, an asynchronous ADC architecture is proposed to speed up the power-efficient SAR algorithm described in [4,5]. The profit from the asynchronous architecture, the power efficiency and the area of the high-speed ADC in [4,5] have been optimized. However, the problem of the DAC settling time still exists.
n
Corresponding author. E-mail addresses: [email protected] (Z. Zhu), [email protected] (M. Liu), [email protected] (Q. Wang), [email protected] (Y. Yang). http://dx.doi.org/10.1016/j.mejo.2014.04.039 0026-2692/& 2014 Elsevier Ltd. All rights reserved.
In this paper, to improve the speed of ADCs, a novel energyefficient procedure named “pre-settling”, which can relax the settling time of the DAC completely, is proposed. A dynamic comparator and clock generation are utilized to achieve high-speed operation.
cmp1 T&H
DAC[2] T&H
clk
Clock generation
Decide[1] cmp3 Clock generation
DAC3
DAC[0]
cmp3 cmp2 cmp1
Decide[2] cmp2
DAC2
DAC[1] T&H
Clock generation
DAC1
Decide[0]
Decide[2:0] cmp
Memory
DAC[2:0]
LOGIC
Fig. 1. The architecture of the proposed ADC.
cmp
Z. Zhu et al. / Microelectronics Journal 45 (2014) 880–885
Furthermore, asynchronous processing is used to shorten the total conversion time. The paper is organized as follows. Section 2 describes the proposed ADC architecture and the pre-settling procedure. Section 3 presents the detailed circuit design of the ADC. The simulation performances of the ADC are presented in Section 4.
synchronous … MSB
MSB-1
LSB
asynchronous … MSB
Sampling
MSB-1
881
LSB
Conversion
2. Architecture design
ck tcomp
C MP
tready ck tDAC
DAC
Fig. 2. Synchronous processing and asynchronous processing in [7].
Fig. 1 shows the architecture of the proposed ADC. With the pre-settling procedure and asynchronous clock, based on our previous design [6], the sample rate of the proposed SAR ADC is improved from 208 MHz to 660 MHz. The architecture incorporates T&H circuit, DAC, comparator and clock generation. Through an OR gate, three results from the comparators can be transferred to the memory and logic in turn. Thus, the final 8-bit codes are obtained. Fig. 2 shows synchronous processing and asynchronous processing with an unequal time interval. A synchronous approach relies on a clock to divide the conversion phase into equal timeslot as the conversion proceeds from MSB to LSB. However, asynchronous processing makes the average of the total conversion time significantly shorter with unequal time intervals. The high-speed internal clock is also avoided. Fig. 2 shows the critical path for one-bit conversion of the SAR ADC architecture in [7]. N comparators for N-bit conversion are used to store each comparison result into the digital output of each comparator. These digital outputs are utilized simultaneously in two parallel paths: one flows directly to the capacitive DAC, and the other flows to a digital clock generator that detects the completion of the
Comparion
Pre-settling+
Pre-settlingPre-settling+
Comparison
Cmp=1 Cmp=0 Pre-settling+
Pre-settlingDAC1
Comparison
DAC2
Pre-settling+
DAC3
Pre-settling-
Pre-settling-
Cmp=1
Comparsion
Cmp=0
Comparison
Pre-settling+ Pre-settling+
Pre-settling-
Cmp=1 Pre-settling-
Comparsion
Cmp=0 Pre-settling+ Comparsion
Pre-settling-
Fig. 3. Proposed procedure.
882
Z. Zhu et al. / Microelectronics Journal 45 (2014) 880–885
current quantization and generates a “ready” signal to clock the next quantization. Both paths occur simultaneously. Then, the critical path is reduced to [7]. T critical ¼ t comp þ max ½t ready ; t DAC : For this asynchronous algorithm, the settling time of the DAC still limits the speed, and N comparators consume more power. Fig. 3 shows a 3-bit example of the proposed procedure. The proposed procedure can be performed by three DACs and comparators to relax the settling time of the DACs completely. As in Fig. 3, Fig. 4 shows that, at the start of the sampling phase, the switches of the three DACs are set to the same state. At the holding phase, the bootstrapped switch is opened and DAC1 with its comparator starts the first comparison. Meanwhile, DAC2 and DAC3 are set to different states for the next comparison. By the end of the first comparison, the outputs of the comparator trigger a clock pulse by the clock generation. Then, the DAC and comparator in the next comparison are chosen by the logic signal DAC o2:0 4 and Decide o2:0 4, which depend on the results of the first comparison. If the result of the comparison is high, DAC2 with its comparator will start the second comparison, while DAC1 and DAC3 will be set to the pre-settling state. Otherwise, DAC3 will be used for comparison. This procedure can be repeated until the successive conversion is complete. After the last comparison, all the DACs will be reset for the sampling phase. In the proposed procedure, the settling time of the DAC has no effect on the speed of the ADC. Fig. 4 shows the asynchronous clock used in this paper. Clearly, the speed of the proposed ADC is only limit by the comparator. In the pre-settling procedure, each cycle of the proposed SAR ADC is about half the duration of a conventional cycle. The simulation results (Section 4) show that this procedure can achieve low power consumption and high accuracy at a high sampling rate.
3. Circuit implementation The implementation details of the S/H circuit, comparator and the clock generation are presented in this section. These components are critical to the speed, power consumption, and accuracy of the ADC. The design considerations of the building blocks are described in the following subsections.
3.1. S/H circuit The function of the S/H circuit is achieved by a bootstrapped switch and a DAC. As mentioned above, sampling on the top plates of the capacitors offers a better performance in speed. The substrate coupling noise can be rejected by differential sampling [8]. However, the charge injection will have a critical effect on accuracy due to the device in the deep sub-micron technology. We can regard the different charge injections in the differential sides as a noise signal. Differential sampling could cancel the even harmonic components. Consequently, a differential sampling is significant. Fig. 5 shows the DAC of the SAR ADC. To achieve a better linearity, a binary-weighted capacitor carry, described in [6], is employed in the DAC. As in the switching process in [6], a good common-mode noise rejection and a high accuracy can be achieved. The unit capacitance is 4 fF, which is small enough to ensure that the pre-settling time is shorter than the comparison time.
cmp+ cmpclk
1.3 1.2 1.1 1.0 0.9
Sample
0.8 com
d
pre
d
re
pre
d
re
d
re
0.7
V
DAC1 DAC2
pre
DAC3
pre
com
d
0.6 0.5 0.4 0.3 0.2
com--comparison
0.1
d—digtal delay
delay
0.0 Pre—pre-settling
-0.1
t
Re—reset phase
Fig. 4. Asynchronous clock.
Fig. 6. Schematic and waveform of a conventional comparator.
GND Vref
Cdummy
C6 C5
C4
C3
C2
C1
C0
C0
Vip SAR logic
Vin Cdummy
C6 C5
C4
C3
C2
C1
C0
C0
Vref GND Fig. 5. Schematic of DAC.
Z. Zhu et al. / Microelectronics Journal 45 (2014) 880–885
883
VDD
VDD
clk
clk
CmpCmp+
VP
M1
M3
ref+
ref-
M4
M2
VN
clkb
clk
Fig. 7. Schematic of the proposed comparator.
1.3 1.2
ref+
cmp+ cmpclk
ref
-
5b DAC logic
1.1
cm
1.0 0.9
cm
0.8
clk
V
0.7
Fig. 9. Circuit of the comparator calibration.
0.6 0.5 0.4 0.3 0.2 0.1
Cmp-
clk
Cmp+
0.0
FB
-0.1
t
clk rd
Fig. 8. Waveform of the proposed comparator.
M1 ~FB
reset
3.2. Comparator with offset calibration Fig. 6 shows the waveform of a conventional comparator. When the clock switches to high, the currents flowing in the latch charge the output nodes at different rates depending on the values of the input voltages. When one of the output voltages reaches the threshold voltage VDD |Vthp| of the PMOS, a feedback operation starts and the two outputs eventually reach VDD and ground. When the clock is high, the comparator works at the comparison phase. In the pre-amplify phase, the regeneration latch is reset to | VDD Vthp|. In the comparison phase, the regeneration latch compares the amplified voltage. The delay can be calculated as the time difference from the start time of the comparison to the time when the output reaches the threshold voltage. Fig. 7 shows the comparator employed in this ADC. The comparator is composed of two stages, an amplification stage and a regenerative stage. Based on the comparator in [9], the comparator calibration is proposed in this paper. When the clock is low, the difference between VP ðW B =W A Þn ref þ and VN ðW B =W A Þn ref is amplified and the differential outputs are applied to the inputs of the regenerative stage (W1 ¼W2 ¼ WA, W3 ¼W4 ¼ WB). Like the calibration voltage, ref þ and ref are always constant.
Fig. 10. Schematic of the clock generation.
power consumption
comparators
DACs other analog circuits digital circuits
Fig. 11. Power consumption in each part.
The two stages of the comparator work at the same start time. When the clock is high, the amplification stage is designed to
884
Z. Zhu et al. / Microelectronics Journal 45 (2014) 880–885
SFDR = 64.2dB SNDR = 49.5dB THD = -62.9dB ENOB = 7.94bit
AMPLITUDE(dB)
0
-50
-100
0
50
100
150
200
250
300
reasonable refþ and ref voltages can cancel out the offset. To obtain the voltages of refþ and ref, a 5-bit SAR ADC is employed. Before the operation of the 8-bit ADC, the input signals of the comparator are common-mode voltages and the 5-bit SAR ADC calibrates the reasonable voltages of refþ and ref . The procedure of the calibration is shown in Fig. 9. Before the operation of the ADC, the input of the comparators is switched to the common voltage. Due to the mismatch of the comparator, the outputs of the comparator trigger the logic circuits to get a new ref voltage. Then, the comparators do the second comparison. In the following phases, the process is repeated 5 times. With the 5-bit SAR ADC, the circuit must compensate for an offset from 0.5 mV to 16 mV. The comparator reaches a sensitivity of 0.5 mV, which is lower than 1/4 LSB (1 mV). 3.3. Clock generation
ANALOG INPUT FREQUENCY(MHz) Fig. 12. FFT spectrum with input frequency close to 100 MHz.
0.5
To design the clock generation circuit, we proposed a semiclosed loop digital circuit. We observed that both Cmp and Cmpþ are fully charged to VDD at the end of each reset phase; thus, a voltage drop in either or both would indicate the start of comparison. As shown in Fig. 10, detecting the start of the comparison shortens the overall delay of the critical path, thus allowing an increased speed without the power penalty. However, as the comparator switches into the compare phase, both Cmp
SFDR
0.0
|THD|
65
SNDR
-0.5 0
100
200
SFDR,|THD|,SNDR(dB)
DNL(LSB)
70
60
55
50
Output Code
45
1.0 40
0
50
100
150
200
250
300
Fin(MHz)
INL(LSB)
0.5
Fig. 14. Dynamic performance versus input frequency.
0.0
40
mean=7.736 3sigam=0.417 -0.5
30
-1.0 0
100
200
20
Output Code Fig. 13. Simulated INL and DNL.
10 produce its output close to VDD |Vthp| [9], which can effectively reduce the delay time. The outputs are shown in Fig. 8. The offset due to the mismatch of the MOS transistor results in the digital output linearity offset, which may cause a distorted peak. For this reason, a calibration circuit is employed. The offset can be regarded as an excess voltage of input. Therefore,
0
7.4
7.6
7.8
ENOB(bit) Fig. 15. Results of the Monte-Carlo simulation.
8.0
Z. Zhu et al. / Microelectronics Journal 45 (2014) 880–885
885
Table 1 Performance summary and comparison with the state-of-the art. Specifications
ISSCC09 [5],a
JSSC0 11 [6],a
JSSC0 10 [10],a
JSSC0 12[11],a
This Workb
Technology (nm) Supply voltage (V) Sampling rate (MS/s) Resolution (bit) ENOB (bit) Power (mW) FOM (fJ/conv)
65 1 800 5 4.4 1.97 116
40 1.25 1250 6 4.77 6.08 178
65 1.2 1000 6 5 6.27 210
65 1.2 400 8 7.08 4 117
65 1.2 660 8 7.94 7.6 46
a b
Measured results. Simulation results.
and Cmp þ are pulled down together by the regenerative latch to a level much lower than the supply voltage before one of them is charged back to VDD and the other is discharged to GND [10]. Then, rd is pulled to VDD and triggers a pulse generator to create the reset phase. The clk signal will also pull down the FB to feedback to the rd signal. Additionally, a NMOS transistor M1 is employed to avoid the feedback circuit, triggering two reset signals in a period.
it achieves a 660 MS/s operation speed with a power consumption of only 7.6 mW. The procedure is accomplished with asynchronous logic. Moreover, the ADC achieves a 7.94-bit ENOB without error compensation. The paper demonstrates the efficiency and the high-speed potential of the ADC.
4. Simulation results
This work was supported by the National Natural Science Foundation of China (61234002, 61322405, 61306044, 61376033), the National High-tech Program of China (2012AA012302, 2013AA014103) and the Ph.D. Programs Foundation of the Ministry of Education of China (20120203110017).
The proposed SAR ADC is simulated in SMIC 65 nm 1.2 V 1P6M CMOS process. The total capacitance of the SAR ADC is 0.5 pF, and the unit's capacitance is 4 fF. The differential input range is 1 Vpp. At 660 MS/s sampling rate, the ADC consumes 7.6 mW from a 1.2 V reference voltage. Fig. 11 shows the distribution of the ADC's power consumption in detail. The analog circuit and the digital circuit use 42% and 58% of the total power consumption, respectively. The FFT spectrum result is shown in Fig. 12. The simulated SNDR is 49.5 dB and the SFDR is 64.2 dB. The resultant ENOB is 7.94 bits, and the FOM of the proposed ADC is 46 fJ/conv. The simulated differential nonlinearity (DNL) and integral nonlinearity (INL) of the proposed ADC are shown in Fig. 13. The ADC's DNL and INL are 0.4/0.4 LSBs and 0.9/0.8 LSBs, respectively. The dynamic performance of the ADC with different input frequencies is shown in Fig. 14 which plots the simulated SNDR, SFDR and THD. The signal-to-noise-plus-distortion ratio (SNDR) does not drop by 3 dB until the Nyquist frequency. Considering mismatch and process variation, the ADC is also evaluated extensively with Monte-Carlo simulations. The results of Monte-Carlo simulations are shown in Fig. 15. There are 100 results obtained, with ENOBs higher than 7.4 bits. Obviously, the proposed architecture has a high robustness. Table 1 compares the proposed ADC with other state-of-the-art ADCs. As shown in Table 1, this work achieves high speed with a single channel. Nonetheless, the ENOB and power in this work are better in Table 1. The FOM in Table 1 also presents the efficiency of this work. 5. Conclusion The paper presents a novel SAR ADC in 65 nm CMOS. It, which benefits from the proposed capacitor switching procedure so that
Acknowledgments
References [1] Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin, A 10-bit 50MS/s SAR ADC with a monotonic capacitor switching procedure, IEEE J. SolidState Circuits 45 (4) (2010) 731–740. [2] Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, U Seng-Pan, Rui Paulo Martins, Franco Maloberti, A 10-bit 100-MS/s reference-free SAR ADC n 90 nm CMOS, IEEE J. Solid-State Circuits 45 (6) (2010) 1111–1121. [3] Brian P. Ginsburg, Anantha P. Chandrakasan, 500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC, IEEE J. Solid-State Circuits 42 (4) (2007) 739–747. [4] Geert Van der Plas, Bob Verbruggen, A 150 MS/s 133 mW 7b ADC in 90 nm digital CMOS using a comparator-based asynchronous binary-search sub-ADC, IEEE Int. Solid-State Circuits Conf. (2008) 242–610. [5] S.-W.M. Chen, R.W. Brodersen, A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-mmCMOS, IEEE J. Solid-State Circuits 41 (12) (2006) 2669–2680. [6] Zhangming Zhu, Qiyu Wang, Yu Xiao, Xiaoli Song, Yintang Yang, An 8-bit 208 MS/s SAR ADC in 65 nm CMOS, Analog Integr. Circuits Signal Process. 77 (2) (2013) 249–255. [7] Tao Jiang, Wing Liu, Freeman Y. Zhong, Charlie Zhong, Kangmin Hu, Patrick Yin Chiang, A Single-Channel, 1.25-GS/s, 6-bit, 6.08-mW asynchronous successive-approximation adc with improved feedback delay in 40-nm CMOS, IEEE J. Solid-State Circuits 47 (10) (2012) 2444–2453. [8] S. Jiang, M.A. Do, K.S. Yeo, W.M. Lim, An 8-bit 200-MSample/s pipelined ADC with mixed-mode front-end S/H circuit, IEEE Trans. Circuits Syst. I: Regul. Pap. 55 (6) (2008) 1430–1440. [9] Mohamed Abbas, Yasuo Furukawa, Satoshi Komatsu, Takahiro J. Yamaguchi, Kunihiro Asada, Clocked comparator for high-speed applications in 65 nm technology, IEEE Asian Solid State Circuits Conf. (2010) 1–4. [10] Yang Jing, Thura Lin Naing, Robert W. Brodersen, A 1 GS/s 6 bit 6.7 mW successive approximation ADC using asynchronous processing, IEEE J. SolidState Circuits 45 (10) (2010) 1469–1478. [11] Hegong We, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, U Seng-Pan, Rui Paulo Martins, Franco Maloberti, An 8-b 400-MS/s 2-b-per-cycle SAR ADC with resistive DAC, IEEE J. Solid-State Circuits 47 (11) (2012) 1469–1478.
Contents lists available at ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
A single-channel 8-bit 660 MS/s asynchronous SAR ADC with pre-settling procedure in 65 nm CMOS Zhangming Zhu n, Minjie Liu, Qiyu Wang, Yintang Yang School of Microelectronics, Xidian University, Xi'an 710071, China
art ic l e i nf o
a b s t r a c t
Article history: Received 15 September 2013 Received in revised form 24 April 2014 Accepted 25 April 2014 Available online 23 May 2014
A single-channel 8-bit low-power high-speed SAR ADC with a novel pre-settling procedure is presented in this paper. The proposed procedure relaxes the settling time significantly and improves the speed of the ADC. Moreover, the asynchronous technique avoids the high frequency internal clocks and further increases the speed of the SAR ADC. Based on SMIC 65 nm 1.2-V CMOS technology, the simulation results demonstrate that DNL and INL are 0.4/0.4 LSBs and 0.9/0.8 LSBs, respectively. At 660 MS/s sampling rate, the ADC consumes 7.6 mW from a 1.2 V supply. The proposed SAR ADC's SNDR and SFDR are 49.5 dB and 64.2 dB, respectively. & 2014 Elsevier Ltd. All rights reserved.
Keywords: Successive approximation register (SAR) A/D converter High speed CMOS Asynchronous logic circuits Pre-setting procedure
1. Introduction Achieving a moderate resolution, high speed and low power, successive approximation register (SAR) ADCs are usually employed in communication systems such as UWB, mm-wave and serial link transceivers. Because of the improvement of the CMOS process, hundreds of megabytes of sample speed can be attained in 6 to 10 bits [1,2] by SAR ADCs. Additionally, SAR ADCs take advantage of time interleaved [3] due to its excellent energy efficiency. The two major limitations of the speed of SAR ADCs are the settling time of the DAC and the speed of the comparator. Obviously, conventional SAR ADCs have a logarithmic dependence on resolution, but they consume multiple clock cycle to implement the conversion algorithm. Thus, an asynchronous ADC architecture is proposed to speed up the power-efficient SAR algorithm described in [4,5]. The profit from the asynchronous architecture, the power efficiency and the area of the high-speed ADC in [4,5] have been optimized. However, the problem of the DAC settling time still exists.
n
Corresponding author. E-mail addresses: [email protected] (Z. Zhu), [email protected] (M. Liu), [email protected] (Q. Wang), [email protected] (Y. Yang). http://dx.doi.org/10.1016/j.mejo.2014.04.039 0026-2692/& 2014 Elsevier Ltd. All rights reserved.
In this paper, to improve the speed of ADCs, a novel energyefficient procedure named “pre-settling”, which can relax the settling time of the DAC completely, is proposed. A dynamic comparator and clock generation are utilized to achieve high-speed operation.
cmp1 T&H
DAC[2] T&H
clk
Clock generation
Decide[1] cmp3 Clock generation
DAC3
DAC[0]
cmp3 cmp2 cmp1
Decide[2] cmp2
DAC2
DAC[1] T&H
Clock generation
DAC1
Decide[0]
Decide[2:0] cmp
Memory
DAC[2:0]
LOGIC
Fig. 1. The architecture of the proposed ADC.
cmp
Z. Zhu et al. / Microelectronics Journal 45 (2014) 880–885
Furthermore, asynchronous processing is used to shorten the total conversion time. The paper is organized as follows. Section 2 describes the proposed ADC architecture and the pre-settling procedure. Section 3 presents the detailed circuit design of the ADC. The simulation performances of the ADC are presented in Section 4.
synchronous … MSB
MSB-1
LSB
asynchronous … MSB
Sampling
MSB-1
881
LSB
Conversion
2. Architecture design
ck
C MP
tready ck
DAC
Fig. 2. Synchronous processing and asynchronous processing in [7].
Fig. 1 shows the architecture of the proposed ADC. With the pre-settling procedure and asynchronous clock, based on our previous design [6], the sample rate of the proposed SAR ADC is improved from 208 MHz to 660 MHz. The architecture incorporates T&H circuit, DAC, comparator and clock generation. Through an OR gate, three results from the comparators can be transferred to the memory and logic in turn. Thus, the final 8-bit codes are obtained. Fig. 2 shows synchronous processing and asynchronous processing with an unequal time interval. A synchronous approach relies on a clock to divide the conversion phase into equal timeslot as the conversion proceeds from MSB to LSB. However, asynchronous processing makes the average of the total conversion time significantly shorter with unequal time intervals. The high-speed internal clock is also avoided. Fig. 2 shows the critical path for one-bit conversion of the SAR ADC architecture in [7]. N comparators for N-bit conversion are used to store each comparison result into the digital output of each comparator. These digital outputs are utilized simultaneously in two parallel paths: one flows directly to the capacitive DAC, and the other flows to a digital clock generator that detects the completion of the
Comparion
Pre-settling+
Pre-settlingPre-settling+
Comparison
Cmp=1 Cmp=0 Pre-settling+
Pre-settlingDAC1
Comparison
DAC2
Pre-settling+
DAC3
Pre-settling-
Pre-settling-
Cmp=1
Comparsion
Cmp=0
Comparison
Pre-settling+ Pre-settling+
Pre-settling-
Cmp=1 Pre-settling-
Comparsion
Cmp=0 Pre-settling+ Comparsion
Pre-settling-
Fig. 3. Proposed procedure.
882
Z. Zhu et al. / Microelectronics Journal 45 (2014) 880–885
current quantization and generates a “ready” signal to clock the next quantization. Both paths occur simultaneously. Then, the critical path is reduced to [7]. T critical ¼ t comp þ max ½t ready ; t DAC : For this asynchronous algorithm, the settling time of the DAC still limits the speed, and N comparators consume more power. Fig. 3 shows a 3-bit example of the proposed procedure. The proposed procedure can be performed by three DACs and comparators to relax the settling time of the DACs completely. As in Fig. 3, Fig. 4 shows that, at the start of the sampling phase, the switches of the three DACs are set to the same state. At the holding phase, the bootstrapped switch is opened and DAC1 with its comparator starts the first comparison. Meanwhile, DAC2 and DAC3 are set to different states for the next comparison. By the end of the first comparison, the outputs of the comparator trigger a clock pulse by the clock generation. Then, the DAC and comparator in the next comparison are chosen by the logic signal DAC o2:0 4 and Decide o2:0 4, which depend on the results of the first comparison. If the result of the comparison is high, DAC2 with its comparator will start the second comparison, while DAC1 and DAC3 will be set to the pre-settling state. Otherwise, DAC3 will be used for comparison. This procedure can be repeated until the successive conversion is complete. After the last comparison, all the DACs will be reset for the sampling phase. In the proposed procedure, the settling time of the DAC has no effect on the speed of the ADC. Fig. 4 shows the asynchronous clock used in this paper. Clearly, the speed of the proposed ADC is only limit by the comparator. In the pre-settling procedure, each cycle of the proposed SAR ADC is about half the duration of a conventional cycle. The simulation results (Section 4) show that this procedure can achieve low power consumption and high accuracy at a high sampling rate.
3. Circuit implementation The implementation details of the S/H circuit, comparator and the clock generation are presented in this section. These components are critical to the speed, power consumption, and accuracy of the ADC. The design considerations of the building blocks are described in the following subsections.
3.1. S/H circuit The function of the S/H circuit is achieved by a bootstrapped switch and a DAC. As mentioned above, sampling on the top plates of the capacitors offers a better performance in speed. The substrate coupling noise can be rejected by differential sampling [8]. However, the charge injection will have a critical effect on accuracy due to the device in the deep sub-micron technology. We can regard the different charge injections in the differential sides as a noise signal. Differential sampling could cancel the even harmonic components. Consequently, a differential sampling is significant. Fig. 5 shows the DAC of the SAR ADC. To achieve a better linearity, a binary-weighted capacitor carry, described in [6], is employed in the DAC. As in the switching process in [6], a good common-mode noise rejection and a high accuracy can be achieved. The unit capacitance is 4 fF, which is small enough to ensure that the pre-settling time is shorter than the comparison time.
cmp+ cmpclk
1.3 1.2 1.1 1.0 0.9
Sample
0.8 com
d
pre
d
re
pre
d
re
d
re
0.7
V
DAC1 DAC2
pre
DAC3
pre
com
d
0.6 0.5 0.4 0.3 0.2
com--comparison
0.1
d—digtal delay
delay
0.0 Pre—pre-settling
-0.1
t
Re—reset phase
Fig. 4. Asynchronous clock.
Fig. 6. Schematic and waveform of a conventional comparator.
GND Vref
Cdummy
C6 C5
C4
C3
C2
C1
C0
C0
Vip SAR logic
Vin Cdummy
C6 C5
C4
C3
C2
C1
C0
C0
Vref GND Fig. 5. Schematic of DAC.
Z. Zhu et al. / Microelectronics Journal 45 (2014) 880–885
883
VDD
VDD
clk
clk
CmpCmp+
VP
M1
M3
ref+
ref-
M4
M2
VN
clkb
clk
Fig. 7. Schematic of the proposed comparator.
1.3 1.2
ref+
cmp+ cmpclk
ref
-
5b DAC logic
1.1
cm
1.0 0.9
cm
0.8
clk
V
0.7
Fig. 9. Circuit of the comparator calibration.
0.6 0.5 0.4 0.3 0.2 0.1
Cmp-
clk
Cmp+
0.0
FB
-0.1
t
clk rd
Fig. 8. Waveform of the proposed comparator.
M1 ~FB
reset
3.2. Comparator with offset calibration Fig. 6 shows the waveform of a conventional comparator. When the clock switches to high, the currents flowing in the latch charge the output nodes at different rates depending on the values of the input voltages. When one of the output voltages reaches the threshold voltage VDD |Vthp| of the PMOS, a feedback operation starts and the two outputs eventually reach VDD and ground. When the clock is high, the comparator works at the comparison phase. In the pre-amplify phase, the regeneration latch is reset to | VDD Vthp|. In the comparison phase, the regeneration latch compares the amplified voltage. The delay can be calculated as the time difference from the start time of the comparison to the time when the output reaches the threshold voltage. Fig. 7 shows the comparator employed in this ADC. The comparator is composed of two stages, an amplification stage and a regenerative stage. Based on the comparator in [9], the comparator calibration is proposed in this paper. When the clock is low, the difference between VP ðW B =W A Þn ref þ and VN ðW B =W A Þn ref is amplified and the differential outputs are applied to the inputs of the regenerative stage (W1 ¼W2 ¼ WA, W3 ¼W4 ¼ WB). Like the calibration voltage, ref þ and ref are always constant.
Fig. 10. Schematic of the clock generation.
power consumption
comparators
DACs other analog circuits digital circuits
Fig. 11. Power consumption in each part.
The two stages of the comparator work at the same start time. When the clock is high, the amplification stage is designed to
884
Z. Zhu et al. / Microelectronics Journal 45 (2014) 880–885
SFDR = 64.2dB SNDR = 49.5dB THD = -62.9dB ENOB = 7.94bit
AMPLITUDE(dB)
0
-50
-100
0
50
100
150
200
250
300
reasonable refþ and ref voltages can cancel out the offset. To obtain the voltages of refþ and ref, a 5-bit SAR ADC is employed. Before the operation of the 8-bit ADC, the input signals of the comparator are common-mode voltages and the 5-bit SAR ADC calibrates the reasonable voltages of refþ and ref . The procedure of the calibration is shown in Fig. 9. Before the operation of the ADC, the input of the comparators is switched to the common voltage. Due to the mismatch of the comparator, the outputs of the comparator trigger the logic circuits to get a new ref voltage. Then, the comparators do the second comparison. In the following phases, the process is repeated 5 times. With the 5-bit SAR ADC, the circuit must compensate for an offset from 0.5 mV to 16 mV. The comparator reaches a sensitivity of 0.5 mV, which is lower than 1/4 LSB (1 mV). 3.3. Clock generation
ANALOG INPUT FREQUENCY(MHz) Fig. 12. FFT spectrum with input frequency close to 100 MHz.
0.5
To design the clock generation circuit, we proposed a semiclosed loop digital circuit. We observed that both Cmp and Cmpþ are fully charged to VDD at the end of each reset phase; thus, a voltage drop in either or both would indicate the start of comparison. As shown in Fig. 10, detecting the start of the comparison shortens the overall delay of the critical path, thus allowing an increased speed without the power penalty. However, as the comparator switches into the compare phase, both Cmp
SFDR
0.0
|THD|
65
SNDR
-0.5 0
100
200
SFDR,|THD|,SNDR(dB)
DNL(LSB)
70
60
55
50
Output Code
45
1.0 40
0
50
100
150
200
250
300
Fin(MHz)
INL(LSB)
0.5
Fig. 14. Dynamic performance versus input frequency.
0.0
40
mean=7.736 3sigam=0.417 -0.5
30
-1.0 0
100
200
20
Output Code Fig. 13. Simulated INL and DNL.
10 produce its output close to VDD |Vthp| [9], which can effectively reduce the delay time. The outputs are shown in Fig. 8. The offset due to the mismatch of the MOS transistor results in the digital output linearity offset, which may cause a distorted peak. For this reason, a calibration circuit is employed. The offset can be regarded as an excess voltage of input. Therefore,
0
7.4
7.6
7.8
ENOB(bit) Fig. 15. Results of the Monte-Carlo simulation.
8.0
Z. Zhu et al. / Microelectronics Journal 45 (2014) 880–885
885
Table 1 Performance summary and comparison with the state-of-the art. Specifications
ISSCC09 [5],a
JSSC0 11 [6],a
JSSC0 10 [10],a
JSSC0 12[11],a
This Workb
Technology (nm) Supply voltage (V) Sampling rate (MS/s) Resolution (bit) ENOB (bit) Power (mW) FOM (fJ/conv)
65 1 800 5 4.4 1.97 116
40 1.25 1250 6 4.77 6.08 178
65 1.2 1000 6 5 6.27 210
65 1.2 400 8 7.08 4 117
65 1.2 660 8 7.94 7.6 46
a b
Measured results. Simulation results.
and Cmp þ are pulled down together by the regenerative latch to a level much lower than the supply voltage before one of them is charged back to VDD and the other is discharged to GND [10]. Then, rd is pulled to VDD and triggers a pulse generator to create the reset phase. The clk signal will also pull down the FB to feedback to the rd signal. Additionally, a NMOS transistor M1 is employed to avoid the feedback circuit, triggering two reset signals in a period.
it achieves a 660 MS/s operation speed with a power consumption of only 7.6 mW. The procedure is accomplished with asynchronous logic. Moreover, the ADC achieves a 7.94-bit ENOB without error compensation. The paper demonstrates the efficiency and the high-speed potential of the ADC.
4. Simulation results
This work was supported by the National Natural Science Foundation of China (61234002, 61322405, 61306044, 61376033), the National High-tech Program of China (2012AA012302, 2013AA014103) and the Ph.D. Programs Foundation of the Ministry of Education of China (20120203110017).
The proposed SAR ADC is simulated in SMIC 65 nm 1.2 V 1P6M CMOS process. The total capacitance of the SAR ADC is 0.5 pF, and the unit's capacitance is 4 fF. The differential input range is 1 Vpp. At 660 MS/s sampling rate, the ADC consumes 7.6 mW from a 1.2 V reference voltage. Fig. 11 shows the distribution of the ADC's power consumption in detail. The analog circuit and the digital circuit use 42% and 58% of the total power consumption, respectively. The FFT spectrum result is shown in Fig. 12. The simulated SNDR is 49.5 dB and the SFDR is 64.2 dB. The resultant ENOB is 7.94 bits, and the FOM of the proposed ADC is 46 fJ/conv. The simulated differential nonlinearity (DNL) and integral nonlinearity (INL) of the proposed ADC are shown in Fig. 13. The ADC's DNL and INL are 0.4/0.4 LSBs and 0.9/0.8 LSBs, respectively. The dynamic performance of the ADC with different input frequencies is shown in Fig. 14 which plots the simulated SNDR, SFDR and THD. The signal-to-noise-plus-distortion ratio (SNDR) does not drop by 3 dB until the Nyquist frequency. Considering mismatch and process variation, the ADC is also evaluated extensively with Monte-Carlo simulations. The results of Monte-Carlo simulations are shown in Fig. 15. There are 100 results obtained, with ENOBs higher than 7.4 bits. Obviously, the proposed architecture has a high robustness. Table 1 compares the proposed ADC with other state-of-the-art ADCs. As shown in Table 1, this work achieves high speed with a single channel. Nonetheless, the ENOB and power in this work are better in Table 1. The FOM in Table 1 also presents the efficiency of this work. 5. Conclusion The paper presents a novel SAR ADC in 65 nm CMOS. It, which benefits from the proposed capacitor switching procedure so that
Acknowledgments
References [1] Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin, A 10-bit 50MS/s SAR ADC with a monotonic capacitor switching procedure, IEEE J. SolidState Circuits 45 (4) (2010) 731–740. [2] Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, U Seng-Pan, Rui Paulo Martins, Franco Maloberti, A 10-bit 100-MS/s reference-free SAR ADC n 90 nm CMOS, IEEE J. Solid-State Circuits 45 (6) (2010) 1111–1121. [3] Brian P. Ginsburg, Anantha P. Chandrakasan, 500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC, IEEE J. Solid-State Circuits 42 (4) (2007) 739–747. [4] Geert Van der Plas, Bob Verbruggen, A 150 MS/s 133 mW 7b ADC in 90 nm digital CMOS using a comparator-based asynchronous binary-search sub-ADC, IEEE Int. Solid-State Circuits Conf. (2008) 242–610. [5] S.-W.M. Chen, R.W. Brodersen, A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-mmCMOS, IEEE J. Solid-State Circuits 41 (12) (2006) 2669–2680. [6] Zhangming Zhu, Qiyu Wang, Yu Xiao, Xiaoli Song, Yintang Yang, An 8-bit 208 MS/s SAR ADC in 65 nm CMOS, Analog Integr. Circuits Signal Process. 77 (2) (2013) 249–255. [7] Tao Jiang, Wing Liu, Freeman Y. Zhong, Charlie Zhong, Kangmin Hu, Patrick Yin Chiang, A Single-Channel, 1.25-GS/s, 6-bit, 6.08-mW asynchronous successive-approximation adc with improved feedback delay in 40-nm CMOS, IEEE J. Solid-State Circuits 47 (10) (2012) 2444–2453. [8] S. Jiang, M.A. Do, K.S. Yeo, W.M. Lim, An 8-bit 200-MSample/s pipelined ADC with mixed-mode front-end S/H circuit, IEEE Trans. Circuits Syst. I: Regul. Pap. 55 (6) (2008) 1430–1440. [9] Mohamed Abbas, Yasuo Furukawa, Satoshi Komatsu, Takahiro J. Yamaguchi, Kunihiro Asada, Clocked comparator for high-speed applications in 65 nm technology, IEEE Asian Solid State Circuits Conf. (2010) 1–4. [10] Yang Jing, Thura Lin Naing, Robert W. Brodersen, A 1 GS/s 6 bit 6.7 mW successive approximation ADC using asynchronous processing, IEEE J. SolidState Circuits 45 (10) (2010) 1469–1478. [11] Hegong We, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, U Seng-Pan, Rui Paulo Martins, Franco Maloberti, An 8-b 400-MS/s 2-b-per-cycle SAR ADC with resistive DAC, IEEE J. Solid-State Circuits 47 (11) (2012) 1469–1478.