- Email: [email protected]
s SAR ADC with a tri-level based capacitor switching procedure
Microelectronics Journal 44 (2013) 1132–1137
Contents lists available at ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
A 1.33 μW 10-bit 200KS/s SAR ADC with a tri-level based capacitor switching procedure Zhangming Zhu, Yu Xiao n, Weitie Wang, Yuheng Guan, Lianxi Liu, Yintang Yang School of Microelectronics, Xidian University, Xi'an 710071, PR China
art ic l e i nf o
a b s t r a c t
Article history: Received 27 December 2012 Received in revised form 25 June 2013 Accepted 27 June 2013 Available online 18 July 2013
A 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) using an energyefficient tri-level based capacitor switching procedure is presented. The proposed switching procedure achieves 97.66% less switching energy when compared to the conventional method. The number of unit capacitors is reduced by a factor of 4 over that of conventional architecture as well. To make the power consumption of the comparator scale down with respect to the comparison rate, the fully dynamic comparator is used. Moreover, the dynamic logic circuit is implemented to further reduce the power of digital circuits. The ADC is implemented in a 0.18 μm 1P6M CMOS technology. At 1.0-V power supply and 200KS/s, the ADC achieves an SNDR of 60.54 dB and consumes 1.33 μW, resulting in a figure-of-merit (FOM) of 7.7 fJ/conversion-step. The ADC core occupies an active area of only 230 400 mm2. & 2013 Elsevier Ltd. All rights reserved.
Keywords: Analog-to-digital converter Energy-efficient Capacitor switching procedure Dynamic logic Successive approximation register
1. Introduction Low power is one of the most relevant design concerns for energy-limited applications, such as wireless sensor networks and implantable medical devices. Since ADCs are the key blocks of these systems, it is essential to improve the energy efficiency of the ADC to extend the system's life-span. Successive approximation register (SAR) ADC has found wide applications for its moderate resolution, speed, simple structure, and high energy efficiency [1,2]. In SAR ADCs, the primary sources of power consumption are capacitor arrays, comparator, and digital circuits. With the advancement of technology and supply voltage scaling, the digital power dissipation is becoming lower. The fully dynamic comparator is often used owing to its good power efficiency. Therefore, the power of capacitor arrays dominates the overall power consumption of SAR ADCs. Reducing the capacitance of the unit capacitor is an effective way to minimize the power consumption of capacitor arrays. However, using a small unit capacitor will degrade the linearity of ADC because of mismatch issue. Recently, several energy-efficient switching schemes have been developed to reduce the power of capacitor arrays. Compared to conventional architecture [3], the energy-saving [4], monotonic [5], and VCMbased [6] reduce 56%, 81%, and 87.54% switching energy,
n
Corresponding author. Tel.: +86 812 988 469040. E-mail addresses: [email protected] (Z. Zhu). [email protected] (Y. Xiao). 0026-2692/$ - see front matter & 2013 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.mejo.2013.06.018
respectively. In this paper, a more energy-efficient tri-level based capacitor switching procedure is proposed. By using the level shifting technique after the MSB is determined and monotonic switching procedure for subsequent bit steps, the switching energy and number of capacitors have been significantly reduced. This paper presents a power-efficient SAR ADC that combines several techniques to achieve low power design. First, a novel tri-level based capacitor switching procedure is developed to reduce the power of capacitor arrays. Second, the fully dynamic comparator is adopted to make the power consumption of the comparator scale proportional to the comparison rate. Finally, the dynamic logic circuit is implemented to further reduce the power dissipation of digital circuits. The post-layout simulation results show the ADC achieves an ENOB of 9.76 bit at a sampling rate of 200KS/s. It consumes only 1.33 μW from a 1.0 V supply and achieves a figure of merit of 7.7 fJ/conversion-step. 2. SAR ADC architecture 2.1. Tri-level based capacitor switching procedure SAR ADCs usually use a binary-weighted capacitor array rather than a C–2C capacitor array or capacitor array with a scaling capacitor for better linearity. Fig. 1(a) and (b) show a conventional differential 10-bit SAR ADC and the proposed SAR ADC, respectively. A differential architecture is employed to have a good commonmode noise rejection and achieve high accuracy. Compared to conventional structure, the proposed ADC reduces the number of
Z. Zhu et al. / Microelectronics Journal 44 (2013) 1132–1137
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Fig. 1. (a) A conventional 10-bit SAR ADC (b) the proposed SAR ADC architecture.
capacitors by a factor of 4 but requires a third reference voltage VCM which is designed to 1/2 VREF. The operation of the proposed ADC is described below. At the sampling phase, the differential input signal is sampled on the top-plates of two capacitor arrays via sampling switches, and simultaneously the bottom-plates of capacitors are connected to the common-mode voltage VCM. Next, the sampling switches are open and the comparator performs the first comparison without consuming any switching energy. Once the MSB is obtained, the bottom-plates of the capacitor array which samples the higher input voltage are reconnected to ground and the other capacitor array remains unchanged. Thus, the voltage of capacitors on the higher voltage potential side is level-shifted down by 1/2 VREF. The capacitor array consumes no switching energy in this operation. After the MSB comparison, the different reference voltages will be chosen for the differential capacitor arrays, as shown in Table 1. If MSB¼1, the positive and negative reference voltages on the VXP side will be VCM and VGND. On the VXN side, the positive and negative reference voltages will be VREF and VCM. Then the ADC performs monotonic switching procedure for the following successive approximation operation which is similar as the scheme in Ref. [5]. According to the comparator output, the largest bitcapacitor C8 on the lower voltage potential side is switched from VCM to VREF or from ground to VCM and the other bit-capacitor (on the higher voltage potential side) remains unchanged. Then the comparator begins the next comparison. The ADC repeats the producer until the LSB is decided. During the monotonic switching procedure, the proposed scheme only switches one capacitor for each bit cycle, resulting in less switching activity and lower energy. The successive approximation wave for the proposed switching scheme is shown in Fig. 2.
Table 1 Different reference voltages are chosen for differential capacitor arrays according to first comparison result. Differential
MSB ¼1
MSB ¼0
input
Positive side Negative side Positive side Negative side VREF VCM
Positive reference VCM Negative reference VGND
VIP
Sample
1
2
VREF VCM
3
4
VCM VGND
5
6
1/2VREF
VIN Level-shifting
Monotonic switching procedure
Fig. 2. Waveform of proposed switching scheme.
The average switching energy for an N-bit conventional SAR ADC can be expressed as [5] N
Eavg;conv ¼ ∑ 2Nþ12i ð2i 1ÞCV 2REF
ð2Þ
i¼1
2.2. Switching energy To further explain the proposed switching scheme, a 3-bit differential SAR ADC as shown in Fig. 3 is used. The quantitative energy consumption of each switching phase for all possible conversions is also shown in the figure. For the proposed switching scheme, the comparator performs the first comparison without consuming any switching energy. After the MSB is determined, the voltage of capacitors on the higher voltage potential side is levelshifted down by 1/2 VREF. As a result, the 2nd-MSB can be decided. There is no energy consumed in this step as the chargeredistribution is completely passive. Then the ADC performs monotonic switching procedure for the subsequent successive approximation operation. For an N-bit SAR ADC using the proposed switching scheme, if each digital output code is equiprobable, the average switching energy can be derived as N2
Eavg;tri_level ¼ ∑ ð2Ni5 ÞCV 2REF i¼1
ð1Þ
The average switching energy for a 10-bit conventional SAR ADC is 1365.3CV 2REF while the average switching energy for a 10-bit SAR ADC using the proposed switching scheme is only 31.88 CV 2REF . The proposed scheme achieves 97.66% switching energy saving with respect to the conventional one. Energy saving [4] and monotonic switching [5] schemes provide only 56% and 81% reductions, respectively. A comparison of switching energy for the reported switching schemes versus the output code is shown in Fig. 4. 2.3. Linearity The unit capacitor in the SAR ADC capacitor array is typically limited by matching requirements. Assuming the unit capacitor is modeled with a nominal value of C u and a standard deviation of su . For the conventional switching scheme, the mid-code transition is considered as the worst case, since at this transition, all the capacitors change their state. A conventional differential N-bit binary-scaled DAC is composed of 2 2N C u -elements, with an LSB step of 2C u (the factor of 2 arises from the differential implementation) [7]. At the MSB code transition all capacitors are switched,
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Z. Zhu et al. / Microelectronics Journal 44 (2013) 1132–1137
Fig. 3. Switching sequence and energy consumption of 3-bit SAR ADC with proposed method.
1800
Conventional Energy saving Monotonic Proposed
Switching Energy (CV2REF )
1600 1400
Clk
VP
M1
1200
C lkb
M0
M11 M9 OUTN
VN
M2
AP
1000
AN
800
M3
600
M10 M12
C lk b
OUTP
M5
M6
M8
M7
AN
AP Clk
M4
400
OUTP OUTN
200
Valid
Fig. 5. Fully dynamic comparator.
0
0
100
200
300
400
500
600
700
800
900
1000
CODE
capacitor arrays use MIM capacitors. The size of unit capacitor is set to 6 6 mm2 to reduce the nonlinearity caused by mismatch and the capacitance of a unit cell is about 35 fF. The input capacitance of the proposed SAR ADC is about 8.96 pF. To reduce the parasitic capacitance of routing, the binary-weight capacitor array is laid out based on partial common-centroid layout strategy [1].
Fig. 4. Switching energy versus output code.
leading to a s of: pffiffiffiffiffiffiffiffiffiffiffi 2Nþ1 su sDNL;conv ¼ ðLSBÞ 2C u
ð3Þ
For the proposed switching scheme, benefiting from top-plate sampling and level shifting technique, the MSB and 2nd-MSB are determined mismatch-independently, therefore, the worst case DNL occurs at 1/4 VFS and 3/4 VFS. At these two transitions, 2 2N2 C u -elements are switched, resulting in a s of: pffiffiffiffiffiffiffiffiffiffiffi 2N1 su sDNL;tri_level ¼ ðLSBÞ ð4Þ 2C u It follows from Eqs. (3) and (4) that the DNL for the proposed switching procedure is reduced by a factor of 2 with the same capacitor mismatch.
3. Circuit implementation 3.1. Capacitor array For high accuracy A/D converters, a high performance S/H circuit is needed. In this work, the bootstrapped switch circuit [5] is used to achieve low distortion and rail-to-rail operation. The
3.2. Fully dynamic comparator The two-stage fully dynamic comparator [8] shown in Fig. 5 is used to save power. The first stage is a dynamic voltage amplifier and the second stage is a latch. Since the comparator has no static biasing, the average power consumption of the comparator is proportional to the conversion rate. For one-bit/step SAR ADCs, the offset of the comparator does not affect the accuracy and only causes the shift of the entire transfer curve and slightly reduces the input voltage range [1]. The size of the transistors have been optimized for low power and low offset. A careful layout to reduce the parasitics and dynamic offset is important as well. As for the input referred noise of the comparator, the post-layout extracted capacitances at the AP/AN nodes are about 15 fF, which makes the thermal noise of the comparator in the same order as the quantization noise of the ADC [8]. The dynamic comparator adopts a P-type input pair. When the system clock Clk is high, the comparator outputs OUTP and OUTN are reset to high. When Clk turns to low, the comparator compares the input voltages and then the latch regeneration forces one
Z. Zhu et al. / Microelectronics Journal 44 (2013) 1132–1137
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Fig. 6. Implementation of main control and DAC control.
Valid Sample
Main_Control 10
Main_Control 9
Clk10
Sample
DAC_Control 10
Main_Control 2
Clk9 P10 N10
DAC_Control 9
Main_Control 1
Clk2 P9 N9
DAC_Control 2
Clk1 P2 P10 P9
N2
P2 OUTP
OUTP OUTN
Output Latch
Fig. 7. Simplified overview of digital circuits.
Fig. 8. Timing diagram.
output to high and the other to low. Consequently, the Valid signal is pulled to high to enable SAR logic circuits. 3.3. SAR dynamic logic circuits To implement the analog components of the ADC in a powerefficient way, the energy-efficient tri-level based capacitor switching procedure and fully dynamic comparator are used. However, the power consumption of digital circuits is still relatively large. Therefore, the digital power consumption also needs to be minimized to achieve a low overall power consumption. For this purpose, dynamic logic [9] is introduced to reduce the complexity of digital circuits. By using dynamic logic instead of complementary logic, less transistors are needed, thus offering a better performance in speed and in power consumption. Fig. 6 shows the dynamic logic implementation of main control and DAC control. The main control circuits function as a shift register and the DAC control circuits are used to sample the output of the comparator. Fig. 7 shows the overall architecture of the digital circuits for the SAR ADC. Output latches are used to store the digital codes for the entire conversion period until a new conversion is completed. At the sampling phase, all the outputs of main control circuits are reset to low. The operation of one dynamic logic cell is as follows.
Fig. 9. Capacitor switch buffer control logic.
At the rising edge of Valid, Clki is precharged to VDD. At the falling edge of Valid, the output Q is reset to VDD and Clki is pull down to ground. The DAC control circuits sample the output of comparator when both Clki and Valid are high. The corresponding timing diagram is shown in Fig. 8. Note P10/N10 is reset to low and P2–P9/ N2–N9 are set to high at sampling phase. The capacitor switch buffer control signals are generated by the combination logic as shown in Fig. 9. Inverters and CMOS transmission gates are used as switch buffers.
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Z. Zhu et al. / Microelectronics Journal 44 (2013) 1132–1137
Table 3 Performance summary and comparison.
Technology Resolution (bit) Supply (V) Sampling rate (Hz) Input range (Vpp) Power (μW) SFDR (dB) SNDR (dB) ENOB (bit) FOM (fJ/conversionstep) n
Fig. 10. Layout of the proposed ADC.
[1]n
[2]n
[7]n
[8]n
[9]nn
Proposednn
130 nm 10 1.0 1K 1.78 0.053 67.6 56.7 9.12 94.5
180 nm 12 1.0 100 K 2 25 71 65.3 10.55 165
90 nm 8 1.0 10 M 0.83 26.3 N/A 48.5 7.77 12
65 nm 10 1.0 1M 1.25 1.9 N/A 54.4 8.75 4.4
65 nm 8 1.0 50 M N/A 192.8 72 49.9 7.99 15
180 nm 10 1.0 200 K 1.8 1.33 78.49 60.54 9.76 7.7
Measured results. Post-layout simulation results.
nn
0
Power(dB)
After the parasitics, capacitor arrays still consume a large part of the total power. This can be improved by implementing capacitor arrays in more advanced technology or using smaller size of unit capacitor. To compare the proposed ADC with other state-of-the-art SAR ADCs, the well-known figure-of-merit (FOM) equation is used.
SFDR=78.49dB SNDR=60.54dB [email protected]
-20 -40 -60 -80 -100
FOM ¼ 0
10
20
30
40
50
60
70
80
90
100
Frequency(KHz) Fig. 11. FFT spectrum of the proposed ADC at 200KS/s.
Table 2 Power consumption distribution of main components.
Power minff s ; 2 ERBWg 2ENOB
ð5Þ
where the fs is the sampling rate, and the ENOB is the effective number of bits at the effective resolution bandwidth (ERBW). The FOM of the proposed ADC is 7.7 fJ/conversion-step at 200KS/s and a 1.0 V supply. Table 3 summarizes the performance of the proposed ADC and shows a comparison to other state-of-the-art SAR ADCs.
Components
Power (μW)
Percentage (%)
5. Conclusion
Capacitor arrays and switches Comparator SAR logic and output latch Switch control logic Parasitics Overall
0.36 0.17 0.27 0.08 0.45 1.33
27.1 12.8 20.3 6.0 33.8 100
In this paper, an energy-efficient tri-level based capacitor switching procedure for SAR ADCs was presented. The proposed switching procedure leads to both lower switching energy and less unit capacitors as compared with the conventional method. With the proposed switching procedure and fully dynamic design, the SAR ADC consumes 1.33 mW at a sampling rate of 200KS/s and achieves an ENOB of 9.76 bit, offering an energy efficiency of 7.7 fJ/ conversion-step.
4. Post-layout simulation results The ADC is implemented in 1P6M 0.18 mm 1.8 V CMOS process. The active area of the ADC is 0.092 mm2, as shown in Fig. 10. In the proposed SAR ADC, both the supply and DAC reference voltage (VREF) are set to 1.0 V, thereby the input signal swing of the ADC is rail-to-rail (2Vpp). However, the parasitic capacitance of the capacitor arrays and comparator input transistors induces a gain error, thus the real input signal range is 1.8 Vpp. Post-layout simulation was performed to characterize the dynamic performance of the ADC. The 1024-point FFT spectrum of the proposed ADC is shown in Fig. 11, for a sinusoidal wave input at 94.7 KHz and sampling rate of 200KS/s. The SNDR is 60.54 dB providing an ENOB of 9.76 bit. The proposed ADC consumes 1.33 mW from a 1.0 V supply. Table 2 list the distribution of power consumption of the main components, where the parasitic component is obtained by subtracting the schematic-based result from the post-layout result. As shown in Table 2, the power consumption of the undesired parasitics is a major contributor to the total power. For low-speed circuits, the power of interconnect is more significant than that of transistors because transistor dimensions are relatively small.
Acknowledgments This work was supported by the National Natural Science Foundation of China (61234002, 61006028), the National Hightech Program of China (2012AA012302, 2013AA014103) and Ph.D. Programs Foundation of Ministry of Education of China (20120203110017). References [1] D. Zhang, A. Bhide, A. Alvandpour, A 53-nW 9.1-ENOB 1KS/s SAR ADC in 0.13 μm CMOS for medical implant devices, IEEE J. Solid-State Circuits 47 (7) (2012) 1585–1593. [2] Naveen Verma, Anantha P. Chandrakasan, An ultra low energy 12-bit rateresolution scalable SAR ADC for wireless sensor nodes, IEEE J. Solid-State Circuits 42 (6) (2007) 1196–1204. [3] Ginsburg, B.P., Chandrakasan, A.P, An energy-efficient charge recycling approach for a SAR converter with capacitive DAC, in: IEEE International Symposium on Circuits and Systems, Kobe, Japan, May 2005, pp. 184–187. [4] Y.K. Chang, C.S. Wang, C.K. Wang, A 8-bit 500KS/s low power SAR ADC for biomedical application, in: IEEE Asian Solid-State Circuits Conference, Jeju, Korea, 228–231, November 2007.
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[5] C.C. Liu, S.J. Chang, G.Y. Huang, Y.Z. Lin, A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure, IEEE J. Solid-State Circuits 45 (4) (2010) 731–740. [6] Y. Zhu, C.-H. Chan, et al., A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS, IEEE J. Solid-State Circuits 45 (6) (2010) 1111–1121. [7] Pieter J.A. Harpe, et al., A 26 μW 8 bit 10MS/s asynchronous SAR ADC for low energy radios, IEEE J. Solid-State Circuits 46 (7) (2011) 1585–1595.
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[8] M. van Elzakker, et al., A 10-bit charge-redistribution ADC consuming 1.9 mW at 1MS/s, IEEE J. Solid-State Circuits 45 (5) (2010) 1007–1015. [9] G.Z. Huang, P.F Lin., A 15 fJ/conversion-step 8-bit 50MS/s asynchronous SAR ADC with efficient charge recycling technique, Microelectron. J. 43 (12) (2012) 941–948.
Contents lists available at ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
A 1.33 μW 10-bit 200KS/s SAR ADC with a tri-level based capacitor switching procedure Zhangming Zhu, Yu Xiao n, Weitie Wang, Yuheng Guan, Lianxi Liu, Yintang Yang School of Microelectronics, Xidian University, Xi'an 710071, PR China
art ic l e i nf o
a b s t r a c t
Article history: Received 27 December 2012 Received in revised form 25 June 2013 Accepted 27 June 2013 Available online 18 July 2013
A 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) using an energyefficient tri-level based capacitor switching procedure is presented. The proposed switching procedure achieves 97.66% less switching energy when compared to the conventional method. The number of unit capacitors is reduced by a factor of 4 over that of conventional architecture as well. To make the power consumption of the comparator scale down with respect to the comparison rate, the fully dynamic comparator is used. Moreover, the dynamic logic circuit is implemented to further reduce the power of digital circuits. The ADC is implemented in a 0.18 μm 1P6M CMOS technology. At 1.0-V power supply and 200KS/s, the ADC achieves an SNDR of 60.54 dB and consumes 1.33 μW, resulting in a figure-of-merit (FOM) of 7.7 fJ/conversion-step. The ADC core occupies an active area of only 230 400 mm2. & 2013 Elsevier Ltd. All rights reserved.
Keywords: Analog-to-digital converter Energy-efficient Capacitor switching procedure Dynamic logic Successive approximation register
1. Introduction Low power is one of the most relevant design concerns for energy-limited applications, such as wireless sensor networks and implantable medical devices. Since ADCs are the key blocks of these systems, it is essential to improve the energy efficiency of the ADC to extend the system's life-span. Successive approximation register (SAR) ADC has found wide applications for its moderate resolution, speed, simple structure, and high energy efficiency [1,2]. In SAR ADCs, the primary sources of power consumption are capacitor arrays, comparator, and digital circuits. With the advancement of technology and supply voltage scaling, the digital power dissipation is becoming lower. The fully dynamic comparator is often used owing to its good power efficiency. Therefore, the power of capacitor arrays dominates the overall power consumption of SAR ADCs. Reducing the capacitance of the unit capacitor is an effective way to minimize the power consumption of capacitor arrays. However, using a small unit capacitor will degrade the linearity of ADC because of mismatch issue. Recently, several energy-efficient switching schemes have been developed to reduce the power of capacitor arrays. Compared to conventional architecture [3], the energy-saving [4], monotonic [5], and VCMbased [6] reduce 56%, 81%, and 87.54% switching energy,
n
Corresponding author. Tel.: +86 812 988 469040. E-mail addresses: [email protected] (Z. Zhu). [email protected] (Y. Xiao). 0026-2692/$ - see front matter & 2013 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.mejo.2013.06.018
respectively. In this paper, a more energy-efficient tri-level based capacitor switching procedure is proposed. By using the level shifting technique after the MSB is determined and monotonic switching procedure for subsequent bit steps, the switching energy and number of capacitors have been significantly reduced. This paper presents a power-efficient SAR ADC that combines several techniques to achieve low power design. First, a novel tri-level based capacitor switching procedure is developed to reduce the power of capacitor arrays. Second, the fully dynamic comparator is adopted to make the power consumption of the comparator scale proportional to the comparison rate. Finally, the dynamic logic circuit is implemented to further reduce the power dissipation of digital circuits. The post-layout simulation results show the ADC achieves an ENOB of 9.76 bit at a sampling rate of 200KS/s. It consumes only 1.33 μW from a 1.0 V supply and achieves a figure of merit of 7.7 fJ/conversion-step. 2. SAR ADC architecture 2.1. Tri-level based capacitor switching procedure SAR ADCs usually use a binary-weighted capacitor array rather than a C–2C capacitor array or capacitor array with a scaling capacitor for better linearity. Fig. 1(a) and (b) show a conventional differential 10-bit SAR ADC and the proposed SAR ADC, respectively. A differential architecture is employed to have a good commonmode noise rejection and achieve high accuracy. Compared to conventional structure, the proposed ADC reduces the number of
Z. Zhu et al. / Microelectronics Journal 44 (2013) 1132–1137
1133
Fig. 1. (a) A conventional 10-bit SAR ADC (b) the proposed SAR ADC architecture.
capacitors by a factor of 4 but requires a third reference voltage VCM which is designed to 1/2 VREF. The operation of the proposed ADC is described below. At the sampling phase, the differential input signal is sampled on the top-plates of two capacitor arrays via sampling switches, and simultaneously the bottom-plates of capacitors are connected to the common-mode voltage VCM. Next, the sampling switches are open and the comparator performs the first comparison without consuming any switching energy. Once the MSB is obtained, the bottom-plates of the capacitor array which samples the higher input voltage are reconnected to ground and the other capacitor array remains unchanged. Thus, the voltage of capacitors on the higher voltage potential side is level-shifted down by 1/2 VREF. The capacitor array consumes no switching energy in this operation. After the MSB comparison, the different reference voltages will be chosen for the differential capacitor arrays, as shown in Table 1. If MSB¼1, the positive and negative reference voltages on the VXP side will be VCM and VGND. On the VXN side, the positive and negative reference voltages will be VREF and VCM. Then the ADC performs monotonic switching procedure for the following successive approximation operation which is similar as the scheme in Ref. [5]. According to the comparator output, the largest bitcapacitor C8 on the lower voltage potential side is switched from VCM to VREF or from ground to VCM and the other bit-capacitor (on the higher voltage potential side) remains unchanged. Then the comparator begins the next comparison. The ADC repeats the producer until the LSB is decided. During the monotonic switching procedure, the proposed scheme only switches one capacitor for each bit cycle, resulting in less switching activity and lower energy. The successive approximation wave for the proposed switching scheme is shown in Fig. 2.
Table 1 Different reference voltages are chosen for differential capacitor arrays according to first comparison result. Differential
MSB ¼1
MSB ¼0
input
Positive side Negative side Positive side Negative side VREF VCM
Positive reference VCM Negative reference VGND
VIP
Sample
1
2
VREF VCM
3
4
VCM VGND
5
6
1/2VREF
VIN Level-shifting
Monotonic switching procedure
Fig. 2. Waveform of proposed switching scheme.
The average switching energy for an N-bit conventional SAR ADC can be expressed as [5] N
Eavg;conv ¼ ∑ 2Nþ12i ð2i 1ÞCV 2REF
ð2Þ
i¼1
2.2. Switching energy To further explain the proposed switching scheme, a 3-bit differential SAR ADC as shown in Fig. 3 is used. The quantitative energy consumption of each switching phase for all possible conversions is also shown in the figure. For the proposed switching scheme, the comparator performs the first comparison without consuming any switching energy. After the MSB is determined, the voltage of capacitors on the higher voltage potential side is levelshifted down by 1/2 VREF. As a result, the 2nd-MSB can be decided. There is no energy consumed in this step as the chargeredistribution is completely passive. Then the ADC performs monotonic switching procedure for the subsequent successive approximation operation. For an N-bit SAR ADC using the proposed switching scheme, if each digital output code is equiprobable, the average switching energy can be derived as N2
Eavg;tri_level ¼ ∑ ð2Ni5 ÞCV 2REF i¼1
ð1Þ
The average switching energy for a 10-bit conventional SAR ADC is 1365.3CV 2REF while the average switching energy for a 10-bit SAR ADC using the proposed switching scheme is only 31.88 CV 2REF . The proposed scheme achieves 97.66% switching energy saving with respect to the conventional one. Energy saving [4] and monotonic switching [5] schemes provide only 56% and 81% reductions, respectively. A comparison of switching energy for the reported switching schemes versus the output code is shown in Fig. 4. 2.3. Linearity The unit capacitor in the SAR ADC capacitor array is typically limited by matching requirements. Assuming the unit capacitor is modeled with a nominal value of C u and a standard deviation of su . For the conventional switching scheme, the mid-code transition is considered as the worst case, since at this transition, all the capacitors change their state. A conventional differential N-bit binary-scaled DAC is composed of 2 2N C u -elements, with an LSB step of 2C u (the factor of 2 arises from the differential implementation) [7]. At the MSB code transition all capacitors are switched,
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Fig. 3. Switching sequence and energy consumption of 3-bit SAR ADC with proposed method.
1800
Conventional Energy saving Monotonic Proposed
Switching Energy (CV2REF )
1600 1400
Clk
VP
M1
1200
C lkb
M0
M11 M9 OUTN
VN
M2
AP
1000
AN
800
M3
600
M10 M12
C lk b
OUTP
M5
M6
M8
M7
AN
AP Clk
M4
400
OUTP OUTN
200
Valid
Fig. 5. Fully dynamic comparator.
0
0
100
200
300
400
500
600
700
800
900
1000
CODE
capacitor arrays use MIM capacitors. The size of unit capacitor is set to 6 6 mm2 to reduce the nonlinearity caused by mismatch and the capacitance of a unit cell is about 35 fF. The input capacitance of the proposed SAR ADC is about 8.96 pF. To reduce the parasitic capacitance of routing, the binary-weight capacitor array is laid out based on partial common-centroid layout strategy [1].
Fig. 4. Switching energy versus output code.
leading to a s of: pffiffiffiffiffiffiffiffiffiffiffi 2Nþ1 su sDNL;conv ¼ ðLSBÞ 2C u
ð3Þ
For the proposed switching scheme, benefiting from top-plate sampling and level shifting technique, the MSB and 2nd-MSB are determined mismatch-independently, therefore, the worst case DNL occurs at 1/4 VFS and 3/4 VFS. At these two transitions, 2 2N2 C u -elements are switched, resulting in a s of: pffiffiffiffiffiffiffiffiffiffiffi 2N1 su sDNL;tri_level ¼ ðLSBÞ ð4Þ 2C u It follows from Eqs. (3) and (4) that the DNL for the proposed switching procedure is reduced by a factor of 2 with the same capacitor mismatch.
3. Circuit implementation 3.1. Capacitor array For high accuracy A/D converters, a high performance S/H circuit is needed. In this work, the bootstrapped switch circuit [5] is used to achieve low distortion and rail-to-rail operation. The
3.2. Fully dynamic comparator The two-stage fully dynamic comparator [8] shown in Fig. 5 is used to save power. The first stage is a dynamic voltage amplifier and the second stage is a latch. Since the comparator has no static biasing, the average power consumption of the comparator is proportional to the conversion rate. For one-bit/step SAR ADCs, the offset of the comparator does not affect the accuracy and only causes the shift of the entire transfer curve and slightly reduces the input voltage range [1]. The size of the transistors have been optimized for low power and low offset. A careful layout to reduce the parasitics and dynamic offset is important as well. As for the input referred noise of the comparator, the post-layout extracted capacitances at the AP/AN nodes are about 15 fF, which makes the thermal noise of the comparator in the same order as the quantization noise of the ADC [8]. The dynamic comparator adopts a P-type input pair. When the system clock Clk is high, the comparator outputs OUTP and OUTN are reset to high. When Clk turns to low, the comparator compares the input voltages and then the latch regeneration forces one
Z. Zhu et al. / Microelectronics Journal 44 (2013) 1132–1137
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Fig. 6. Implementation of main control and DAC control.
Valid Sample
Main_Control 10
Main_Control 9
Clk10
Sample
DAC_Control 10
Main_Control 2
Clk9 P10 N10
DAC_Control 9
Main_Control 1
Clk2 P9 N9
DAC_Control 2
Clk1 P2 P10 P9
N2
P2 OUTP
OUTP OUTN
Output Latch
Fig. 7. Simplified overview of digital circuits.
Fig. 8. Timing diagram.
output to high and the other to low. Consequently, the Valid signal is pulled to high to enable SAR logic circuits. 3.3. SAR dynamic logic circuits To implement the analog components of the ADC in a powerefficient way, the energy-efficient tri-level based capacitor switching procedure and fully dynamic comparator are used. However, the power consumption of digital circuits is still relatively large. Therefore, the digital power consumption also needs to be minimized to achieve a low overall power consumption. For this purpose, dynamic logic [9] is introduced to reduce the complexity of digital circuits. By using dynamic logic instead of complementary logic, less transistors are needed, thus offering a better performance in speed and in power consumption. Fig. 6 shows the dynamic logic implementation of main control and DAC control. The main control circuits function as a shift register and the DAC control circuits are used to sample the output of the comparator. Fig. 7 shows the overall architecture of the digital circuits for the SAR ADC. Output latches are used to store the digital codes for the entire conversion period until a new conversion is completed. At the sampling phase, all the outputs of main control circuits are reset to low. The operation of one dynamic logic cell is as follows.
Fig. 9. Capacitor switch buffer control logic.
At the rising edge of Valid, Clki is precharged to VDD. At the falling edge of Valid, the output Q is reset to VDD and Clki is pull down to ground. The DAC control circuits sample the output of comparator when both Clki and Valid are high. The corresponding timing diagram is shown in Fig. 8. Note P10/N10 is reset to low and P2–P9/ N2–N9 are set to high at sampling phase. The capacitor switch buffer control signals are generated by the combination logic as shown in Fig. 9. Inverters and CMOS transmission gates are used as switch buffers.
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Table 3 Performance summary and comparison.
Technology Resolution (bit) Supply (V) Sampling rate (Hz) Input range (Vpp) Power (μW) SFDR (dB) SNDR (dB) ENOB (bit) FOM (fJ/conversionstep) n
Fig. 10. Layout of the proposed ADC.
[1]n
[2]n
[7]n
[8]n
[9]nn
Proposednn
130 nm 10 1.0 1K 1.78 0.053 67.6 56.7 9.12 94.5
180 nm 12 1.0 100 K 2 25 71 65.3 10.55 165
90 nm 8 1.0 10 M 0.83 26.3 N/A 48.5 7.77 12
65 nm 10 1.0 1M 1.25 1.9 N/A 54.4 8.75 4.4
65 nm 8 1.0 50 M N/A 192.8 72 49.9 7.99 15
180 nm 10 1.0 200 K 1.8 1.33 78.49 60.54 9.76 7.7
Measured results. Post-layout simulation results.
nn
0
Power(dB)
After the parasitics, capacitor arrays still consume a large part of the total power. This can be improved by implementing capacitor arrays in more advanced technology or using smaller size of unit capacitor. To compare the proposed ADC with other state-of-the-art SAR ADCs, the well-known figure-of-merit (FOM) equation is used.
SFDR=78.49dB SNDR=60.54dB [email protected]
-20 -40 -60 -80 -100
FOM ¼ 0
10
20
30
40
50
60
70
80
90
100
Frequency(KHz) Fig. 11. FFT spectrum of the proposed ADC at 200KS/s.
Table 2 Power consumption distribution of main components.
Power minff s ; 2 ERBWg 2ENOB
ð5Þ
where the fs is the sampling rate, and the ENOB is the effective number of bits at the effective resolution bandwidth (ERBW). The FOM of the proposed ADC is 7.7 fJ/conversion-step at 200KS/s and a 1.0 V supply. Table 3 summarizes the performance of the proposed ADC and shows a comparison to other state-of-the-art SAR ADCs.
Components
Power (μW)
Percentage (%)
5. Conclusion
Capacitor arrays and switches Comparator SAR logic and output latch Switch control logic Parasitics Overall
0.36 0.17 0.27 0.08 0.45 1.33
27.1 12.8 20.3 6.0 33.8 100
In this paper, an energy-efficient tri-level based capacitor switching procedure for SAR ADCs was presented. The proposed switching procedure leads to both lower switching energy and less unit capacitors as compared with the conventional method. With the proposed switching procedure and fully dynamic design, the SAR ADC consumes 1.33 mW at a sampling rate of 200KS/s and achieves an ENOB of 9.76 bit, offering an energy efficiency of 7.7 fJ/ conversion-step.
4. Post-layout simulation results The ADC is implemented in 1P6M 0.18 mm 1.8 V CMOS process. The active area of the ADC is 0.092 mm2, as shown in Fig. 10. In the proposed SAR ADC, both the supply and DAC reference voltage (VREF) are set to 1.0 V, thereby the input signal swing of the ADC is rail-to-rail (2Vpp). However, the parasitic capacitance of the capacitor arrays and comparator input transistors induces a gain error, thus the real input signal range is 1.8 Vpp. Post-layout simulation was performed to characterize the dynamic performance of the ADC. The 1024-point FFT spectrum of the proposed ADC is shown in Fig. 11, for a sinusoidal wave input at 94.7 KHz and sampling rate of 200KS/s. The SNDR is 60.54 dB providing an ENOB of 9.76 bit. The proposed ADC consumes 1.33 mW from a 1.0 V supply. Table 2 list the distribution of power consumption of the main components, where the parasitic component is obtained by subtracting the schematic-based result from the post-layout result. As shown in Table 2, the power consumption of the undesired parasitics is a major contributor to the total power. For low-speed circuits, the power of interconnect is more significant than that of transistors because transistor dimensions are relatively small.
Acknowledgments This work was supported by the National Natural Science Foundation of China (61234002, 61006028), the National Hightech Program of China (2012AA012302, 2013AA014103) and Ph.D. Programs Foundation of Ministry of Education of China (20120203110017). References [1] D. Zhang, A. Bhide, A. Alvandpour, A 53-nW 9.1-ENOB 1KS/s SAR ADC in 0.13 μm CMOS for medical implant devices, IEEE J. Solid-State Circuits 47 (7) (2012) 1585–1593. [2] Naveen Verma, Anantha P. Chandrakasan, An ultra low energy 12-bit rateresolution scalable SAR ADC for wireless sensor nodes, IEEE J. Solid-State Circuits 42 (6) (2007) 1196–1204. [3] Ginsburg, B.P., Chandrakasan, A.P, An energy-efficient charge recycling approach for a SAR converter with capacitive DAC, in: IEEE International Symposium on Circuits and Systems, Kobe, Japan, May 2005, pp. 184–187. [4] Y.K. Chang, C.S. Wang, C.K. Wang, A 8-bit 500KS/s low power SAR ADC for biomedical application, in: IEEE Asian Solid-State Circuits Conference, Jeju, Korea, 228–231, November 2007.
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