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s SAR ADC in 90-nm CMOS for Portable Biomedical Applications
Microelectronics Journal 56 (2016) 81–96
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Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
A 200-nW 7.6-ENOB 10-KS/s SAR ADC in 90-nm CMOS for Portable Biomedical Applications Tasnim B. Nazzal a, Soliman A. Mahmoud a,b,n, Mohamed O. Shaker c a
Electrical and Computer Engineering Department, University of Sharjah, UAE Electrical Engineering Department, Fayoum University, Egypt c Electrical and Computer Engineering Department, University of Louisiana at Lafayette, USA b
art ic l e i nf o
a b s t r a c t
Article history: Received 17 March 2016 Received in revised form 16 June 2016 Accepted 4 August 2016
This paper presents an 8-bit low-power clock gated successive approximation analog to digital converter (SA-ADC) using D-flip flop (D-FF) unit for biomedical applications. The architecture of the proposed SAADC is implemented using the sample and hold (S/H) circuit which is based on a sampling transistor with dummy switch, double-tail dynamic latched comparator, the traditional binary weighted capacitor array single ended DAC and a modified clock gated successive approximation register (SAR) controller logic. The SAR controller is implemented using D-FF. The layout and extraction of the proposed low-power clock gated SA-ADC using D-FF unit are done using L-edit and simulated using 90 nm CMOS technology file on LT-spice-IV. According to the simulation results, the low-power clock gated SA-ADC using D-FF unit consumes 200 nW from 1 V power supply without additional calibration or analog circuits. It has signal-to-noise ratio (SNR) of 53.8 dB, peak spurious-free dynamic range (SFDR) of 54.2 dB, and a signalto-noise-and distortion ratio (SNDR) of 48 dB for a 250 Hz full scale input sine wave. It has also an effective number of bits (ENOB) of 7.6-bits, and a figure of merit (FOM2) of 0.1 pJ/Conversion-step. It achieves þ 0.34/ 0.3 and þ 0.79/ 0.58 of Differential non-linearity (DNL) and integral non-linearity (INL) errors respectively. Furthermore, the low-power clock gated SA-ADC using D-FF unit consumes 88.76 nW from 0.85 V power supply without additional calibration or analog circuits. With 0.85 V supply voltage, it has SNR, SFDR and SNDR of 54.6 dB, 39.19 dB and 37.92 dB respectively for the same input sinewave. It achieves ENOB of 6-bits with (FOM2) of 0.13 pJ/Conversion-step. It has DNL and INL of þ0.38/ 0.28 LSB and þ 0.9/ 0.85 LSB respectively. The digitized of real recorded beta EEG signal is precisely reconstructed by the proposed SA-ADC. & 2016 Elsevier Ltd. All rights reserved.
Keywords: EEG Binary weighted Dynamic Clock gated Double-tail Low power
1. Introduction The biomedical electronics world is rapidly changing with high future potential. With new technology, new designs with more features are placed into the biomedical devices. Nowadays, integrated circuit technology was developed in which the medical diagnostic systems can be miniaturized to portable devices. This kind of technology allow people to monitor their medical condition regardless of their age or location using small mobile device such as a smartphone or tablet. These mobile devices are preloaded with healthcare applications and it consists of mobile healthcare sensor, device, server and medical service which make it possible to perform these tasks easily from any location. Various n Corresponding author at: Electrical and Computer Engineering Department, University of Sharjah, UAE. E-mail addresses: [email protected] (T.B. Nazzal), [email protected] (S.A. Mahmoud), [email protected] (M.O. Shaker).
http://dx.doi.org/10.1016/j.mejo.2016.08.004 0026-2692/& 2016 Elsevier Ltd. All rights reserved.
biomedical signals will be sensed by the sensor such as: sleep monitoring, heart rate, skin temperature, stress, electrocardiogram and blood pressure. After that, these biomedical signals will be transferred to the server by the device which will stored and analyzed it. An additional benefit of this approach is such devices can be secured and controlled remotely via medical service [1]. Furthermore, the Electroencephalogram (EEG) is an important biomedical diagnostic technique for medical and consumer applications. Fig. 1 shows the block diagram of portable EEG detection system which is designed based on gain/filtering interleaved architecture (GFIA). It consists of three interchanged amplifier/ filter stages, which are cascaded fully differential instrumentation amplifier (IA) with high pass filter (HPF), fully differential dualnotch low pass filter (DNLPF), and differential input single output programmable gain amplifier (PGA). The instrumentation amplifier is the first block in the EEG detection system. It is used to remove the DC offset and the flicker noise. Due to 50/60 Hz AC power line interference, the notch filter is used to reject this frequency and its harmonics, which appears within the ranges of EEG
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DNLPF IA with HPF
ADC
PGA 150 Hz 50 Hz
Fig. 1. Portable EEG detection system block diagram [2].
Sample and Hold Circuit (S/H)
Vin
Comparator Successive Approximation Register (SAR)
Digital-to-Analog Converter (DAC)
Vref
Fig. 2. Block diagram of a single ended DAC based SAR ADC architecture [8].
Ø
Vin
Ø
Vout,sampled
M1 W = 540nm L = 90nm
M2 Cs
W = 270nm L = 90nm
Fig. 3. Basic sample and hold circuit with dummy switch [3].
frequency spectrum. Moreover, the designed notch filter provides low pass feature to allow the different EEG frequency ranges to pass without any unwanted signal. The PGA is used to provide the EEG signal with more controllable gain to overcome the attenuation provided by the notch filter to the EEG signal; hence, it maximizes the dynamic range of the overall system. The ADC digitizes the signal to be easily utilized by DSP unit. Therefore, using this architecture supports to have more relaxed design for the DNLPF and ADC, and allows partial attenuation of noise and interference signals to be taken by the PGA. This helps the dynamic range required by the ADC to be relaxed as well. The combined gain/filtering operation ensures that the out-of-band and the inband signals are attenuated while the desired EEG signal is amplified [2]. Analog-to-digital converter (ADC) is considered as one of the main electronic blocks in the biomedical systems and healthcare
integrated circuits. It becomes a bottleneck in data processing applications and it limits the performance of the overall system. Low power design and high resolution ADC are the main requirements in the healthcare integrated circuits [1]. Sigma-delta ADC is a proper choice for high resolution ADC where the successive approximation analog to digital converter (SA-ADC) is a proper choice for low power ADC [3]. The objective of this paper is to propose an 8-bit low-power clock gated SA-ADC without additional calibration or analog circuits for portable biomedical applications. It is a proper choice for medium resolution, medium speed and moderate circuit complexity which meets the requirements of portable biomedical applications [3]. The architecture of the SA-ADC used in this work is single ended DAC based and it consists of a sample and hold (S/H) circuit, a comparator, a successive approximation register (SAR) controller in addition to an 8-bit digital to analog converter (DAC). In any digital circuit, the clock signal is the main source of dynamic power consumption due to its high frequency. Therefore the digital circuit SAR logic considers one of the main sources of power consumption in SA-ADC. The second main source of power consumption comes from the comparator. Therefore, the proposed power efficient SA-ADC is derived from the use of double-tail dynamic comparator and clock gated SAR logic. Furthermore, the low power dissipation is behind the use of the simplest S/H and DAC circuits. The proposed low-power clock gated SA-ADC is simulated using 90 nm CMOS technology file on LT-spice-IV. It is simulated under 1 V supply voltage with sampling frequency of 10 KHz and speed of 100 KHz which are reasonable for 250 Hz, 500 mVp-p input sine wave and 8-bit ADC. In addition to that, the proposed low-power clock gated SA-ADC has been compared with previous published paper including recent published paper. In [3,4] a single ended SAR ADC has been proposed which consists of sample and hold (S/H) circuit with dummy switch, static comparator, binary weighted digital-to-analog converter (DAC) and conventional successive approximation register (SAR). Both of them are DAC based SAR ADC architecture. The main differences between them are the technology in which [3] used TSMC 0.25 mm technology and [4] used 180 nm CMOS technology. Furthermore, the digitized ECG signal in [3] has been precisely reconstructed using a novel reconstruction circuit. No additional analog circuits and/or digital calibration circuits have been used in [3,4]. In [5] a single ended charge redistribution SAR ADC architecture has been proposed in which the sample and hold (S/H) circuit samples the analog input signal on the digital-to-analog converter (DAC) capacitors array (charge-recycling method for capacitors switching is used). It used a splitting capacitor array
Fig. 4. Sampled output Voltage ( Vout,sampled ) with sampling frequency of 10 KHz.
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Fig. 5. Noise spectrum of ( Vout,sampled ) over bandwidth of 500 Hz.
VDD
Ø
M13
W=180 nm L=90 nm
W=990 nm L=90 nm
W=990 nm L=90 nm
M7
M8
WN=180 nm WP=180 nm LN=90 nm LP=90 nm Vout-
WN=180 nm WP=180 nm LN=90 nm LP=90 nm
Vout+
M11
M6
M5
W=990 nm W=990 nm L=90 nm L=90 nm
M12
W=990 nm W=990 nm L=90 nm L=90 nm
input-referred noise and a small input-offset voltage. Besides, a low supply voltage can be used in the time-domain comparator because it consists of inverters only. Therefore, an additional digital calibration circuits have been used in [6]. A differential charge redistribution SAR ADC architecture has been proposed in [7]. It used the monotonic switching procedure in the digital to analog converter (DAC) topology and successive approximation register (SAR) which consists of array of Flip Flops (FFs) with DAC switch control logic. Two stage dynamic comparator has been used in this SAR ADC. No additional analog circuits and/or digital calibration circuits have been used in [7]. This paper is organized as follows: Section 2 shows the key building blocks of the proposed SA-ADC including S/H circuit, comparators circuit, DAC circuit and SAR controller. Section 3 presents SA-ADC layout, EEG signal reconstruction and performance evaluation of the proposed SA-ADC. Section 4 concludes the paper.
VDD 2. ADC key building blocks W=180 nm L=90 nm
W=180 nm L=90 nm
Ø
M10
M9
W=180 nm L=90 nm
Vin+
M1
Ø VBias
M2
Vin- W=180 nm L=90 nm
M3 W=180 nm L=90 nm
M4
W=180 nm L=90 nm
Fig. 2 illustrates a block diagram of single ended DAC based SAR ADC [8]. The analog to digital conversion is based on the binary search algorithm. At the sampling phase, the S/H circuit stores the analog signal. The comparator determines the polarity of the difference between the reference voltage and the sampled analog signal. After that, the comparator output triggers the SAR controller which feeds the digital to analog converter (DAC) to prepare the reference voltage for the next comparison. In this algorithm, each bit needs one clock cycle to be determined. Therefore, the SAADC needs n clock cycles to complete an n-bit conversion [8]. The following subsections introduce the analysis of each building block of the proposed low-power clock gated SA-ADC. 2.1. Sample and Hold (S/H) circuit
Fig. 6. Double-tail dynamic latched comparator [11].
method in the DAC topology, static rail to rail comparator with current driven bulk technique and offset cancellation is implemented, digital control logic (DCL) and shift register. Therefore, an additional analog circuits and digital calibration circuits have been used in [5]. A differential charge redistribution SAR ADC architecture has been proposed in [6]. It proposed a digital-domain calibration method for a split-capacitor digital to analog converter (DAC). It calibrates the nonlinearities of SAR ADC due to the DAC capacitance mismatch. It uses a time domain comparator which has low
The objective of the propose low-power clock gated SA-ADC is to achieve minimum power consumption. Therefore, it has been focused on S/H circuits without active block and/or supply voltage type. A study was done in [9] on S/H circuit types. As a result of this study, the basic S/H circuit with dummy switch shown in Fig. 3 was found the best candidate for single ended low power and high performance SA-ADC architecture. Basic S/H circuit with dummy switch is considered one of the most common methods that is used to overcome the charge injection and clock feedthrough effect. As shown in Fig. 2, M2 is a dummy switch with its source and drain shorted. It is placed in
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Fig. 7. Double-tail dynamic latched comparator output when Vin ¼0.25 V at speed of 80 KHz.
Fig. 8. Zoomed double-tail dynamic latched comparator output. Table 1 Double-tail dynamic latched comparator simulation results. Frequency Parameters No. of transistors
Low (250 Hz) 13
Dynamic Range of Vin-Based on the Dynamic Range of Vin þ (V)
Vin þ Vin þ Vin þ
0–0.5 0.15–0.45 0.1–0.6 0.18–0.5 0.2–0.7 0.22–0.54
Power consumption
Vin þ VinVin þ VinVin þ Vin-
0–0.5 106.7 nW 0.25 0.1–0.6 92.8 nW 0.35 0.2–0.7 91.8 nW 0.45
feedthrough will be suppressed [3]. A simulation was done for basic S/H circuit with dummy switch using 90 nm CMOS technology on LT Spice IV. Fig. 4 illustrates the sampled output voltage for a 250 Hz 500 mVp-p sine wave. For the aspect ratios shown in Fig. 2, basic S/H circuit with dummy switch achieved signal-to-noise and-distortion ratio (SNDR) of 54.39 dB. The sampling capacitor value was chosen based on the highest SNDR. It is chosen to be 5 pf. Fig. 5 illustrates the noise spectrum with total RMS output noise of 26.57 μV. 2.2. Comparator circuit
series with M1 having a complement clock of Ø. When M1 turns OFF, and M2 turns ON, M2 will absorb the channel charge deposited on Cs. The following equations express the injected charge Δq1 and the absorbed charge Δq2 respectively as follows:
Δq1 =W1L1Cox(VDD − Vin − Vtn1)
(1)
Δq2 =W2L 2Cox(VDD − Vin − Vtn1)
(2)
In order to achieve (Δq1 ¼ Δq2), the channel width of M2 should be half that of M1 assuming the channel length of both transistors is equal. Thus, the charge injection and clock
There are two types of comparators, static comparators, and dynamic comparators. The trend of achieving both higher speed and lower power consumption in high-to-medium speed applications makes the dynamic comparators very attractive [10]. It is also energy efficient design due to non-consumption of static current in contrast to the static comparator [10]. Therefore, double-tail dynamic latched comparator has been selected in the lowpower clock gated SA-ADC. Fig. 6 shows a double-tail dynamic latched comparator. Many dynamic comparator problems can be compensated using doubletail dynamic comparator. It uses one tail for the input stage and other for the latching stage as shown in Fig. 6. This configuration has less stacking and therefore can operate at lower supply voltages. Furthermore, the double tail enables large current for fast latching independent of the common mode voltage at the latching
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Fig. 9. Schematic diagram of binary weighted switched capacitor array DAC [3]. Table 2 Binary weighted switched capacitor array DAC simulation results. Digital input Calculated value (V) Measured value (V) Percentage error (%) 0000 0000 1000 0000 1000 1000 1100 1100 1100 0000 1111 0000 1111 1100 1111 1111
0 0.5 0.53 0.79 0.75 0.93 0.98 0.99
0 0.5 0.53 0.77 0.73 0.9 0.95 0.96
0 0 0 2.5 2.6 3.2 3 3
stage and a small current for low offset and noise at the input stage [11]. During the reset phase (ؼ0), transistors M9 and M10 precharge the gate of M11 and M12 to (VDD). Accordingly Vout þ and Vout will be high. After the reset phase, the tail transistors M3 and M13 turned ON (ؼVDD). At the drains of the differential pair nodes, the common mode voltage drops monotonically with a rate defined by (IM3Cdifferential pair drains) and on top of this, an input dependent differential voltage (ΔVDi) will build up. The intermediate stage formed by M11 and M12 passes (ΔVDi) to the cross coupled inverters and also provides additional shielding between the input and output which results in less kickback noise. As soon as the common mode voltage at the drains of the differential pair nodes is not enough for M11and M12 to clamp its drain to ground, the inverters starts to regenerate the voltage difference. The ideal
operating point (VCM) and the timing of various phases can be tuned with the transistor sizes. As a result, the advantages of the double tail topology, it has better optimization of the balance between speed and offset independently, power and common mode voltage. In addition to that, it has a better isolation between the input and output of the comparator which results in less kickback noise and is well suited to operate under low supply voltages with low power consumption [11]. A simulation was done for the double-tail dynamic latched comparator using 90 nm CMOS technology on LT Spice IV under 1 V supply voltage, 0.55 V bias voltage and speed of 100 KHz in order to fit the 8-bit resolution. Figs. 7 and 8 show the double-tail dynamic latched comparator output when Vin is 0.25 V and a zoomed part of it respectively. For the transistor aspect ratios shown in Fig. 6, Table 1 shows the double-tail dynamic latched comparator simulation results. As a result, the double-tail dynamic latched comparator achieves the requirements of low power consumption, medium speed and proper dynamic range for low frequency applications. 2.3. Digital-to-analog converter (DAC) The traditional binary weighted capacitor array DAC has been chosen for the proposed low-power clock gated SA-ADC. Fig. 9 shows a schematic diagram of an 8-bit binary weighted switched capacitor array DAC which consists of nine switches from S0 to S8. S0 is implemented using an NMOS switch. S1 to S8 are
Fig. 10. DAC output voltage for (10,000,000) digital input.
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Fig. 11. Modified clock gated SAR logic block diagram [14].
Fig. 12. Schematic diagram of controller1 [14].
implemented using an NMOS and PMOS switches and these switches are controlled by the successive approximation register (SAR) controller. Each capacitor in the binary weighted array has a value of [4,12] i−1
Ci = 2
C0 where i = {1, 2, …8}
(3)
where C0 is the value of the unit capacitor in the DAC. The power source of these passive capacitor array is the reference voltage (Vref). By calculating the required charge of all the capacitors during charging and discharging periods, the power consumption of (Vref) supply when the input voltage Vin is applied can be analyzed and it is [12,13]
⎛V ⎞ 9 PVref ( Vin )=⎜⎜ ref ⎟⎟ ∑ Qci ⎝ T ⎠ i=1
VDAC7 = Vref
(5)
where Ctotal is the total capacitance of the DAC and the charge supplied by (Vref) in the second cycle can be calculated:
Qc 2 = C8⎡⎣ Vref −VDAC8 − ( 0 − 0)⎤⎦
)
(7)
In case of Q 8=1, then the charge that stored in C8 in the second cycle will be shared with C7 in the third cycle, so the charge provided by (Vref) in the third cycle is: Qc3 = C7⎡⎣ Vref −VDAC7) − ( 0−VDAC8 ⎤⎦ + Q 8C8⎡⎣ Vref −VDAC7) − ( Vref −VDAC8 ⎤⎦
(
)
)
(
(
)
)
(6)
(8)
– The operation is continued for the remaining switches in the same technique, the output voltage and the charge can be calculated in each cycle in the same way by using the general expression for each. The general expression for Qci is
⎡ ⎤ Qci = C10 − i⎣ Vref − VDAC( 10 − i) + VDAC( 11 − i) ⎦
(
+
)
8
∑ j = 11− i Q jCj( VDAC( 11− i) – VDAC( 10− i)), i € {3, . . , 9}
(9)
and the general expression for (VDACi) is: 8
VDACi = Vref
C8 Ctotal
C7 + Q 8C8 . Ctotal
(
(4)
– In the first cycle, all the capacitors are connected to ground, so the total charge supplied by Vref is zero. – In the second cycle the most significant bit (MSB) switch S8 is switched to (Vref) while the other capacitor are kept connected to ground, then the output voltage of the DAC is:
(
– In the third cycle, S7 will be switched to (Vref) and the output voltage of the DAC is
= C7 Vref −VDAC7 − VDAC8 + Q 8C8 VDAC8−VDAC7
where T is the period in which the DAC take it to convert a sample and QCi is the total charge supplied by (Vref) during the ith cycle to the DAC. The operation of the binary weighted switched capacitor array can be summarized as follows [8]:
VDAC8 = Vref
If VDAC8 4Vin, Q8 is 1 and S8 will be kept connected to (Vref), otherwise Q8 is 0 and S8 will be switched to ground.
Ci + ∑ j = i + 1 Q jCj Ctotal
(10)
where i¼ {0,..., 7} and it is the number of the capacitor switched to (Vref) in each cycle and Ctotal is the total capacitance of the DAC. – The power consumed by the reference voltage can be estimated using the below equation
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Cout
Fig. 13. Schematic diagram of controller2 [14].
PVref ( Vin ) =
fclk 9
⎛ 5 2 1 2⎞ 28C0⎜ VDD – Vin⎟ ⎝6 2 ⎠
W= 180n L= 360n
where fclk is the sampling frequency of the DAC. Smaller capacitor of C0 of 50 fF can save the power consumption. However, it will also contribute to an increase in thermal noise (it is an electronic noise due to the thermal agitation of the charge carrier regardless of any applied voltage and when it is related to a capacitor it is also called a KTC noise) which degrade the resolution of the DAC [12,13]. A simulation was done for the traditional binary weighted capacitor array DAC using 90 nm CMOS technology on LT Spice IV. It is worth noting that the value of the unit capacitor is a function of two main factors: the ADC input range and resolution, which translates into an equivalent thermal noise specification (KT/C). The unit capacitor value was chosen to trade off the design between power consumption and noise contribution. Moreover, the matching and noise in the capacitor array will dominate the accuracy of the DAC. However, the process variation resulting in matching error commonly plays a more important role compared with the thermal noise. Hence, the unit capacitor is chosen to be 50 fF. Table 2 shows the calculated value, measured value, and the percentage error of set of digital inputs. Fig. 10 illustrates the DAC output voltage for (10,000,000) digital input. The aspect ratios are illustrated in Fig. 9. The reference voltage is 1 V. 2.4. Successive approximation register (SAR) controller The successive approximation register (SAR) is the digital controller circuit that is responsible for executing the binary search algorithm technique. It is the last block of the ADC components in which the output of the SA-ADC circuit will be determined according to the comparator output. Therefore, it has a significant effect on the whole ADC performance which in turns will affect the overall system. The main sources of power consumption in the SAR converter comes from the comparator, DAC, and the SAR logic. In this section, the clock gated SAR controller logic has been chosen in order to reduce the power consumption generated by the clock system which considered one of the most power consuming components. Fig. 11 shows a modified block diagram of a clock gated SAR control logic which reported in [14]. The main concept is to insert a logic block and to connect its output to the FF clock terminal Clkg and to connect the FF inverted output terminal to its input terminal (D). As a result, the gated clock signal Clkg will be active only if the FF needs to change its state. Otherwise, the gated clock signal
Q(K+1)
Q(K)
(11)
Clkg(K)
Q(K)
Cmp
Fig. 14. Gating overhead circuit for Clkg(k) [14].
Q(n-1)
Cmp
Clkg(n-1) W= 180n L= 360n Fig. 15. Gating overhead circuit for Clkg(n 1) [14].
WN= 360n LN= 180n
WP= 360n LP= 180n Q
Clk Q D
Reset Fig. 16. D-FF unit [3].
will never be activated, and the FF will hold its state. In this case, the original clock signal Clk will be isolated and it flips its state according to its frequency and does not consider the activity of the FF input signal. Therefore, a non-redundant clock cycles and lower power consumption will be occurred [14].
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Fig. 17. Clock gated SAR logic outputs when comparator output is 0 (worst case).
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Fig. 18. Clock gated SAR logic outputs when comparator output is 1 (best case).
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Fig. 19. Schematic diagram of the proposed low-power clock gated SA-ADC.
Fig. 20. The input sinusoidal signal and the reconstructed signal for the proposed SA-ADC.
The required clock propagation for each FF is done by the logic blocks which are the controllers. As shown in Fig. 11, the modified clock gated SAR logic consists of n-FFs and (n þ1)/3 controllers. Each controller is assigned for a specific set of FFs in order to generate gated clock signals. The inverted output of each FF is connected to the corresponding controller and to the input terminal of the FF to implement the toggling operation. Each FF is triggered at the positive edge of its gated clock signal Clkg. Controller 1 and controller 2 are shown in Figs. 12 and 13 respectively. Each controller has gating overhead circuits which are shown in Figs. 14 and 15. They consists of passing transistors which responsible for clock propagation for each FF. The MSB changes its state only when it loads its zero value data {Q(n–1) ¼1, Cmp¼0: (data load)}. Furthermore, each other bit changes its state when it
loads its true data (zero value) or when it receives the data coming from the adjacent FF (shift right) {Q(k)¼ 0, Q(k þ1) ¼1:(shift right) and Q(k)¼ 1, Cmp¼0 : (data load) }. A simple AND logic is added in order to initialize the MSB to 1 as shown in Fig. 11 [14]. A simulation was done for the modified clock gated SAR logic using D-FF which shown in Fig. 16 unit on 90 nm CMOS technology on LT Spice IV under speed of 100 KHz and 1 V supply voltage. Figs. 17 and 18 show the modified clock gated SAR logic outputs when the comparator output is 0 (worst case) and when the comparator output is 1 (best case) [14]. According to the simulation results, the modified clock gated SAR control logic saves the power consumption by 87% compared to the conventional SAR control logic which reported in [3]. This result proves the theoretical part where the required number of generated clock pulses in the modified
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Fig. 21. FFT spectrum of the proposed low-power clock gated SA-ADC.
Fig. 22. (a) DNL error of the proposed SA-ADC. (b) INL error of the proposed SA-ADC.
clock gated SAR in the worst and best case scenarios are 2n and n as shown in Figs. 17 and 18 respectively. However, the required number of clock pulses are n2 for the entire conversion. The dynamic power can be calculated as:
P = CL VDD2f α
(12)
where α represents the switching activity of the signal. It is clear that the switching activity is proportional to n2 in the conventional SAR while it is proportional to n in the modified clock gated SAR. This linear relationship saves a great amount of power especially for a higher resolution register.
3. SA-ADC layout, EEG signal reconstruction and performance evaluation of the proposed SA-ADC In this section, the proposed 8-bit low-power clock gated SAADC will be presented and simulated. It is characterized by moderate speed, moderate accuracy, and low power dissipation which meets the requirements of biomedical applications [3]. Single ended DAC based SAR ADC architecture has been used. Fig. 19 illustrates the schematic diagram of the proposed lowpower clock gated SA-ADC. It consists of basic (S/H) circuit with dummy switch, double-tail dynamic latched comparator, binary
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Fig. 23. FFT spectrum of the proposed low-power clock gated SA-ADC using D-FF unit under 0.85 V supply voltage.
Fig. 24. (a) DNL error of the proposed low-power clock gated SA-ADC using D-FF unit under 0.85 V supply. (b) INL error of the proposed low-power clock gated SA-ADC using D-FF unit under 0.85 V supply.
weighted capacitor based DAC and the clock gated SAR logic controller using D-FF unit. In addition, the proposed SA-ADC has been simulated using hybrid latch-flip flop (HL-FF) which exist in the clock gated SAR logic in order to illustrate the effect of the flip flop (FF) type which is in the SAR logic on the SA-ADC performance especially on the power consumption. The proposed SAADC was simulated using 90 nm CMOS technology on LT Spice IV for a 250 Hz-500 mVp-p sinusoidal input with sampling frequency of 10 KS/s, speed of 100 KHz and supply voltage of 1 V. For the aspect ratios shown in Fig. 19, basic S/H circuit with dummy switch achieves 66.65 dB of SNDR. In order to evaluate the performance of the proposed SA-ADC, the input signal should be reconstructed from its digital output. The reconstruction method done by feeding the digital output to DAC and low pass filter respectively. Different dynamic
performance metrics were measured and calculated for the proposed SA-ADC such as signal-to-noise ratio (SNR), spurious-free dynamic range (SFDR), SNDR and effective number of bits (ENOB). It was calculated from the fast Fourier transform (FFT) spectrum of the reconstructed signal at the Nyquist input frequency along 100 cycles for full scale input sinusoidal signal. Furthermore, static performance metrics such as the differential non-linearity (DNL) and integral non-linearity (INL) errors were calculated. Figs. 20 and 21 show the input and the reconstructed sinusoidal signal and the FFT spectrum of the proposed SA-ADC. Fig. 22 show the (DNL) and (INL) errors for the proposed SA-ADC. The ENOB is calculated based on ENOB ¼((SNDR 1.76)/6.02). One more important parameter of the ADC is the figure of merit (FOM1) and (FOM2), which is calculated based on the following equations:
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Fig. 25. The layout of the proposed 8-bit low-power clock gated SA-ADC using D-FF unit under 1 V supply voltage.
Fig. 26. Real recorded input beta EEG signal.
Fig. 27. Reconstructed real recorded beta EEG signal from low-power clock gated SA-ADC using D-FF under 1 V supply voltage.
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Table 3 Simulation results and comparison with other previous works. Specifications
[3] 2015
[4] 2009
[5] 2007
[6] 2013
[7] 2015
Proposed SAR ADC using D-FF
Proposed SAR ADC using HL-FF
Technology Supply Voltage Resolution Sampling Rate (KS/sec) SNR (dB) SNDR (dB) SFDR (dB) ENOB ERBW (KHz) DNL (LSB) INL (LSB) Power Dissipation FOM1 (pJ/Conversion-Step) FOM2 (J/Conversion-Step)
0.25 mm 1V 8-bit 10 57 40.5 41 6.5 1.5 – – 1.87 mW 6.85 2.06 p
0.18 mm 1V 8-bit 10 50.5 45.2 54 7.2 1 ∓0.38/ 0.41 þ0.6/ 0.89 0.95 mW 3.23 0.64 p
0.18 mm 1V 10-bit 40 58.5 58.3 – 9.4 0.3 0.25 0.45 32.6 mW 80.4 1.206 p
0.13 mm 0.5 V 11-bit 10 KS/s – 61.6 78 9.93 – þ 0.96/ 0.97 þ 0.96/ 0.98 730 nW – 74.8 f
110 nm 1V 10-bit 20 – 56.5 64.7 9.1 – 0.44 0.58 100 nW – 9.1 f
90 nm 0.85 V 8-bit 10 54.6 37.92 39.19 6 0.4 þ 0.38/ 0.28 þ 0.9/ 0.85 88.76 nW 1.73 0.13 p
90 nm 1V 8-bit 10 58.2 39.3 40.3 6.2 0.9 þ 0.47/ 0.41 þ 0.92/ 2.6 1.47 uW 11.1 1.99 p
1V 8-bit 10 53.8 48 54.2 7.6 0.75 þ0.34/ 0.3 þ0.79/ 0.58 200 nW 0.68 0.1 p
Fig. 28. The effect of the process variation on the dynamic performance metrics of the proposed SA-ADC.
FOM1 =
FOM2 =
power 2ENOB *2*ERBW
(13)
power 2ENOB *fs
(14)
where ERBW is effective resolution bandwidth [3]. In addition to that, the power consumption were measured for the proposed SAADC. The proposed low-power clock gated SA-ADC using D-FF unit achieves 200 nW of power consumption without additional calibration or analog circuits. However, the proposed SA-ADC achieves 1.47 mW of power consumption using HL-FF in which the HL-FF has been strengthen by increasing the transistors aspect ratio in order to maintain the functionality of the SA-ADC which increase the power consumption. From the FFT shown in Fig. 21, the SNR, SFDR, and SNDR of the proposed low-power clock gated SA-ADC using
D-FF are about 53.8 dB, 54.2 dB and 48 dB respectively. It achieves ENOB of 7.6 and FOM2 of 0.1 pJ/conversion-step. In addition to that, it achieves þ0.34/ 0.3 LSB of DNL and þ0.79/ 0.58 LSB of INL as shown in Fig. 22. In addition to that, the proposed low-power clock gated SAADC using D-FF unit was tested on 0.85 V supply voltage. The latch stage in the double-tail dynamic latched comparator aspect ratios has been changed to W ¼540 nm and L ¼90 nm. Furthermore, the aspect ratio of the NMOS switch M0 in the binary weighted capacitor array DAC has been changed to W¼ 1080 nm and L¼2610 nm. As a result, it achieves 88.76 nW of power consumption. Fig. 23 illustrates the FFT spectrum of the low-power clock gated SA-ADC using D-FF under 0.85 V supply voltage. It has SNR, SFDR, and SNDR of 54.6 dB, 39.19 dB and 37.92 dB respectively. It achieves ENOB of 6 and FOM2 of 0.13 pJ/conversion-step. It achieves þ0.38/ 0.28 LSB of DNL and þ0.9/ 0.85 LSB of INL as shown in Fig. 24.
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Fig. 29. The effect of the temperature variation on the dynamic performance metrics of the proposed SA-ADC.
The 8-bit digital codes of the proposed low-power clock gated SAADC using D-FF can be used by a digital signal processor to diagnose the brain activities precisely. The proposed 8-bit low-power clock gated SA-ADC using D-FF unit has been designed, extracted, and simulated in 90 nm CMOS technology model file using L-Edit. The layout of the proposed 8-bit low-power clock gated SA-ADC using D-FF unit under 1 V supply voltage is shown in Fig. 25. Furthermore, it was tested on a real recorded beta EEG signal as an example of biomedical signals. Figs. 26 and 27 show the input real recorded beta EEG signal to the SA-ADC and the reconstructed real recorded beta EEG signal from the proposed low-power clock gated SA-ADC using D-FF unit under 1 V supply voltage. Hence, Table 3 summarizes the performance of the proposed low-power clock gated SA-ADC using D-FF and HL-FF units compared with five other designs reported in the literature including recent published designs. From this comparison, the proposed lowpower clock gated SA-ADC using D-FF unit design achieves the objective of minimum power consumption with good ENOB and without additional calibration or analog circuits. The performance of the proposed 8-bit low-power clock gated SA-ADC using D-FF has been studied and evaluated under process variation and temperature variation under supply voltage of 1 V. Figs. 28 and 29 show the effect of the process variation and temperature variation on the dynamic performance metrics of the proposed SA-ADC using D-FF. The process variation and the temperature variation does not have a great effect on the SFDR of the proposed SA-ADC. However, increasing or decreasing the mobility of the transistors has a reasonable change on the FOM and power consumption of the proposed SA-ADC. On the other hand, decreasing the temperature has a effect in increasing the FOM and power consumption of the proposed SA-ADC noting that 27 °C is the default temperature of the proposed topology.
4. Conclusion In this paper, an 8-bit low-power clock gated SA-ADC using DFF unit with moderate speed and moderate resolution for biomedical (low-frequency) applications has been proposed. It was implemented using S/H circuit which is based on a sampling transistor with dummy switch, double-tail dynamic latched dynamic comparator, binary weighted capacitor array DAC and a modified clock gated SAR logic controller. The low power dissipation is behind the use of the simplest S/H and DAC circuits. It has been designed using 90 nm CMOS technology. The proposed low-power clock gated SA-ADC using D-FF unit achieves 200 nW of power consumption without additional calibration or analog circuits. This SA-ADC consisted of mostly digital circuits in order to lower the power consumption. Furthermore, the reconstruction of the EEG signal was realized and it was consistent with the input EEG signal waveform. Hence, the 8-bit digital codes of the proposed low-power clock gated SA-ADC using D-FF unit can be processed to diagnose the brain activities precisely.
References [1] Samsung Business, Mobile Healthcare Technology Makes the Rounds. [2] Soliman A. Mahmoud and Aisha A. Alhammadi, A CMOS digitally programmable OTA based instrumentation amplifier for EEG detection system, in: Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, (ICECS), Egypt, 2015, pp. 543–546. [3] S.A. Mahmoud, H.A. Salem, H.M. Albalooshi, An 8-bit, 10 KS/s, 1.87 μW Successive approximation analog to digital converter in 0.25 mm CMOS technology for ECG detection systems, in: Proceedings of the Circuits, Systems, and Signal Processing, puplished Online: doi: 10.1007/s00034- 015–9973-z, vol. 34, 2, Feb. 2015.
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[4] S.Y. Lee, C.G. Cheng, C.P. Wang, S.C. Lee, A 1-V 8-Bit 0.95 mW successive approximation adc for biosignal acquisition systems, in: Proceedings of the IEEE International Symposium on Circuits and Systems, vol. 42, no. 10, May. 2009, pp. 649–652. [5] H.C. Chow, Y.H. Chen, 1 V 10-bit approximation ADC for low power biomedical applications, in: Proceedings of the IEEE 18th European Conference on Circuit Theory and Design, Aug. 2007, pp. 196–199. [6] J-Y. Um, Y.-J. Kim, E.-W. Song, J.-Y. Sim, H.-J. Park, A digital-domain calibration of split-capacitor DAC for a differential SAR ADC without additional analog circuits, in: Proceedings of the IEEE Transactions on Circuits and Systems-I, Regular Papers, vol. 60, no. 11, Nov. 2013, pp. 2845–2856. [7] H. Lee, S. Park, C. Lim, C. Kim, A 100-nW 9.1-ENOB 20-kS/s SAR ADC for portable pulse oximeter, in: Proceedings of the IEEE Transactions on Circuits and Systems-II, Express Briefs, vol. 62, no. 4, April 2015, pp. 357–361. [8] D.A. Johns, K. Martin, Analog Integrated Circuit Design, second ed., John Wiley & Sons, United Stated, 2008. [9] S.A. Mahmoud, T.B. Nazzal, Sample and hold circuits for low-frequency signals
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in analog-to-digital converter, in: Proceedings of the International Conference on Information and Communication Technology Research (ICTRC2015), 2015, pp. 33–36. J.M. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits, second ed., 2002. D. Schinkel, E. Mensink, E. Klumperink, E.V. Tuijl, B. Nauta, A double-tail latchtype voltage sense amplifier with 18 ps setup þ hold time, in: Proceedings of the IEEE International Solid-State Circuits Conference, ISBN 9781424408535, Feb. 2007, pp. 314–315. H.C. Hong, G.M. Lee, A 65-fJ/conversion-step 0.9-V 200-kS/s rail-to-rail 8-bit successive approximation ADC, IEEE J. Solid-State Circuits 42 (10) (2007) 2161–2168. R.E. Suarez, P.R. Gray, D.A. Hodges, All-MOS charge distribution analog-to-digital conversion techniques—Part II, IEEE J. Solid-State Circuits SSC-10 (6) (1975) 379–385. M.O. Shaker, M.A. Bayoumi, A clock gated successive approximation register for A/D converters, J. Circuits Syst. Comput. 23 (2) (2013) 1–11.
Contents lists available at ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
A 200-nW 7.6-ENOB 10-KS/s SAR ADC in 90-nm CMOS for Portable Biomedical Applications Tasnim B. Nazzal a, Soliman A. Mahmoud a,b,n, Mohamed O. Shaker c a
Electrical and Computer Engineering Department, University of Sharjah, UAE Electrical Engineering Department, Fayoum University, Egypt c Electrical and Computer Engineering Department, University of Louisiana at Lafayette, USA b
art ic l e i nf o
a b s t r a c t
Article history: Received 17 March 2016 Received in revised form 16 June 2016 Accepted 4 August 2016
This paper presents an 8-bit low-power clock gated successive approximation analog to digital converter (SA-ADC) using D-flip flop (D-FF) unit for biomedical applications. The architecture of the proposed SAADC is implemented using the sample and hold (S/H) circuit which is based on a sampling transistor with dummy switch, double-tail dynamic latched comparator, the traditional binary weighted capacitor array single ended DAC and a modified clock gated successive approximation register (SAR) controller logic. The SAR controller is implemented using D-FF. The layout and extraction of the proposed low-power clock gated SA-ADC using D-FF unit are done using L-edit and simulated using 90 nm CMOS technology file on LT-spice-IV. According to the simulation results, the low-power clock gated SA-ADC using D-FF unit consumes 200 nW from 1 V power supply without additional calibration or analog circuits. It has signal-to-noise ratio (SNR) of 53.8 dB, peak spurious-free dynamic range (SFDR) of 54.2 dB, and a signalto-noise-and distortion ratio (SNDR) of 48 dB for a 250 Hz full scale input sine wave. It has also an effective number of bits (ENOB) of 7.6-bits, and a figure of merit (FOM2) of 0.1 pJ/Conversion-step. It achieves þ 0.34/ 0.3 and þ 0.79/ 0.58 of Differential non-linearity (DNL) and integral non-linearity (INL) errors respectively. Furthermore, the low-power clock gated SA-ADC using D-FF unit consumes 88.76 nW from 0.85 V power supply without additional calibration or analog circuits. With 0.85 V supply voltage, it has SNR, SFDR and SNDR of 54.6 dB, 39.19 dB and 37.92 dB respectively for the same input sinewave. It achieves ENOB of 6-bits with (FOM2) of 0.13 pJ/Conversion-step. It has DNL and INL of þ0.38/ 0.28 LSB and þ 0.9/ 0.85 LSB respectively. The digitized of real recorded beta EEG signal is precisely reconstructed by the proposed SA-ADC. & 2016 Elsevier Ltd. All rights reserved.
Keywords: EEG Binary weighted Dynamic Clock gated Double-tail Low power
1. Introduction The biomedical electronics world is rapidly changing with high future potential. With new technology, new designs with more features are placed into the biomedical devices. Nowadays, integrated circuit technology was developed in which the medical diagnostic systems can be miniaturized to portable devices. This kind of technology allow people to monitor their medical condition regardless of their age or location using small mobile device such as a smartphone or tablet. These mobile devices are preloaded with healthcare applications and it consists of mobile healthcare sensor, device, server and medical service which make it possible to perform these tasks easily from any location. Various n Corresponding author at: Electrical and Computer Engineering Department, University of Sharjah, UAE. E-mail addresses: [email protected] (T.B. Nazzal), [email protected] (S.A. Mahmoud), [email protected] (M.O. Shaker).
http://dx.doi.org/10.1016/j.mejo.2016.08.004 0026-2692/& 2016 Elsevier Ltd. All rights reserved.
biomedical signals will be sensed by the sensor such as: sleep monitoring, heart rate, skin temperature, stress, electrocardiogram and blood pressure. After that, these biomedical signals will be transferred to the server by the device which will stored and analyzed it. An additional benefit of this approach is such devices can be secured and controlled remotely via medical service [1]. Furthermore, the Electroencephalogram (EEG) is an important biomedical diagnostic technique for medical and consumer applications. Fig. 1 shows the block diagram of portable EEG detection system which is designed based on gain/filtering interleaved architecture (GFIA). It consists of three interchanged amplifier/ filter stages, which are cascaded fully differential instrumentation amplifier (IA) with high pass filter (HPF), fully differential dualnotch low pass filter (DNLPF), and differential input single output programmable gain amplifier (PGA). The instrumentation amplifier is the first block in the EEG detection system. It is used to remove the DC offset and the flicker noise. Due to 50/60 Hz AC power line interference, the notch filter is used to reject this frequency and its harmonics, which appears within the ranges of EEG
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DNLPF IA with HPF
ADC
PGA 150 Hz 50 Hz
Fig. 1. Portable EEG detection system block diagram [2].
Sample and Hold Circuit (S/H)
Vin
Comparator Successive Approximation Register (SAR)
Digital-to-Analog Converter (DAC)
Vref
Fig. 2. Block diagram of a single ended DAC based SAR ADC architecture [8].
Ø
Vin
Ø
Vout,sampled
M1 W = 540nm L = 90nm
M2 Cs
W = 270nm L = 90nm
Fig. 3. Basic sample and hold circuit with dummy switch [3].
frequency spectrum. Moreover, the designed notch filter provides low pass feature to allow the different EEG frequency ranges to pass without any unwanted signal. The PGA is used to provide the EEG signal with more controllable gain to overcome the attenuation provided by the notch filter to the EEG signal; hence, it maximizes the dynamic range of the overall system. The ADC digitizes the signal to be easily utilized by DSP unit. Therefore, using this architecture supports to have more relaxed design for the DNLPF and ADC, and allows partial attenuation of noise and interference signals to be taken by the PGA. This helps the dynamic range required by the ADC to be relaxed as well. The combined gain/filtering operation ensures that the out-of-band and the inband signals are attenuated while the desired EEG signal is amplified [2]. Analog-to-digital converter (ADC) is considered as one of the main electronic blocks in the biomedical systems and healthcare
integrated circuits. It becomes a bottleneck in data processing applications and it limits the performance of the overall system. Low power design and high resolution ADC are the main requirements in the healthcare integrated circuits [1]. Sigma-delta ADC is a proper choice for high resolution ADC where the successive approximation analog to digital converter (SA-ADC) is a proper choice for low power ADC [3]. The objective of this paper is to propose an 8-bit low-power clock gated SA-ADC without additional calibration or analog circuits for portable biomedical applications. It is a proper choice for medium resolution, medium speed and moderate circuit complexity which meets the requirements of portable biomedical applications [3]. The architecture of the SA-ADC used in this work is single ended DAC based and it consists of a sample and hold (S/H) circuit, a comparator, a successive approximation register (SAR) controller in addition to an 8-bit digital to analog converter (DAC). In any digital circuit, the clock signal is the main source of dynamic power consumption due to its high frequency. Therefore the digital circuit SAR logic considers one of the main sources of power consumption in SA-ADC. The second main source of power consumption comes from the comparator. Therefore, the proposed power efficient SA-ADC is derived from the use of double-tail dynamic comparator and clock gated SAR logic. Furthermore, the low power dissipation is behind the use of the simplest S/H and DAC circuits. The proposed low-power clock gated SA-ADC is simulated using 90 nm CMOS technology file on LT-spice-IV. It is simulated under 1 V supply voltage with sampling frequency of 10 KHz and speed of 100 KHz which are reasonable for 250 Hz, 500 mVp-p input sine wave and 8-bit ADC. In addition to that, the proposed low-power clock gated SA-ADC has been compared with previous published paper including recent published paper. In [3,4] a single ended SAR ADC has been proposed which consists of sample and hold (S/H) circuit with dummy switch, static comparator, binary weighted digital-to-analog converter (DAC) and conventional successive approximation register (SAR). Both of them are DAC based SAR ADC architecture. The main differences between them are the technology in which [3] used TSMC 0.25 mm technology and [4] used 180 nm CMOS technology. Furthermore, the digitized ECG signal in [3] has been precisely reconstructed using a novel reconstruction circuit. No additional analog circuits and/or digital calibration circuits have been used in [3,4]. In [5] a single ended charge redistribution SAR ADC architecture has been proposed in which the sample and hold (S/H) circuit samples the analog input signal on the digital-to-analog converter (DAC) capacitors array (charge-recycling method for capacitors switching is used). It used a splitting capacitor array
Fig. 4. Sampled output Voltage ( Vout,sampled ) with sampling frequency of 10 KHz.
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Fig. 5. Noise spectrum of ( Vout,sampled ) over bandwidth of 500 Hz.
VDD
Ø
M13
W=180 nm L=90 nm
W=990 nm L=90 nm
W=990 nm L=90 nm
M7
M8
WN=180 nm WP=180 nm LN=90 nm LP=90 nm Vout-
WN=180 nm WP=180 nm LN=90 nm LP=90 nm
Vout+
M11
M6
M5
W=990 nm W=990 nm L=90 nm L=90 nm
M12
W=990 nm W=990 nm L=90 nm L=90 nm
input-referred noise and a small input-offset voltage. Besides, a low supply voltage can be used in the time-domain comparator because it consists of inverters only. Therefore, an additional digital calibration circuits have been used in [6]. A differential charge redistribution SAR ADC architecture has been proposed in [7]. It used the monotonic switching procedure in the digital to analog converter (DAC) topology and successive approximation register (SAR) which consists of array of Flip Flops (FFs) with DAC switch control logic. Two stage dynamic comparator has been used in this SAR ADC. No additional analog circuits and/or digital calibration circuits have been used in [7]. This paper is organized as follows: Section 2 shows the key building blocks of the proposed SA-ADC including S/H circuit, comparators circuit, DAC circuit and SAR controller. Section 3 presents SA-ADC layout, EEG signal reconstruction and performance evaluation of the proposed SA-ADC. Section 4 concludes the paper.
VDD 2. ADC key building blocks W=180 nm L=90 nm
W=180 nm L=90 nm
Ø
M10
M9
W=180 nm L=90 nm
Vin+
M1
Ø VBias
M2
Vin- W=180 nm L=90 nm
M3 W=180 nm L=90 nm
M4
W=180 nm L=90 nm
Fig. 2 illustrates a block diagram of single ended DAC based SAR ADC [8]. The analog to digital conversion is based on the binary search algorithm. At the sampling phase, the S/H circuit stores the analog signal. The comparator determines the polarity of the difference between the reference voltage and the sampled analog signal. After that, the comparator output triggers the SAR controller which feeds the digital to analog converter (DAC) to prepare the reference voltage for the next comparison. In this algorithm, each bit needs one clock cycle to be determined. Therefore, the SAADC needs n clock cycles to complete an n-bit conversion [8]. The following subsections introduce the analysis of each building block of the proposed low-power clock gated SA-ADC. 2.1. Sample and Hold (S/H) circuit
Fig. 6. Double-tail dynamic latched comparator [11].
method in the DAC topology, static rail to rail comparator with current driven bulk technique and offset cancellation is implemented, digital control logic (DCL) and shift register. Therefore, an additional analog circuits and digital calibration circuits have been used in [5]. A differential charge redistribution SAR ADC architecture has been proposed in [6]. It proposed a digital-domain calibration method for a split-capacitor digital to analog converter (DAC). It calibrates the nonlinearities of SAR ADC due to the DAC capacitance mismatch. It uses a time domain comparator which has low
The objective of the propose low-power clock gated SA-ADC is to achieve minimum power consumption. Therefore, it has been focused on S/H circuits without active block and/or supply voltage type. A study was done in [9] on S/H circuit types. As a result of this study, the basic S/H circuit with dummy switch shown in Fig. 3 was found the best candidate for single ended low power and high performance SA-ADC architecture. Basic S/H circuit with dummy switch is considered one of the most common methods that is used to overcome the charge injection and clock feedthrough effect. As shown in Fig. 2, M2 is a dummy switch with its source and drain shorted. It is placed in
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Fig. 7. Double-tail dynamic latched comparator output when Vin ¼0.25 V at speed of 80 KHz.
Fig. 8. Zoomed double-tail dynamic latched comparator output. Table 1 Double-tail dynamic latched comparator simulation results. Frequency Parameters No. of transistors
Low (250 Hz) 13
Dynamic Range of Vin-Based on the Dynamic Range of Vin þ (V)
Vin þ Vin þ Vin þ
0–0.5 0.15–0.45 0.1–0.6 0.18–0.5 0.2–0.7 0.22–0.54
Power consumption
Vin þ VinVin þ VinVin þ Vin-
0–0.5 106.7 nW 0.25 0.1–0.6 92.8 nW 0.35 0.2–0.7 91.8 nW 0.45
feedthrough will be suppressed [3]. A simulation was done for basic S/H circuit with dummy switch using 90 nm CMOS technology on LT Spice IV. Fig. 4 illustrates the sampled output voltage for a 250 Hz 500 mVp-p sine wave. For the aspect ratios shown in Fig. 2, basic S/H circuit with dummy switch achieved signal-to-noise and-distortion ratio (SNDR) of 54.39 dB. The sampling capacitor value was chosen based on the highest SNDR. It is chosen to be 5 pf. Fig. 5 illustrates the noise spectrum with total RMS output noise of 26.57 μV. 2.2. Comparator circuit
series with M1 having a complement clock of Ø. When M1 turns OFF, and M2 turns ON, M2 will absorb the channel charge deposited on Cs. The following equations express the injected charge Δq1 and the absorbed charge Δq2 respectively as follows:
Δq1 =W1L1Cox(VDD − Vin − Vtn1)
(1)
Δq2 =W2L 2Cox(VDD − Vin − Vtn1)
(2)
In order to achieve (Δq1 ¼ Δq2), the channel width of M2 should be half that of M1 assuming the channel length of both transistors is equal. Thus, the charge injection and clock
There are two types of comparators, static comparators, and dynamic comparators. The trend of achieving both higher speed and lower power consumption in high-to-medium speed applications makes the dynamic comparators very attractive [10]. It is also energy efficient design due to non-consumption of static current in contrast to the static comparator [10]. Therefore, double-tail dynamic latched comparator has been selected in the lowpower clock gated SA-ADC. Fig. 6 shows a double-tail dynamic latched comparator. Many dynamic comparator problems can be compensated using doubletail dynamic comparator. It uses one tail for the input stage and other for the latching stage as shown in Fig. 6. This configuration has less stacking and therefore can operate at lower supply voltages. Furthermore, the double tail enables large current for fast latching independent of the common mode voltage at the latching
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Fig. 9. Schematic diagram of binary weighted switched capacitor array DAC [3]. Table 2 Binary weighted switched capacitor array DAC simulation results. Digital input Calculated value (V) Measured value (V) Percentage error (%) 0000 0000 1000 0000 1000 1000 1100 1100 1100 0000 1111 0000 1111 1100 1111 1111
0 0.5 0.53 0.79 0.75 0.93 0.98 0.99
0 0.5 0.53 0.77 0.73 0.9 0.95 0.96
0 0 0 2.5 2.6 3.2 3 3
stage and a small current for low offset and noise at the input stage [11]. During the reset phase (ؼ0), transistors M9 and M10 precharge the gate of M11 and M12 to (VDD). Accordingly Vout þ and Vout will be high. After the reset phase, the tail transistors M3 and M13 turned ON (ؼVDD). At the drains of the differential pair nodes, the common mode voltage drops monotonically with a rate defined by (IM3Cdifferential pair drains) and on top of this, an input dependent differential voltage (ΔVDi) will build up. The intermediate stage formed by M11 and M12 passes (ΔVDi) to the cross coupled inverters and also provides additional shielding between the input and output which results in less kickback noise. As soon as the common mode voltage at the drains of the differential pair nodes is not enough for M11and M12 to clamp its drain to ground, the inverters starts to regenerate the voltage difference. The ideal
operating point (VCM) and the timing of various phases can be tuned with the transistor sizes. As a result, the advantages of the double tail topology, it has better optimization of the balance between speed and offset independently, power and common mode voltage. In addition to that, it has a better isolation between the input and output of the comparator which results in less kickback noise and is well suited to operate under low supply voltages with low power consumption [11]. A simulation was done for the double-tail dynamic latched comparator using 90 nm CMOS technology on LT Spice IV under 1 V supply voltage, 0.55 V bias voltage and speed of 100 KHz in order to fit the 8-bit resolution. Figs. 7 and 8 show the double-tail dynamic latched comparator output when Vin is 0.25 V and a zoomed part of it respectively. For the transistor aspect ratios shown in Fig. 6, Table 1 shows the double-tail dynamic latched comparator simulation results. As a result, the double-tail dynamic latched comparator achieves the requirements of low power consumption, medium speed and proper dynamic range for low frequency applications. 2.3. Digital-to-analog converter (DAC) The traditional binary weighted capacitor array DAC has been chosen for the proposed low-power clock gated SA-ADC. Fig. 9 shows a schematic diagram of an 8-bit binary weighted switched capacitor array DAC which consists of nine switches from S0 to S8. S0 is implemented using an NMOS switch. S1 to S8 are
Fig. 10. DAC output voltage for (10,000,000) digital input.
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Fig. 11. Modified clock gated SAR logic block diagram [14].
Fig. 12. Schematic diagram of controller1 [14].
implemented using an NMOS and PMOS switches and these switches are controlled by the successive approximation register (SAR) controller. Each capacitor in the binary weighted array has a value of [4,12] i−1
Ci = 2
C0 where i = {1, 2, …8}
(3)
where C0 is the value of the unit capacitor in the DAC. The power source of these passive capacitor array is the reference voltage (Vref). By calculating the required charge of all the capacitors during charging and discharging periods, the power consumption of (Vref) supply when the input voltage Vin is applied can be analyzed and it is [12,13]
⎛V ⎞ 9 PVref ( Vin )=⎜⎜ ref ⎟⎟ ∑ Qci ⎝ T ⎠ i=1
VDAC7 = Vref
(5)
where Ctotal is the total capacitance of the DAC and the charge supplied by (Vref) in the second cycle can be calculated:
Qc 2 = C8⎡⎣ Vref −VDAC8 − ( 0 − 0)⎤⎦
)
(7)
In case of Q 8=1, then the charge that stored in C8 in the second cycle will be shared with C7 in the third cycle, so the charge provided by (Vref) in the third cycle is: Qc3 = C7⎡⎣ Vref −VDAC7) − ( 0−VDAC8 ⎤⎦ + Q 8C8⎡⎣ Vref −VDAC7) − ( Vref −VDAC8 ⎤⎦
(
)
)
(
(
)
)
(6)
(8)
– The operation is continued for the remaining switches in the same technique, the output voltage and the charge can be calculated in each cycle in the same way by using the general expression for each. The general expression for Qci is
⎡ ⎤ Qci = C10 − i⎣ Vref − VDAC( 10 − i) + VDAC( 11 − i) ⎦
(
+
)
8
∑ j = 11− i Q jCj( VDAC( 11− i) – VDAC( 10− i)), i € {3, . . , 9}
(9)
and the general expression for (VDACi) is: 8
VDACi = Vref
C8 Ctotal
C7 + Q 8C8 . Ctotal
(
(4)
– In the first cycle, all the capacitors are connected to ground, so the total charge supplied by Vref is zero. – In the second cycle the most significant bit (MSB) switch S8 is switched to (Vref) while the other capacitor are kept connected to ground, then the output voltage of the DAC is:
(
– In the third cycle, S7 will be switched to (Vref) and the output voltage of the DAC is
= C7 Vref −VDAC7 − VDAC8 + Q 8C8 VDAC8−VDAC7
where T is the period in which the DAC take it to convert a sample and QCi is the total charge supplied by (Vref) during the ith cycle to the DAC. The operation of the binary weighted switched capacitor array can be summarized as follows [8]:
VDAC8 = Vref
If VDAC8 4Vin, Q8 is 1 and S8 will be kept connected to (Vref), otherwise Q8 is 0 and S8 will be switched to ground.
Ci + ∑ j = i + 1 Q jCj Ctotal
(10)
where i¼ {0,..., 7} and it is the number of the capacitor switched to (Vref) in each cycle and Ctotal is the total capacitance of the DAC. – The power consumed by the reference voltage can be estimated using the below equation
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87
Cout
Fig. 13. Schematic diagram of controller2 [14].
PVref ( Vin ) =
fclk 9
⎛ 5 2 1 2⎞ 28C0⎜ VDD – Vin⎟ ⎝6 2 ⎠
W= 180n L= 360n
where fclk is the sampling frequency of the DAC. Smaller capacitor of C0 of 50 fF can save the power consumption. However, it will also contribute to an increase in thermal noise (it is an electronic noise due to the thermal agitation of the charge carrier regardless of any applied voltage and when it is related to a capacitor it is also called a KTC noise) which degrade the resolution of the DAC [12,13]. A simulation was done for the traditional binary weighted capacitor array DAC using 90 nm CMOS technology on LT Spice IV. It is worth noting that the value of the unit capacitor is a function of two main factors: the ADC input range and resolution, which translates into an equivalent thermal noise specification (KT/C). The unit capacitor value was chosen to trade off the design between power consumption and noise contribution. Moreover, the matching and noise in the capacitor array will dominate the accuracy of the DAC. However, the process variation resulting in matching error commonly plays a more important role compared with the thermal noise. Hence, the unit capacitor is chosen to be 50 fF. Table 2 shows the calculated value, measured value, and the percentage error of set of digital inputs. Fig. 10 illustrates the DAC output voltage for (10,000,000) digital input. The aspect ratios are illustrated in Fig. 9. The reference voltage is 1 V. 2.4. Successive approximation register (SAR) controller The successive approximation register (SAR) is the digital controller circuit that is responsible for executing the binary search algorithm technique. It is the last block of the ADC components in which the output of the SA-ADC circuit will be determined according to the comparator output. Therefore, it has a significant effect on the whole ADC performance which in turns will affect the overall system. The main sources of power consumption in the SAR converter comes from the comparator, DAC, and the SAR logic. In this section, the clock gated SAR controller logic has been chosen in order to reduce the power consumption generated by the clock system which considered one of the most power consuming components. Fig. 11 shows a modified block diagram of a clock gated SAR control logic which reported in [14]. The main concept is to insert a logic block and to connect its output to the FF clock terminal Clkg and to connect the FF inverted output terminal to its input terminal (D). As a result, the gated clock signal Clkg will be active only if the FF needs to change its state. Otherwise, the gated clock signal
Q(K+1)
Q(K)
(11)
Clkg(K)
Q(K)
Cmp
Fig. 14. Gating overhead circuit for Clkg(k) [14].
Q(n-1)
Cmp
Clkg(n-1) W= 180n L= 360n Fig. 15. Gating overhead circuit for Clkg(n 1) [14].
WN= 360n LN= 180n
WP= 360n LP= 180n Q
Clk Q D
Reset Fig. 16. D-FF unit [3].
will never be activated, and the FF will hold its state. In this case, the original clock signal Clk will be isolated and it flips its state according to its frequency and does not consider the activity of the FF input signal. Therefore, a non-redundant clock cycles and lower power consumption will be occurred [14].
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Fig. 17. Clock gated SAR logic outputs when comparator output is 0 (worst case).
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Fig. 18. Clock gated SAR logic outputs when comparator output is 1 (best case).
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Fig. 19. Schematic diagram of the proposed low-power clock gated SA-ADC.
Fig. 20. The input sinusoidal signal and the reconstructed signal for the proposed SA-ADC.
The required clock propagation for each FF is done by the logic blocks which are the controllers. As shown in Fig. 11, the modified clock gated SAR logic consists of n-FFs and (n þ1)/3 controllers. Each controller is assigned for a specific set of FFs in order to generate gated clock signals. The inverted output of each FF is connected to the corresponding controller and to the input terminal of the FF to implement the toggling operation. Each FF is triggered at the positive edge of its gated clock signal Clkg. Controller 1 and controller 2 are shown in Figs. 12 and 13 respectively. Each controller has gating overhead circuits which are shown in Figs. 14 and 15. They consists of passing transistors which responsible for clock propagation for each FF. The MSB changes its state only when it loads its zero value data {Q(n–1) ¼1, Cmp¼0: (data load)}. Furthermore, each other bit changes its state when it
loads its true data (zero value) or when it receives the data coming from the adjacent FF (shift right) {Q(k)¼ 0, Q(k þ1) ¼1:(shift right) and Q(k)¼ 1, Cmp¼0 : (data load) }. A simple AND logic is added in order to initialize the MSB to 1 as shown in Fig. 11 [14]. A simulation was done for the modified clock gated SAR logic using D-FF which shown in Fig. 16 unit on 90 nm CMOS technology on LT Spice IV under speed of 100 KHz and 1 V supply voltage. Figs. 17 and 18 show the modified clock gated SAR logic outputs when the comparator output is 0 (worst case) and when the comparator output is 1 (best case) [14]. According to the simulation results, the modified clock gated SAR control logic saves the power consumption by 87% compared to the conventional SAR control logic which reported in [3]. This result proves the theoretical part where the required number of generated clock pulses in the modified
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Fig. 21. FFT spectrum of the proposed low-power clock gated SA-ADC.
Fig. 22. (a) DNL error of the proposed SA-ADC. (b) INL error of the proposed SA-ADC.
clock gated SAR in the worst and best case scenarios are 2n and n as shown in Figs. 17 and 18 respectively. However, the required number of clock pulses are n2 for the entire conversion. The dynamic power can be calculated as:
P = CL VDD2f α
(12)
where α represents the switching activity of the signal. It is clear that the switching activity is proportional to n2 in the conventional SAR while it is proportional to n in the modified clock gated SAR. This linear relationship saves a great amount of power especially for a higher resolution register.
3. SA-ADC layout, EEG signal reconstruction and performance evaluation of the proposed SA-ADC In this section, the proposed 8-bit low-power clock gated SAADC will be presented and simulated. It is characterized by moderate speed, moderate accuracy, and low power dissipation which meets the requirements of biomedical applications [3]. Single ended DAC based SAR ADC architecture has been used. Fig. 19 illustrates the schematic diagram of the proposed lowpower clock gated SA-ADC. It consists of basic (S/H) circuit with dummy switch, double-tail dynamic latched comparator, binary
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Fig. 23. FFT spectrum of the proposed low-power clock gated SA-ADC using D-FF unit under 0.85 V supply voltage.
Fig. 24. (a) DNL error of the proposed low-power clock gated SA-ADC using D-FF unit under 0.85 V supply. (b) INL error of the proposed low-power clock gated SA-ADC using D-FF unit under 0.85 V supply.
weighted capacitor based DAC and the clock gated SAR logic controller using D-FF unit. In addition, the proposed SA-ADC has been simulated using hybrid latch-flip flop (HL-FF) which exist in the clock gated SAR logic in order to illustrate the effect of the flip flop (FF) type which is in the SAR logic on the SA-ADC performance especially on the power consumption. The proposed SAADC was simulated using 90 nm CMOS technology on LT Spice IV for a 250 Hz-500 mVp-p sinusoidal input with sampling frequency of 10 KS/s, speed of 100 KHz and supply voltage of 1 V. For the aspect ratios shown in Fig. 19, basic S/H circuit with dummy switch achieves 66.65 dB of SNDR. In order to evaluate the performance of the proposed SA-ADC, the input signal should be reconstructed from its digital output. The reconstruction method done by feeding the digital output to DAC and low pass filter respectively. Different dynamic
performance metrics were measured and calculated for the proposed SA-ADC such as signal-to-noise ratio (SNR), spurious-free dynamic range (SFDR), SNDR and effective number of bits (ENOB). It was calculated from the fast Fourier transform (FFT) spectrum of the reconstructed signal at the Nyquist input frequency along 100 cycles for full scale input sinusoidal signal. Furthermore, static performance metrics such as the differential non-linearity (DNL) and integral non-linearity (INL) errors were calculated. Figs. 20 and 21 show the input and the reconstructed sinusoidal signal and the FFT spectrum of the proposed SA-ADC. Fig. 22 show the (DNL) and (INL) errors for the proposed SA-ADC. The ENOB is calculated based on ENOB ¼((SNDR 1.76)/6.02). One more important parameter of the ADC is the figure of merit (FOM1) and (FOM2), which is calculated based on the following equations:
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Fig. 25. The layout of the proposed 8-bit low-power clock gated SA-ADC using D-FF unit under 1 V supply voltage.
Fig. 26. Real recorded input beta EEG signal.
Fig. 27. Reconstructed real recorded beta EEG signal from low-power clock gated SA-ADC using D-FF under 1 V supply voltage.
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Table 3 Simulation results and comparison with other previous works. Specifications
[3] 2015
[4] 2009
[5] 2007
[6] 2013
[7] 2015
Proposed SAR ADC using D-FF
Proposed SAR ADC using HL-FF
Technology Supply Voltage Resolution Sampling Rate (KS/sec) SNR (dB) SNDR (dB) SFDR (dB) ENOB ERBW (KHz) DNL (LSB) INL (LSB) Power Dissipation FOM1 (pJ/Conversion-Step) FOM2 (J/Conversion-Step)
0.25 mm 1V 8-bit 10 57 40.5 41 6.5 1.5 – – 1.87 mW 6.85 2.06 p
0.18 mm 1V 8-bit 10 50.5 45.2 54 7.2 1 ∓0.38/ 0.41 þ0.6/ 0.89 0.95 mW 3.23 0.64 p
0.18 mm 1V 10-bit 40 58.5 58.3 – 9.4 0.3 0.25 0.45 32.6 mW 80.4 1.206 p
0.13 mm 0.5 V 11-bit 10 KS/s – 61.6 78 9.93 – þ 0.96/ 0.97 þ 0.96/ 0.98 730 nW – 74.8 f
110 nm 1V 10-bit 20 – 56.5 64.7 9.1 – 0.44 0.58 100 nW – 9.1 f
90 nm 0.85 V 8-bit 10 54.6 37.92 39.19 6 0.4 þ 0.38/ 0.28 þ 0.9/ 0.85 88.76 nW 1.73 0.13 p
90 nm 1V 8-bit 10 58.2 39.3 40.3 6.2 0.9 þ 0.47/ 0.41 þ 0.92/ 2.6 1.47 uW 11.1 1.99 p
1V 8-bit 10 53.8 48 54.2 7.6 0.75 þ0.34/ 0.3 þ0.79/ 0.58 200 nW 0.68 0.1 p
Fig. 28. The effect of the process variation on the dynamic performance metrics of the proposed SA-ADC.
FOM1 =
FOM2 =
power 2ENOB *2*ERBW
(13)
power 2ENOB *fs
(14)
where ERBW is effective resolution bandwidth [3]. In addition to that, the power consumption were measured for the proposed SAADC. The proposed low-power clock gated SA-ADC using D-FF unit achieves 200 nW of power consumption without additional calibration or analog circuits. However, the proposed SA-ADC achieves 1.47 mW of power consumption using HL-FF in which the HL-FF has been strengthen by increasing the transistors aspect ratio in order to maintain the functionality of the SA-ADC which increase the power consumption. From the FFT shown in Fig. 21, the SNR, SFDR, and SNDR of the proposed low-power clock gated SA-ADC using
D-FF are about 53.8 dB, 54.2 dB and 48 dB respectively. It achieves ENOB of 7.6 and FOM2 of 0.1 pJ/conversion-step. In addition to that, it achieves þ0.34/ 0.3 LSB of DNL and þ0.79/ 0.58 LSB of INL as shown in Fig. 22. In addition to that, the proposed low-power clock gated SAADC using D-FF unit was tested on 0.85 V supply voltage. The latch stage in the double-tail dynamic latched comparator aspect ratios has been changed to W ¼540 nm and L ¼90 nm. Furthermore, the aspect ratio of the NMOS switch M0 in the binary weighted capacitor array DAC has been changed to W¼ 1080 nm and L¼2610 nm. As a result, it achieves 88.76 nW of power consumption. Fig. 23 illustrates the FFT spectrum of the low-power clock gated SA-ADC using D-FF under 0.85 V supply voltage. It has SNR, SFDR, and SNDR of 54.6 dB, 39.19 dB and 37.92 dB respectively. It achieves ENOB of 6 and FOM2 of 0.13 pJ/conversion-step. It achieves þ0.38/ 0.28 LSB of DNL and þ0.9/ 0.85 LSB of INL as shown in Fig. 24.
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Fig. 29. The effect of the temperature variation on the dynamic performance metrics of the proposed SA-ADC.
The 8-bit digital codes of the proposed low-power clock gated SAADC using D-FF can be used by a digital signal processor to diagnose the brain activities precisely. The proposed 8-bit low-power clock gated SA-ADC using D-FF unit has been designed, extracted, and simulated in 90 nm CMOS technology model file using L-Edit. The layout of the proposed 8-bit low-power clock gated SA-ADC using D-FF unit under 1 V supply voltage is shown in Fig. 25. Furthermore, it was tested on a real recorded beta EEG signal as an example of biomedical signals. Figs. 26 and 27 show the input real recorded beta EEG signal to the SA-ADC and the reconstructed real recorded beta EEG signal from the proposed low-power clock gated SA-ADC using D-FF unit under 1 V supply voltage. Hence, Table 3 summarizes the performance of the proposed low-power clock gated SA-ADC using D-FF and HL-FF units compared with five other designs reported in the literature including recent published designs. From this comparison, the proposed lowpower clock gated SA-ADC using D-FF unit design achieves the objective of minimum power consumption with good ENOB and without additional calibration or analog circuits. The performance of the proposed 8-bit low-power clock gated SA-ADC using D-FF has been studied and evaluated under process variation and temperature variation under supply voltage of 1 V. Figs. 28 and 29 show the effect of the process variation and temperature variation on the dynamic performance metrics of the proposed SA-ADC using D-FF. The process variation and the temperature variation does not have a great effect on the SFDR of the proposed SA-ADC. However, increasing or decreasing the mobility of the transistors has a reasonable change on the FOM and power consumption of the proposed SA-ADC. On the other hand, decreasing the temperature has a effect in increasing the FOM and power consumption of the proposed SA-ADC noting that 27 °C is the default temperature of the proposed topology.
4. Conclusion In this paper, an 8-bit low-power clock gated SA-ADC using DFF unit with moderate speed and moderate resolution for biomedical (low-frequency) applications has been proposed. It was implemented using S/H circuit which is based on a sampling transistor with dummy switch, double-tail dynamic latched dynamic comparator, binary weighted capacitor array DAC and a modified clock gated SAR logic controller. The low power dissipation is behind the use of the simplest S/H and DAC circuits. It has been designed using 90 nm CMOS technology. The proposed low-power clock gated SA-ADC using D-FF unit achieves 200 nW of power consumption without additional calibration or analog circuits. This SA-ADC consisted of mostly digital circuits in order to lower the power consumption. Furthermore, the reconstruction of the EEG signal was realized and it was consistent with the input EEG signal waveform. Hence, the 8-bit digital codes of the proposed low-power clock gated SA-ADC using D-FF unit can be processed to diagnose the brain activities precisely.
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