- Email: [email protected]
An 8-bit current-steering digital to analog converter
Int. J. Electron. Commun. (AEÜ) 66 (2012) 433–437
Contents lists available at SciVerse ScienceDirect
International Journal of Electronics and Communications (AEÜ) journal homepage: www.elsevier.de/aeue
An 8-bit current-steering digital to analog converter Shu-Chung Yi ∗ National Changhua University of Education, Graduate Institute of Integrated Circuit Design, No. 1, Jin-De Road, Changhua 500, 50007, Taiwan, ROC
a r t i c l e
i n f o
Article history: Received 7 December 2010 Accepted 4 October 2011 Keywords: CMOS digital integrated circuits Current mirrors DAC Digital-analog conversion
a b s t r a c t In this paper, an 8-bit current steering digital-to-analog converter is proposed. The digital-to-analog converter contained four sets of current mirrors with different weight. The digital-to-analog converter was implemented using TSMC 0.35 m, 2P4M CMOS process. The average INL and DNL are 0.27 LSB and 0.32 LSB, respectively. At the sample rate of 100 MHz and supply voltage of 3.3 V, the DAC consumed about 27.6 mW. The SFDR was 50.9 dB. The core size is 0.024 mm2 . The digital-to-analog converter of this construction consumed less power and chip area. It is suitable for portable device application. © 2011 Elsevier GmbH. All rights reserved.
1. Introduction In recent years, the current steering converter is the dominant construction for very high speed Digital to Analog Converters (DAC). The current steering DAC has the advantages of being quite small for resolution below 10 bits, being very fast, and being more cost effective. However, the major drawback is its sensitivity to device mismatch, glitches, and current source output impedance for higher number of bits. For example, its integral non-linearity (INL) and differential non-linearity (DNL) are vulnerable to the accuracy of current sources. Generally, a self-calibrated circuit can be designed to solve these problems [1,2], but the circuit will consume more power and require a large chip area. Current steering DAC has three main designs: Binary Weighted Current Steering DAC [3], Thermometer Coded Current Steering DAC [4] and Segmented Current Steering DAC [5,6]. In a binary implementation, one bit in the digital input word directly turns a relative current source on or off, and the output sums up all the current sources that are turned on. The current value is proportional to the input binary word [7]. The binary structure is simple and requires less area and less power, as no decoding logic is required. However, its major drawback is its down-graded performance mainly due to glitches at middle code transitions and stringent matching requirement of the current sources [8]. For example, when the digital input code changes from 0111. . .1 to 1000. . .0, one MSB turn on and all the other LSB’s turn off. Glitch will be induced during the switching of input code. It is a limitation of high-speed operation of DAC. Although the die size of a binary weighted converter might be relatively small, its specifications for
∗ Tel.: +886 422959907. E-mail addresses: [email protected], [email protected] 1434-8411/$ – see front matter © 2011 Elsevier GmbH. All rights reserved. doi:10.1016/j.aeue.2011.10.003
dynamic performance are stringent. Therefore, binary weighting is not suitable for high-speed digital-to-analog conversion [9]. The thermometer-coded DAC, also called unary DAC, utilizes a number of equally weighted elements. Thermometer-coded DAC is invariably monotonic. When the digital input increases by 1 LSB, one current source is switched from negative to positive, and the analog output always increases with input signal. In comparison, the binary-weighted type manifests poorer dynamic performance than the thermometer-coded type. For a large number of bits, the digital circuits converting the binary code into thermometer code and the number of interconnecting wires become large. This implies a more complex circuit layout. Therefore, the disadvantages of the thermometer-coded DAC are its complexity, consumption of a large area, and the larger power requirement of the binary-tothermometer decoders. The segmented current steering is a very popular approach for designing digital-to-analog converters because it combines the advantages of binary-weighted and thermometer-coded designs. The segmented DAC is commonly to use a thermometer-coded approach for the top few MSB’s while using a binary-weighted approach for the lower LSB’s. In this way, the glitch is significantly reduced and accuracy is high for the MSBs. Subsequently, the circuit area is minimized with the segmented DAC (Fig. 1). 2. Construction The proposed differential mode DAC was formed by two single-ended DAC circuits. The single-ended DAC contained binaryto-thermometer (BT) decoders and current mirror circuits, as shown in Fig. 4. The current mirror circuit contained four current mirrors of different weighting. Each current mirror is controlled by a 2-bit binary to thermometer code decoder, as shown in Fig. 2. The proposed DAC has the advantage of low chip area. It is owing to
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M1
M0 Vout
I1 Fig. 1. Single-ended DAC construction.
low transistor count of this construction. The MOS transistor has larger capacitances in its gate oxide, source and drain. Moreover, less number of transistors has the possibility of less interconnection than those of more transistors. Dynamic power consumption of MOS circuits is proportional to the total capacitances of load and internal node. Low transistor count DAC has the chance for low total capacitances. Therefore, the proposed DAC has more possibility to consume low power. 2.1. Binary to thermometer (BT) decoder Fig. 2 shows the constitution circuit of one 2-bit binary to thermometer decoder. It consisted of one AND gate and one OR gate. S0 , S1 , S2 were the control signals for current mirrors. The 8-bit DAC decoder of differential mode required only eight AND gates and eight OR gates.
(W/L)M0
M2
S2 M3
R1
I0
M4
Fig. 3. Current mirror circuits of 2-bit DAC.
The current mirrors of the 8-bit single-sided DAC needed 12 NMOS transistors as switches to turn the current on or off. Iout collected all the current from current mirrors. The output Iout can be described as follows: Iout = [(B1 ∧ B0 ) + (B1 ) + (B1 ∧ B0 )](Iunit ) + [(B3 ∧ B2 ) + (B3 ) + (B3 ∧ B2 )(4Iunit )
+ [(B7 ∧ B6 ) + (B7 ) + (B7 ∧ B6 )(64Iunit ).
Fig. 4 shows a single-ended 8-bit DAC. It contained four BT decoders and four current mirrors. Each current mirror generated 2-bit DAC. Fig. 3 depicts the circuit of one 2-bit DAC. The three NMOS transistors, M2 ∼ M4 , were switches that turned on the current path. The three signals, S0 ∼ S2 , were generated by the previous BT decoder stage. I0 were the drain current of M0 mirrored from I1 , the drain current of M1 . Transistors M2 , M3 and M4 acted as switches. When they were turned on, effective resistance appeared between the drain of M1 and ground. For example, when the switch was turned on via S0 , the effective resistance of M2 appeared between the drain of M1 and the ground. There were four thermometric configurations of (S2 S1 S0 ), namely (111), (011) (001) and (000). For example, if (S2 S1 S0 ) = (011), then I1 was the total current drawn by M2 and M3 . The relationship between I0 and I1 was derived as follows:
(W/L)M1
S1
+ [(B5 ∧ B4 ) + (B5 ) + (B5 ∧ B4 )(16Iunit )
2.2. Current mirror construction
I0 = I1∗
S0
= [(S1 ∧ S0 ) + (S1 ) + (S1 ∧ S0 )](Iunit ),
(1)
where Iunit was the unit output current of the 2-bit DAC when (S2 S1 S0 ) = (001). The operators ∧, ∨ were the Boolean AND, and Boolean OR, respectively. The I1 , shown in Fig. 3, was determined by the parallel resistance of M2 , M3 and M4 .
(2)
For example, Iout = 3Iunit for (B1 B0 )2 = (11)2 , and Iout = Iunit for (B1 B0 )2 = (01)2 . In Fig. 3, the PMOS transistors M0 and M1 were used as a basic current mirror. The width of the M2 ∼ M4 transistors were adjusted to obtain a suitable current on M1 . Different currents were obtained by changing the width of the PMOS M0 . Fig. 4 depicts the single-side 8-bit DAC. The DAC required four different current sources, namely Iunit , 4Iunit , 16Iunit , and 64Iunit . The conventional N-bit thermometer-coded type DAC required at least 2N−1 current sources. The conventional N-bit binary weighted DAC required N current sources. It is the reason of smaller area for the proposed DAC. The aspect ratio of M0 –M1 were adjusted to obtain the unit current Iunit . 4Iunit , 16Iunit , and 64Iunit were also determined by adjusting the aspect ratio of M5 /M6 , M10 /M11 and M15 /M16 . Last, a differential 8-bit current mirror DAC were constructed using two 8-bit single-ended current mirror DACs. Differential mode DAC can increase the linear performance of the proposed construction. Compared to the binary weighted DAC, the construction partially used thermometric code, and slightly decreased the glitch. 3. Results
B0 B1
S2 S1
S 2 = B0 B1 S 1 = B1 S 0 = B 0 +B1
S0 Fig. 2. 2-Bit BT decoder.
The differential mode DAC was implemented using TSMC 0.35 m, 2P4M CMOS process. The voltage of the circuit was 3.3 V. The chip was packaged with 14 pins. The common package limits and degrades the maximum frequency of the chip, which was feed by Agilent 16903A pattern generator. Therefore, the sampling rate was set at 100 MHz. The output was measured using Agilent 54855A oscilloscope. The average INL and DNL were about +0.27/−0.17 LSB and +0.32/−0.1 LSB, as shown in Figs. 5 and 6, respectively.
S.-C. Yi / Int. J. Electron. Commun. (AEÜ) 66 (2012) 433–437
435
0.3 0.2
M0 Vout
B0
Rload
B1 M2
M3 M4
DNL(LSB)
M1
0.1 0 -0.1 -0.2
Iout
-0.3
0
20
40
60
80
100 120 140 160 180 200 220 240
Input code
M5
M6
Fig. 6. DNL of 8-bit DAC.
B2 B3 M7
M8 M9
M11
M10
B4 B5 M12
M13 M14 Fig. 7. SFDR of 8-bit DAC.
M16
M15
B6 B7 M17
M18 M19
Fig. 4. An 8 bit single-ended current mirror DAC.
INL(LSB)
Spurious-Free Dynamic Range (SFDR) is the strength ratio of the fundamental signal to the strongest spurious signal in the output. It is also defined as a measure used to specify analog-to-digital and digital-to-analog converters (ADCs and DACs, respectively) and radio receivers. SFDR is defined as the ratio of the RMS value of the carrier frequency (maximum signal component) at the input of the 0.3 0.25 0.2 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2
ADC or DAC to the RMS value of the next largest noise or harmonic distortion component at its output [14]. Under the sampling rate of 100 MHz, the 3.79 MHz digitized sine waveform was feed into the chip. The SFDR was about 50.9 dB, as shown in Fig. 7. The full-scale output was 254 mV. The power consumption was 27.6 mW at the sample rate of 100 MHz. Table 1 summarized the specifications averaged of all the DAC chips. Table 2 compared recently published noticeable DACs with the converter presented in this work. The power dissipation is the smallest one among them [10–13]. The power efficiency is 0.275 mW/MHz. It is also the smallest among [10,13] for 0.35 m technology. The core size of the chip is also the smallest one. The reason is that the DAC requires only one current mirror for 2-bit conversion. It is suitable for low power and small-area DAC applications, especially for portable device. The die photo of the DAC chip is shown in Fig. 8.
Table 1 Performance summary.
0
20
40
60
80
100 120 140 160 180 200 220 240
Input code Fig. 5. INL of 8-bit DAC.
Resolution
8 bits
Supply voltage Sample rate INL DNL SFDR Power dissipation Chip size Core size Full scale of output Transistor count Technology
3.3 V 100 MHz +0.27/−0.17 LSB +0.32/−0.1 LSB 50.9 dB (3.79 MHz@100 MS/s) 27.6 mW (3.79 MHz@100 MS/s) 0.72 mm2 (0.907 mm × 0.796 mm) 0.024 mm2 (0.1802 mm × 0.1327 mm) 254 mV (RL = 50 ) 152 0.35 m
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Table 2 Comparison with other DACs.
Resolution (bit) Supply voltage Sample rate (Hz) INL (LSB) DNL (LSB) SFDR (dB) (Hz@Hz) Power dissipation (mW) Core size (mm2 ) Technology (m) Full scale of output (mV)
This work
[10]
[11]
[12]
[13]
8 3.3 V 100 M 0.26 0.31 53.4 (3.79 M@100 M) 27.5 0.024 0.35 254
8 3.3 V 100 M 0.32 0.12 62.13 (2.49 M@100 M) 54.5 0.449 0.35 –
8 1.8 V 500 M 0.331 0.137 35.42 (10 M@500 M) – – 0.18 –
8 1V 12 G 0.31 0.28 51 (750 M@12 G) 190 0.235 0.09 –
8 3.3 V 100 M <0.15 <0.15 54 (3.79 M@100 M) 45 0.449 0.35 –
4. Discussion The 8-bit proposed DAC has some interesting characteristics. It requires four current sources of different weight, i.e., 20 Iunit , 22 Iunit , 24 Iunit , and 26 Iunit . However, conventional 8-bit binary-weighted DAC requires 8 current sources of different weight, i.e., 20 Iunit , 21 Iunit , . . ., 26 Iunit , and 27 Iunit . Therefore, the proposed approach meets less mismatch problem of current sources compared with binary weighted DAC. The conventional 8-bit thermometer-coded type DAC required at least 27 current sources. The proposed 8-bit DAC required only 4 current sources. It is the reason of smaller area for the proposed DAC. The approach uses thermometric code in 2-bit DAC. It slightly decreases the glitch during digital code switching compared with binary weighted DAC. The proposed DAC was sensitive to the resistances of M2 , M3 , and M4 in Fig. 3. The sensitivity of the resistance would degrade the performance of linearity. It is possible the only disadvantage. The layout of each set of current mirror was placed common centroid to avoid mismatch effect. The placement of transistors M5 and M6 is depicted in Fig. 9. Transistor M5 was split into four equal transistors. Transistor M6 was split into 64 equal transistors, circles in Fig. 9. The “D” inside the circle was represented for dummy. The ratio of M6 over M5 was 4/64. The size of switches controlled by S0 , S1 , and S2 were all same for each set of current mirror source. The widths were 0.85 m, 1.06 m and 1.08 m of M2 , M3 , and M4 , respectively. Although resistors or transistors were allowable to implement the switches, the use of the transistors M2 –M4 could reduce the area of switches
Fig. 9. Placement diagram of the current mirror M5 and M6 .
in replacement of resistors. Transistors M3 and M4 were split into two fingers respectively. Transistors M2 –M4 were then interdigitated in the order of M4 –M3 –M2 –M4 –M3 . The mismatch of switches M2 –M4 can be slightly reduced. In this differential mode implementation, the INL and DNL were about +0.27/−0.17 LSB and +0.32/−0.1 LSB. The respective value of INL and DNL was roughly similar as [10,11,12]. If more INL and DNL improvement required, the possible approach is the laser trimming technique. The SFDR was similar as that of [12,13]. Differential mode DAC can also improve the linearity of the single-ended DAC. However, it doubles the area of the proposed DAC. The core size of the proposed differential mode DAC was 0.024 mm2 . As the construction is simple, the core size is only 10% of [12] and 5% of [10,13]. The results demonstrated the smallest size advantage among Refs. [10–13]. From Eq. (1), it is obvious that output current I0 equals I1∗ ((W/L)M0 /(W/L)M1 ). The factor of M0 over M1 is 1/64. The output current could shrink to 1/64. The mismatch of current mirror also could shrink to 1/64. 5. Conclusion
Fig. 8. Die photo of the DAC chip.
An 8-bit differential mode current steering DAC is proposed in this paper. The DAC was implemented using TSMC 0.35 m, 2P4M CMOS process technology. Four different unit current mirrors were used to form the 8-bit DAC. The full-scale output was 254 mV. The DAC consumed 27.5 mW for 3.79 MHz analog signal at 100 MS/s. The INL and DNL were +0.26/−0.17 LSB and
S.-C. Yi / Int. J. Electron. Commun. (AEÜ) 66 (2012) 433–437
+0.31/−0.09 LSB, respectively. Therefore, the circuit was found to consume less power and core area. It is suitable for low power and small-area DAC applications, especially for portable device. Acknowledgments The author is very grateful for the comments of Reviewers and Editor. The author also thanks the CIC (Chip Implementation Center) for the chip implementation. References [1] Tiilikainen MP. A 14-bit 1.8-V 20-mW 1-mm2 CMOS DAC. IEEE Journal of SolidState Circuits 2001;36(July (7)):1144–7. [2] Bugeja AR, Song B-S. A self trimming 14-b 100-MS/s CMOS DAC. IEEE Journal of Solid-State Circuits 2000;35(December (12)):1841–52. [3] Deveugele J, Steyaert MSJ. A 10-bit 250-MS/s binary-weighted current steering DAC. IEEE Journal of Solid-State Circuits 2006;41(February (2)):320–9. [4] Van der Plas GAM, Vandenbussche J, Sansen W, Steyaert MSJ, Gielen GGE. A 14bit intrinsic accuracy Q2 random walk CMOS DAC. IEEE Journal of Solid-State Circuits 2000;34(December (12)):1708–18. [5] Van den Bosch A, Borremans MAF, Steyaert MSJ, Sansen W. A 10-bit 1 GSample/s Nyquist current-steering CMOS D/A converter. IEEE Journal of Solid-State Circuits 2001;36(March (3)):315–24. [6] Chen W, Bauwelinck J, Ossieur P, Qiu X-Z, Vandewege J. A current-steering DAC architecture with novel switching scheme for GPON burst-mode laser drivers. IEICE Transactions on Electronics 2007;E90-C(4):877–84.
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[7] Chena C-Y. Current-mode digital-to-analog converter designed in hybrid architecture. International Journal of Electronics 2008;95:361–9. [8] Lin C-H, Bult K. A 10-b 500-MSample/s CMOS DAC in 0.6 mm2 . IEEE Journal of Solid-State Circuits 1998;33(December (12)):1948–58. [9] van de Plassche R. CMOS integrated analog-to-digital and digital-to-analog converters. 2nd edition Kluwer Academic Publishers; 2003. [10] Zhou Y, Yuan J. An 8-Bit 100-MHz CMOS linear interpolation DAC. IEEE Journal of Solid-State Circuits 2003;38(October (10)):1758–61. [11] Sarkar S, Prasad RS, Dey SK, Belde V, Banerjee S. An 8-bit 1.8 V 500 MS/s CMOS DAC with a novel four-stage current steering architecture. IEEE International Symposium on Circuits and Systems 2008, May:149–52. [12] Savoj J, Abbasfar A, Amirkhany A, Jeeradit M, Garlepp BW. A 12-GS/s phasecalibrated CMOS digital-to-analog converter for backplane communications. IEEE Journal of Solid-State Circuits 2008;43(May (5)):1107–26. [13] Zhou Y, Yuan J. An 8-bit 100-MHz low glitch interpolation DAC. IEEE International Symposium on Circuits and Systems 2001, May:116–9. [14] http://www.analog.com/static/imported-files/tutorials/MT-003.pdf. Shu-Chung Yi received the B.S., M.S. and Ph.D. degrees in Electrical Engineering from National Cheng Kung University, National Taiwan University, National Taiwan University, in 1986, 1990 and 1998, respectively. He is currently an associate professor in the Graduate Institute of Integrated Circuit Design, National Changhwa University of Education. His research interests include algorithms, VLSI architectures, and circuit level techniques.
Contents lists available at SciVerse ScienceDirect
International Journal of Electronics and Communications (AEÜ) journal homepage: www.elsevier.de/aeue
An 8-bit current-steering digital to analog converter Shu-Chung Yi ∗ National Changhua University of Education, Graduate Institute of Integrated Circuit Design, No. 1, Jin-De Road, Changhua 500, 50007, Taiwan, ROC
a r t i c l e
i n f o
Article history: Received 7 December 2010 Accepted 4 October 2011 Keywords: CMOS digital integrated circuits Current mirrors DAC Digital-analog conversion
a b s t r a c t In this paper, an 8-bit current steering digital-to-analog converter is proposed. The digital-to-analog converter contained four sets of current mirrors with different weight. The digital-to-analog converter was implemented using TSMC 0.35 m, 2P4M CMOS process. The average INL and DNL are 0.27 LSB and 0.32 LSB, respectively. At the sample rate of 100 MHz and supply voltage of 3.3 V, the DAC consumed about 27.6 mW. The SFDR was 50.9 dB. The core size is 0.024 mm2 . The digital-to-analog converter of this construction consumed less power and chip area. It is suitable for portable device application. © 2011 Elsevier GmbH. All rights reserved.
1. Introduction In recent years, the current steering converter is the dominant construction for very high speed Digital to Analog Converters (DAC). The current steering DAC has the advantages of being quite small for resolution below 10 bits, being very fast, and being more cost effective. However, the major drawback is its sensitivity to device mismatch, glitches, and current source output impedance for higher number of bits. For example, its integral non-linearity (INL) and differential non-linearity (DNL) are vulnerable to the accuracy of current sources. Generally, a self-calibrated circuit can be designed to solve these problems [1,2], but the circuit will consume more power and require a large chip area. Current steering DAC has three main designs: Binary Weighted Current Steering DAC [3], Thermometer Coded Current Steering DAC [4] and Segmented Current Steering DAC [5,6]. In a binary implementation, one bit in the digital input word directly turns a relative current source on or off, and the output sums up all the current sources that are turned on. The current value is proportional to the input binary word [7]. The binary structure is simple and requires less area and less power, as no decoding logic is required. However, its major drawback is its down-graded performance mainly due to glitches at middle code transitions and stringent matching requirement of the current sources [8]. For example, when the digital input code changes from 0111. . .1 to 1000. . .0, one MSB turn on and all the other LSB’s turn off. Glitch will be induced during the switching of input code. It is a limitation of high-speed operation of DAC. Although the die size of a binary weighted converter might be relatively small, its specifications for
∗ Tel.: +886 422959907. E-mail addresses: [email protected], [email protected] 1434-8411/$ – see front matter © 2011 Elsevier GmbH. All rights reserved. doi:10.1016/j.aeue.2011.10.003
dynamic performance are stringent. Therefore, binary weighting is not suitable for high-speed digital-to-analog conversion [9]. The thermometer-coded DAC, also called unary DAC, utilizes a number of equally weighted elements. Thermometer-coded DAC is invariably monotonic. When the digital input increases by 1 LSB, one current source is switched from negative to positive, and the analog output always increases with input signal. In comparison, the binary-weighted type manifests poorer dynamic performance than the thermometer-coded type. For a large number of bits, the digital circuits converting the binary code into thermometer code and the number of interconnecting wires become large. This implies a more complex circuit layout. Therefore, the disadvantages of the thermometer-coded DAC are its complexity, consumption of a large area, and the larger power requirement of the binary-tothermometer decoders. The segmented current steering is a very popular approach for designing digital-to-analog converters because it combines the advantages of binary-weighted and thermometer-coded designs. The segmented DAC is commonly to use a thermometer-coded approach for the top few MSB’s while using a binary-weighted approach for the lower LSB’s. In this way, the glitch is significantly reduced and accuracy is high for the MSBs. Subsequently, the circuit area is minimized with the segmented DAC (Fig. 1). 2. Construction The proposed differential mode DAC was formed by two single-ended DAC circuits. The single-ended DAC contained binaryto-thermometer (BT) decoders and current mirror circuits, as shown in Fig. 4. The current mirror circuit contained four current mirrors of different weighting. Each current mirror is controlled by a 2-bit binary to thermometer code decoder, as shown in Fig. 2. The proposed DAC has the advantage of low chip area. It is owing to
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S.-C. Yi / Int. J. Electron. Commun. (AEÜ) 66 (2012) 433–437
M1
M0 Vout
I1 Fig. 1. Single-ended DAC construction.
low transistor count of this construction. The MOS transistor has larger capacitances in its gate oxide, source and drain. Moreover, less number of transistors has the possibility of less interconnection than those of more transistors. Dynamic power consumption of MOS circuits is proportional to the total capacitances of load and internal node. Low transistor count DAC has the chance for low total capacitances. Therefore, the proposed DAC has more possibility to consume low power. 2.1. Binary to thermometer (BT) decoder Fig. 2 shows the constitution circuit of one 2-bit binary to thermometer decoder. It consisted of one AND gate and one OR gate. S0 , S1 , S2 were the control signals for current mirrors. The 8-bit DAC decoder of differential mode required only eight AND gates and eight OR gates.
(W/L)M0
M2
S2 M3
R1
I0
M4
Fig. 3. Current mirror circuits of 2-bit DAC.
The current mirrors of the 8-bit single-sided DAC needed 12 NMOS transistors as switches to turn the current on or off. Iout collected all the current from current mirrors. The output Iout can be described as follows: Iout = [(B1 ∧ B0 ) + (B1 ) + (B1 ∧ B0 )](Iunit ) + [(B3 ∧ B2 ) + (B3 ) + (B3 ∧ B2 )(4Iunit )
+ [(B7 ∧ B6 ) + (B7 ) + (B7 ∧ B6 )(64Iunit ).
Fig. 4 shows a single-ended 8-bit DAC. It contained four BT decoders and four current mirrors. Each current mirror generated 2-bit DAC. Fig. 3 depicts the circuit of one 2-bit DAC. The three NMOS transistors, M2 ∼ M4 , were switches that turned on the current path. The three signals, S0 ∼ S2 , were generated by the previous BT decoder stage. I0 were the drain current of M0 mirrored from I1 , the drain current of M1 . Transistors M2 , M3 and M4 acted as switches. When they were turned on, effective resistance appeared between the drain of M1 and ground. For example, when the switch was turned on via S0 , the effective resistance of M2 appeared between the drain of M1 and the ground. There were four thermometric configurations of (S2 S1 S0 ), namely (111), (011) (001) and (000). For example, if (S2 S1 S0 ) = (011), then I1 was the total current drawn by M2 and M3 . The relationship between I0 and I1 was derived as follows:
(W/L)M1
S1
+ [(B5 ∧ B4 ) + (B5 ) + (B5 ∧ B4 )(16Iunit )
2.2. Current mirror construction
I0 = I1∗
S0
= [(S1 ∧ S0 ) + (S1 ) + (S1 ∧ S0 )](Iunit ),
(1)
where Iunit was the unit output current of the 2-bit DAC when (S2 S1 S0 ) = (001). The operators ∧, ∨ were the Boolean AND, and Boolean OR, respectively. The I1 , shown in Fig. 3, was determined by the parallel resistance of M2 , M3 and M4 .
(2)
For example, Iout = 3Iunit for (B1 B0 )2 = (11)2 , and Iout = Iunit for (B1 B0 )2 = (01)2 . In Fig. 3, the PMOS transistors M0 and M1 were used as a basic current mirror. The width of the M2 ∼ M4 transistors were adjusted to obtain a suitable current on M1 . Different currents were obtained by changing the width of the PMOS M0 . Fig. 4 depicts the single-side 8-bit DAC. The DAC required four different current sources, namely Iunit , 4Iunit , 16Iunit , and 64Iunit . The conventional N-bit thermometer-coded type DAC required at least 2N−1 current sources. The conventional N-bit binary weighted DAC required N current sources. It is the reason of smaller area for the proposed DAC. The aspect ratio of M0 –M1 were adjusted to obtain the unit current Iunit . 4Iunit , 16Iunit , and 64Iunit were also determined by adjusting the aspect ratio of M5 /M6 , M10 /M11 and M15 /M16 . Last, a differential 8-bit current mirror DAC were constructed using two 8-bit single-ended current mirror DACs. Differential mode DAC can increase the linear performance of the proposed construction. Compared to the binary weighted DAC, the construction partially used thermometric code, and slightly decreased the glitch. 3. Results
B0 B1
S2 S1
S 2 = B0 B1 S 1 = B1 S 0 = B 0 +B1
S0 Fig. 2. 2-Bit BT decoder.
The differential mode DAC was implemented using TSMC 0.35 m, 2P4M CMOS process. The voltage of the circuit was 3.3 V. The chip was packaged with 14 pins. The common package limits and degrades the maximum frequency of the chip, which was feed by Agilent 16903A pattern generator. Therefore, the sampling rate was set at 100 MHz. The output was measured using Agilent 54855A oscilloscope. The average INL and DNL were about +0.27/−0.17 LSB and +0.32/−0.1 LSB, as shown in Figs. 5 and 6, respectively.
S.-C. Yi / Int. J. Electron. Commun. (AEÜ) 66 (2012) 433–437
435
0.3 0.2
M0 Vout
B0
Rload
B1 M2
M3 M4
DNL(LSB)
M1
0.1 0 -0.1 -0.2
Iout
-0.3
0
20
40
60
80
100 120 140 160 180 200 220 240
Input code
M5
M6
Fig. 6. DNL of 8-bit DAC.
B2 B3 M7
M8 M9
M11
M10
B4 B5 M12
M13 M14 Fig. 7. SFDR of 8-bit DAC.
M16
M15
B6 B7 M17
M18 M19
Fig. 4. An 8 bit single-ended current mirror DAC.
INL(LSB)
Spurious-Free Dynamic Range (SFDR) is the strength ratio of the fundamental signal to the strongest spurious signal in the output. It is also defined as a measure used to specify analog-to-digital and digital-to-analog converters (ADCs and DACs, respectively) and radio receivers. SFDR is defined as the ratio of the RMS value of the carrier frequency (maximum signal component) at the input of the 0.3 0.25 0.2 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2
ADC or DAC to the RMS value of the next largest noise or harmonic distortion component at its output [14]. Under the sampling rate of 100 MHz, the 3.79 MHz digitized sine waveform was feed into the chip. The SFDR was about 50.9 dB, as shown in Fig. 7. The full-scale output was 254 mV. The power consumption was 27.6 mW at the sample rate of 100 MHz. Table 1 summarized the specifications averaged of all the DAC chips. Table 2 compared recently published noticeable DACs with the converter presented in this work. The power dissipation is the smallest one among them [10–13]. The power efficiency is 0.275 mW/MHz. It is also the smallest among [10,13] for 0.35 m technology. The core size of the chip is also the smallest one. The reason is that the DAC requires only one current mirror for 2-bit conversion. It is suitable for low power and small-area DAC applications, especially for portable device. The die photo of the DAC chip is shown in Fig. 8.
Table 1 Performance summary.
0
20
40
60
80
100 120 140 160 180 200 220 240
Input code Fig. 5. INL of 8-bit DAC.
Resolution
8 bits
Supply voltage Sample rate INL DNL SFDR Power dissipation Chip size Core size Full scale of output Transistor count Technology
3.3 V 100 MHz +0.27/−0.17 LSB +0.32/−0.1 LSB 50.9 dB (3.79 MHz@100 MS/s) 27.6 mW (3.79 MHz@100 MS/s) 0.72 mm2 (0.907 mm × 0.796 mm) 0.024 mm2 (0.1802 mm × 0.1327 mm) 254 mV (RL = 50 ) 152 0.35 m
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Table 2 Comparison with other DACs.
Resolution (bit) Supply voltage Sample rate (Hz) INL (LSB) DNL (LSB) SFDR (dB) (Hz@Hz) Power dissipation (mW) Core size (mm2 ) Technology (m) Full scale of output (mV)
This work
[10]
[11]
[12]
[13]
8 3.3 V 100 M 0.26 0.31 53.4 (3.79 M@100 M) 27.5 0.024 0.35 254
8 3.3 V 100 M 0.32 0.12 62.13 (2.49 M@100 M) 54.5 0.449 0.35 –
8 1.8 V 500 M 0.331 0.137 35.42 (10 M@500 M) – – 0.18 –
8 1V 12 G 0.31 0.28 51 (750 M@12 G) 190 0.235 0.09 –
8 3.3 V 100 M <0.15 <0.15 54 (3.79 M@100 M) 45 0.449 0.35 –
4. Discussion The 8-bit proposed DAC has some interesting characteristics. It requires four current sources of different weight, i.e., 20 Iunit , 22 Iunit , 24 Iunit , and 26 Iunit . However, conventional 8-bit binary-weighted DAC requires 8 current sources of different weight, i.e., 20 Iunit , 21 Iunit , . . ., 26 Iunit , and 27 Iunit . Therefore, the proposed approach meets less mismatch problem of current sources compared with binary weighted DAC. The conventional 8-bit thermometer-coded type DAC required at least 27 current sources. The proposed 8-bit DAC required only 4 current sources. It is the reason of smaller area for the proposed DAC. The approach uses thermometric code in 2-bit DAC. It slightly decreases the glitch during digital code switching compared with binary weighted DAC. The proposed DAC was sensitive to the resistances of M2 , M3 , and M4 in Fig. 3. The sensitivity of the resistance would degrade the performance of linearity. It is possible the only disadvantage. The layout of each set of current mirror was placed common centroid to avoid mismatch effect. The placement of transistors M5 and M6 is depicted in Fig. 9. Transistor M5 was split into four equal transistors. Transistor M6 was split into 64 equal transistors, circles in Fig. 9. The “D” inside the circle was represented for dummy. The ratio of M6 over M5 was 4/64. The size of switches controlled by S0 , S1 , and S2 were all same for each set of current mirror source. The widths were 0.85 m, 1.06 m and 1.08 m of M2 , M3 , and M4 , respectively. Although resistors or transistors were allowable to implement the switches, the use of the transistors M2 –M4 could reduce the area of switches
Fig. 9. Placement diagram of the current mirror M5 and M6 .
in replacement of resistors. Transistors M3 and M4 were split into two fingers respectively. Transistors M2 –M4 were then interdigitated in the order of M4 –M3 –M2 –M4 –M3 . The mismatch of switches M2 –M4 can be slightly reduced. In this differential mode implementation, the INL and DNL were about +0.27/−0.17 LSB and +0.32/−0.1 LSB. The respective value of INL and DNL was roughly similar as [10,11,12]. If more INL and DNL improvement required, the possible approach is the laser trimming technique. The SFDR was similar as that of [12,13]. Differential mode DAC can also improve the linearity of the single-ended DAC. However, it doubles the area of the proposed DAC. The core size of the proposed differential mode DAC was 0.024 mm2 . As the construction is simple, the core size is only 10% of [12] and 5% of [10,13]. The results demonstrated the smallest size advantage among Refs. [10–13]. From Eq. (1), it is obvious that output current I0 equals I1∗ ((W/L)M0 /(W/L)M1 ). The factor of M0 over M1 is 1/64. The output current could shrink to 1/64. The mismatch of current mirror also could shrink to 1/64. 5. Conclusion
Fig. 8. Die photo of the DAC chip.
An 8-bit differential mode current steering DAC is proposed in this paper. The DAC was implemented using TSMC 0.35 m, 2P4M CMOS process technology. Four different unit current mirrors were used to form the 8-bit DAC. The full-scale output was 254 mV. The DAC consumed 27.5 mW for 3.79 MHz analog signal at 100 MS/s. The INL and DNL were +0.26/−0.17 LSB and
S.-C. Yi / Int. J. Electron. Commun. (AEÜ) 66 (2012) 433–437
+0.31/−0.09 LSB, respectively. Therefore, the circuit was found to consume less power and core area. It is suitable for low power and small-area DAC applications, especially for portable device. Acknowledgments The author is very grateful for the comments of Reviewers and Editor. The author also thanks the CIC (Chip Implementation Center) for the chip implementation. References [1] Tiilikainen MP. A 14-bit 1.8-V 20-mW 1-mm2 CMOS DAC. IEEE Journal of SolidState Circuits 2001;36(July (7)):1144–7. [2] Bugeja AR, Song B-S. A self trimming 14-b 100-MS/s CMOS DAC. IEEE Journal of Solid-State Circuits 2000;35(December (12)):1841–52. [3] Deveugele J, Steyaert MSJ. A 10-bit 250-MS/s binary-weighted current steering DAC. IEEE Journal of Solid-State Circuits 2006;41(February (2)):320–9. [4] Van der Plas GAM, Vandenbussche J, Sansen W, Steyaert MSJ, Gielen GGE. A 14bit intrinsic accuracy Q2 random walk CMOS DAC. IEEE Journal of Solid-State Circuits 2000;34(December (12)):1708–18. [5] Van den Bosch A, Borremans MAF, Steyaert MSJ, Sansen W. A 10-bit 1 GSample/s Nyquist current-steering CMOS D/A converter. IEEE Journal of Solid-State Circuits 2001;36(March (3)):315–24. [6] Chen W, Bauwelinck J, Ossieur P, Qiu X-Z, Vandewege J. A current-steering DAC architecture with novel switching scheme for GPON burst-mode laser drivers. IEICE Transactions on Electronics 2007;E90-C(4):877–84.
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[7] Chena C-Y. Current-mode digital-to-analog converter designed in hybrid architecture. International Journal of Electronics 2008;95:361–9. [8] Lin C-H, Bult K. A 10-b 500-MSample/s CMOS DAC in 0.6 mm2 . IEEE Journal of Solid-State Circuits 1998;33(December (12)):1948–58. [9] van de Plassche R. CMOS integrated analog-to-digital and digital-to-analog converters. 2nd edition Kluwer Academic Publishers; 2003. [10] Zhou Y, Yuan J. An 8-Bit 100-MHz CMOS linear interpolation DAC. IEEE Journal of Solid-State Circuits 2003;38(October (10)):1758–61. [11] Sarkar S, Prasad RS, Dey SK, Belde V, Banerjee S. An 8-bit 1.8 V 500 MS/s CMOS DAC with a novel four-stage current steering architecture. IEEE International Symposium on Circuits and Systems 2008, May:149–52. [12] Savoj J, Abbasfar A, Amirkhany A, Jeeradit M, Garlepp BW. A 12-GS/s phasecalibrated CMOS digital-to-analog converter for backplane communications. IEEE Journal of Solid-State Circuits 2008;43(May (5)):1107–26. [13] Zhou Y, Yuan J. An 8-bit 100-MHz low glitch interpolation DAC. IEEE International Symposium on Circuits and Systems 2001, May:116–9. [14] http://www.analog.com/static/imported-files/tutorials/MT-003.pdf. Shu-Chung Yi received the B.S., M.S. and Ph.D. degrees in Electrical Engineering from National Cheng Kung University, National Taiwan University, National Taiwan University, in 1986, 1990 and 1998, respectively. He is currently an associate professor in the Graduate Institute of Integrated Circuit Design, National Changhwa University of Education. His research interests include algorithms, VLSI architectures, and circuit level techniques.