Experimental implementation of the eight bit analog-to-digital converter

ICEC 14 Proceedings

EXPERIMENTAL IMPLEMENTATION OF THE EIGHT BIT ANALOG-TO-DIGITAL CONVERTER Vsevolod Kaplunenko

Marat Khabipov

Valery Koshelets Sergey Kovtonyuk Dmitry Khohlov

Institute of Radio Engineering and Electronics, Russia Academy of Sciences, Mokhovaya street 11, Moscow, 103907, Russia. Two bit Single Flux Quantum (SFQ) Analog to Digital Converter (ADC) has been recently realized and successfully tested. The new design and the improved fabrication technique of superconducting microcircuits has allowed us to expand the number of bits up to eight. This converter consists of a comparator and reversible ripple counter. The comparator is loaded with two SFQ transmission lines which independence from the input signal. Non-destructive read-out of the counter contents is carried out by SFQ/DC converters which is connected to the each counter bit. The integrated circuit is fabricated using 4 ~tNb-AIOx-Nb trilayer technology with critical current density about 1000 Alcm2. Careful investigation of the ADC input circuits have been performed.

INTRODUCTION Counter-type superconducting A/D converters [1,2,3] are very promising for high-accuracy measurements of medium-bandwidth signals. However, at least two evident problems reversible counting and error-free counter contents reading without interrupting the input signal tracking - should be solved before the practical applications. Several approaches [2,3] have been proposed to solve these problems. One of the possibilities to overcome'these drawbacks have been developed recently on the base of ultrafast Rapid Single Flux Quantum (RSFQ) logic family [4,5]. The design of a reversible counter [6] was based on a usual unidirectional RSFQ binary ripple counter, but some new elements were added to it. In the case of adding SFQ pulses it is applied to less significant bit (LSB) section of the counter, while in case of diminishing SFQ pulses they are applied to all stages of the counter, providing the complementary binary code representation of (-1). The second problem was solved by using the asynchronous read-out scheme in our converter; its main idea is the application of SFQ/DC voltage converters [4,5] to all the stages of the counter. As a result, any change of the counter state is almost immediately converted to a corresponding change of the DC-voltage digital output signals. In the report we present the details of the A/D converter construction and layout together with experimental results for the comparator with a input transformer and T-flipflop with SFQ/DC converter which is employed as one bit counter.

CIRCUIT AND LAYOUT DESIGN Figure la shows the block-structure of the A/D converter [6]. Comparator produces two SFQ pulse trains which go to two separate transmission lines. W h e n the input signal is increased the SFQ pulses go through the adding transmission line to LSB (BIT0 in Fig.l). In the opposite case of input signal decreasing the SFQ pulses go through the diminishing transmission line which is connected to all the stages. These diminishing pulses decrease by unit the contents of the stages. SFQ/DC converters perform asynchronous nondestructive reading-out of state of each bits. Figure lb shows the equivalent circuit of two first bits of the A/D converter.

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ICEC 14 Proceedings

input

The comparator is the usual two-junction interferometer (Jl, L1, J2 signal current I. induces a proportional magnetic flux ~=MI. In

in Fig. lb). The applied to the

in

interferometer. To improve the sensitivity of the ADC, a 10 turn input ransforrneris used. if the flux is constant, no SFQ pulses appear at the outputs. If the flux is increased in time, and crosses a level ~on+k~0 (with an integer k), the current through junction Jl reaches its critical value and the SFQ pulse is generated by this junction. Thus the SFQ pulse rate at the upper output of the comparator (adding line) equals ] ~ [ / ~ 0 at ~ > 0. At ~ < 0, this junction is silent, but junction 32 develops a similar train of the pulses at the reverse output of the converter. The split-confluence buffer is a combination of split buffer and confluence element [4]. The splitting function is performed by junction J4, inductances L2, L3; confluence function is performed by junctions J3, J4, J5, J6, J7. T flip-flop with SFQ/DC converter is an optimized version of the element described earlier (see, for example [4,5]). The inductance L4 is introduced in the circuit for improving parameter margins. Additional one-turn transformer coupled to the interferometer is used for the setting of the initial state of the T-flip-flop and for the fine adjustment of the magnetic field in the interferometer. On the basis of these elements the eight-bit A/D converter have been designed and fabricated. This integrated circuit contained 169 Josephson junctions and 300 resistors. We have fabricated our test circuits using the all-refractory 4~ design rule technology [6,7]. This structure contains four superconducting layers: the ground plane, the base electrode, counter pre-electrode and counter electrode. The layout differs in several aspects from the traditional Josephson Nb-AIO-Nb technology. Firstly, the layout included X

holes in the ground plane intended for pinning of the parasitic Abricosov vortices and filtering picosecond SFQ pulses in interconnecting lines. Secondly, to increase reliability and to reduce the relief steps, we have employed two insulator layers which are produced with different pattern. Besides that we try to avoid the crossing of a two conducting bottom layers under counter electrode.

EXPERIMENTAL RESULTS Test circuit for the investigation of the ADC input part have been designed and fabricated. This circuit is very similar to the input bit of the ADC except split-confluence buffer. The sawtooth signal is applied to the input of the 10-turn square input coil and is converted to the magnetic flux in the comparator interferometer. The comparator produces the SFQ pulses (see Fig. 2). To produce nest SFQ pulse it is necessary to increase the input current on 75 ~A. The calculated frequency range of the input transformer is about 1 GHz. We have checked the linearity of the input circuit by application of the sawtooth signal together with large offset current (see Fig 3). The correct operation of the input part of the ADC has been obtained for the offset currents from -14 mA up to +11 mA, which corresponds to about 330 SFQ pulses. It p r o v e d the appropriateness of the designed input circuit for 8-bit ADC (256 levels). The investigation of the 8-bit ADC is in progress. The preliminary measurements show that the input elements operate properly and provide the conversion of the input signal to SFQ pulse with the designed value 75 ~A per SFQ pulse. SFQ/DC converters of all 8 bits have been tested independently. The spread of the critical currents for all outputs was lower than 5~o, and margins for all main parameters was about 40~o. CONCLUSION As a result, the analog-to-digital counter-type A/D converter which is very promising for high-accuracy measurement of medium-bandwidth signal have been designed, fabricated and successfully tested. The input circuits for the high frequency ADC have been optimized and tested. The investigation of the 8-bit A/D converters is underway but preliminary results prove the possibility to create a new type of the SFQ devices with outstanding parameters.

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ACKNOWLEDGMENTS The numerous fruitful discussions with V.K.Semenov, O.A.Mukhanov .and S.V.Rylov are grateful acknowledged. This work is supported by Russia State Scientific Program "HTc Superconductivity" under Contract No 90463. REFERENCES HurreI,J.P. Pridmore-Brown, D. C. and Silver, A.H., Analog-to-digital conversion unlatched SQUID's 1EEE Trans. Electron. Dev. (1980) ED-27 No.10 1887-1896 Lee, G.S., A variable hysteresis aperturing method for supercundueting converters I EEE Trans. on Magn. (1989) MAG-25 No.2 830-833 3

Kuo, F. ,

with

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Superconducting A/D Converters based on Josephson binary counter

A/D

I EEE Trans

on Magn. (1991) No 2 2883-2886 Likharev, K.K. Semenov, V.K., RSFQ Logic/Memory Family: A Josephson-Junction Technology for Sub-Terahertz-Clock-Frequency Digital Systems IEEE Trans. on Appl. Superconductivity (1991) Vol.l No.1 3-28

}(oshelets, V.P.,

Single flux quantum

digital devices Supercond. Sci.

Technol.

(1991) 4

555-560

Filippenko, L.V. Kaplunenko, K.K. Khabipov, M.|. Koshelets, V.P. Likharev, K.K. Mukhanov, O.A. Rylov, S.V. Semenov, V.K. and Vystavkin A.N., I EEE Trans. on Magn.

(1990)

MAG-27 No.2 2464-2467 Koshelets, V.P. Kovtonyuk, S.A. Serpuehenko, I.L. Filippenko, L.V. and Shchukin,A.V. High Quality Nb-AIOx-Nb Tunnel Junctions for Microwave and SFQ Logic Devices I EEE Trans. on Magn. (1990) Mag-27 No.2 3141-3144

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Cryogenics 1992 Vol 32 ICEC Supplement

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