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Analog characteristics of drain engineered submicron MOSFETs for mixed-signal applications
ElectronicsVol. 38, No. I I, pp. 1857-1859, 1995
Solid-Slate
Pergamon
Copyright 0 I995 Elsevier Science Ltd Printed in Great Britain. All rights reserved
003%1101(95)00029-1
0038-l I01195 $9.50 + 0.00
ANALOG CHARACTERISTICS OF DRAIN ENGINEERED SUBMICRON MOSFETs FOR MIXED-SIGNAL APPLICATIONS HUNG-SHENG National
CHEN,
Semiconductor
CHIH
Corporation, Santa
SIEH TENG, JI ZHAO, RAJEEVA LAHRI 2900 Semiconductor Drive, Clara, CA 95052, U.S.A.
LARRY
MOBERLY
and
M/S E-120, P.O. Box 58090,
(Receirred 20 January 1995) Abstract-Drain engineered MOSFETs are compared in terms of their impact on analog performance for submicron mixed-signal applications. The high energy implanted lightly doped drain (LDD) devices are shown only to improve voltage gain at high drain voltage, while large-angle-tilt implanted drain (LATID) devices show that the reduced substrate current and junction depth due to the tilt angle implant can significantly improve maximum available gain and voltage swing. Also, superior analog hot-carrier immunity in LATID MOSFETs is demonstrated through offset voltage drift in source-coupled transistor pair. These results suggest that LATID technology is promising for applications to submicron mixed analog/digital circuits.
1. INTRODUCTION
Combining high performance analog circuits with high speed digital circuits at the chip level has become a key element in many VLSI applications ranging from signal processing to telecommunications. However, as MOS channel lengths are scaled to improve digital performance and packing density, key analog parameters such as output resistance, voltage gain, and hot-carrier immunity are drastically degraded[l,2]. The most common approach to these problems is the addition of analog devices onto conventional digital CMOS processes to improve drain output resistance r,, and transconductance g, at the cost of increases process complexity[3]. However, for economical reasons, the analog part of a circuit must be fully compatible with a process basically tailored for digital requirements. With recent progress in drain engineered MOSFETs, such as LDD (lightly doped drain) and LATID (Large-Angle-Tilt Implanted Drain) technologies, device performance and reliability have been dramatically improved[4,5]. However, these technologies have been focused on digital applications. In this letter, we examine the impact of drain engineered MOSFETs on analog/digital device performance in a conventional CMOS process. 2. DEVICE
FABRICATION
The device examined in this study were fabricated using a submicron 5 V CMOS process with 135 A gate oxide, After poly-gate definition, reoxidation was performed to protect the oxide near the gate
Phosphorus n implant of a total n - ion flux of 4 x 10” cme2 was done with different implant energy and tilt angle. After formation of sidewall spacers, arsenic was implanted to form n+ drain. Process conditions and electrical parameters for both LDD and LATID structures examined in this study were summarized in Table 1.
edge.
3. RESULTS
AND DISCUSSION
One of the most important characteristics in analog circuit designs are the maximum available gain and the onsets of drain voltage at which gain starts decreasing on both sides of the maximum gain, which determines the dynamic swing of the drain voltage. To evaluate the analog characteristics of the structures shown in Table 1, voltage gain was measured on MOSFETs operated in saturation region with different channel length. The current biases Id for each MOSFETs were determined by (Id. L)/ W = 40 PA, which gives Vg5- Vfhm 1.O V. This measurement scheme is consistent with the operation of basic analog subcircuits, such as current mirrors and differential amplifiers, which operate under constant bias current at saturation region. For each drain voltage ,V,,, gate voltage Vgs was iteratively determined to obtained the desired Id. Once the bias point has been determined, a 25 mV change in VBsand Vds were then applied to the bias point to determine g,,, and rO, respectively. Finally, the voltage gain was calculated by the product of g, and r,. Substrate current Isubwas also monitored simultaneously at each bias point to evaluate its impact on voltage gain. 1857
Hung-Sheng Chen et al.
1858 Table
I.
Analog digital device and W/L = 3610.65 pm2 MOSFETs Unit
implant Energy Tilt angle Device parameters LC, V,h (wO.1 ~Aipm) Id (tic V,, = vgq = 5 V) Max. Iruh ((u I’,, = 5 V) Max. R, (kzfd.L/W =40pA) Max. gain (caId.L/W=40pA) Voltage swing ((a Gain > 25)
parameters
LDD
LDD
50 I
90 7
for LATID
n
keV degree
0.48 Pm !J 0.69 PA/Pm 500 2.9 PA!P’m X.6 kR 34 b ?.I
90 45
0.42 0.36 0.65 0.65 526 514 2.4 1.3 x.4 9.1 33 39 2.3 3.0
Figures 1 and 2 show the measured voltage gain versus drain voltage for LDD and LATID structures with drawn channel length L of 0.65 and 2.88 pm, respectively. One can see that, in all the devices measured, the voltage gain is reduced at high I’,,, due to weak avalanche breakdown. The avalanche induced Isub turn on the source injection and, subsequently, I,, shows a rise with drain voltage and voltage gain drops dramatically. This substrate current induced body effect (SCBE) limits the maximum gain and voltage swing[l]. In low Vd,. the velocity saturation region near the drain extends toward the source, which reduces the effective channel length and in turn decreases the voltage gain. This channel length modulation effect (CLM) also limits the maximum available gain and voltage swing[l]. To improve the voltage gain at high V,,, the drain structures used in improving hot-carrier reliability were employed to suppress I,ub. High energy (90 keV) implant is effective in suppressing lsub because the peak electric field in the n drain shifts away from the surface, which separates the current flow from the high field region[4]. LATID is also effective in suppressing I,“,, due to its increased depletion width at
Drain Voltage
(V)
Fig. 2. Voltage gain and the ratio of substrate current to drain current vs drain voltage for different drain structure (drawn dimension W/L = 36/2.88 pm, bias condition: (I,,.L)/W=40pA and V@- V,,- I.OV).
gate/r] overlap region[5]. As shown in Figs I and 2, the lsub/ld ratio in both 90 keV implanted LDD and LATID devices are reduced significantly. As a result, voltage gain in both structures are improved at high I’,, as compared to 50 keV implanted LDD devices. Such a reduction in ISUb/& ratio not only improves voltage gain and hot-carrier reliability, but also serves to minimize the crosstalk induced by impact ionization between neighboring analog and digital circuits[6], which is of great importance in highprecision mixed-signal circuits. To improve voltage gain at high Vds by increasing implant energy can cause gain degradation in low Vds region. A semi-empirical model for the output resistance of an MOS device for a given bias current can be expressed as[7]:
F
P - 0.06 g g ? - 0.04 7 !? -
-0
1
2
3
Drain Voltage
4
0.02
2G J 0 5 a 2
5
(V)
Fig. 1. Voltage gain and the ratio of substrate current to drain current vs drain voltage for different drain structure (drawn dimension W/L = 36/0.65pm, bias condition: (I,.L)/W=40pA and Vgs- V,,- l.OV).
where L,,, To, and X, are effective channel length, oxide thickness and junction depth, respectively. One should note that r,, decreases as L,,/,,$ is reduced at a given gate oxide thickness and bias current. As shown in Fig. I, by increasing the implant energy in LDD device, voltage gain can be increased for V,, > 3 V due to the reduced SCBE. However, for Vd, < 3 V voltage gain degrades in L = 0.65 pm devices. This is explained by the reduced L,,/& due to higher implant energy. The increased X, and reduced L,, enhance channel length modulation and, as a result, r0 and voltage gain degrades. It is noted that as channel length increases, the CLM effect reduces. Therefore, as shown in Fig. 2, the voltage gain at low Vdsin 50 and 90 keV LDD devices become comparable. In LATID devices not only IsUb is reduced, the junction depth also decreases monotonously with
1859
Analog submicron MOSFETs lo2 -f-o-
LATID - 90 keV LDD - 90 keV
10’
loo10’
10’
10”
10’
lo5
Time (set) Fig. 3. Offset voltage drift of source-coupled transistor pair as a function of time for LDD and LATID devices (drawn dimension W/L = 36/0.72pm, stress condition: Vdr= 7 V, V@= 2.5 V).
increasing tilt angle[5], which provides improved resistance to CLM. As shown in Figs 1 and 2, the gain and voltage swing have been improved in LATID devices at both high and low drain voltage regions. It is noted that even though L,, has been substantially decreased from 0.42 to 0.36 pm with LATID implant in 0.65 pm devices. LATID devices are able to provide improved gain over a wider drain voltage range. Importantly, as the channel length increases, L,, becomes comparable in LDD and LATID devices. The increase in tilt angle compared to a conventional LDD design becomes key to maintaining a shallow drain junction, and thus providing further improvement in voltage gain for L = 2.88 pm devices (maximum voltage gain increases from 34 to 39 at L = 0.65pm and from 220 to 360 at L = 2.88 pm). Table 1 summarizes the device characteristics of the drain engineered MOSFETs examined in this study. It is noted that LATID device improves not only analog performance, but also increases current drive capability.
Device mismatching is a major limitation to the accuracy of analog circuits, which can be aggravated by hot-carrier effects[2]. Many aspects of CMOS analog circuits can be discerned from examining the simple source-coupled transistor pair. By comparing offset voltage before and after hot-carrier stress, the effect of drain engineering on analog hot-carrier reliability can be determined. Figure 3 compares the offset voltage drift between LDD and LATID devices. As can be seen, LDD devices have significant offset voltage drift. This is a direct reflection of higher electric field near the drain junction in LDD devices. With the introduction of LATID, electric field and substrate current is reduced. As a result, offset voltage drift improves dramatically. 4. CONCLUSIONS
In conclusion, LATID devices surpass the conventional LDD devices not only in digital performance but also in analog performance. Excellent analog device characteristics and offset voltage drift in LATID MOSFETs have been achieved without compromising digital performance or increasing process complexity. These results suggest that LATID technology is scalable for submicron mixed-signal applications. REFERENCES 1.
2. 3. 4. 5. 6. 7.
J. H. Huang, Z. H. Liu. M. C. Jeng, P. K. Ko and C. Hu, IEDM, p. 569 (1992). J. E. Chung. K. N. Quader. C. G. Sodini, P. K. Ko, and C. Hu, IEDM p. 553 (1990). L. T. Su, J. A. Yasaitis and D. A. Antoniadis, IEDM. p. 367 (1991). E. Matsuoka, K. Kasai. H. Oyamatsu, M. Kinugawa and K. Maeguchi, IEDM, p. 833 (1990). T. Hori and K. Kurimoto. IEEE Trans. Electron Dec~ices, p. 2312 (1992). K. Sakui, S. Wong and B. Wooley, IEEE Trans. Electron Devices. p. 1603 (1994). C. G. Sodini, S. S. Wong and P. K. Ko, IEEE J. Solid St. Circuits, p. 118 (1989).
Solid-Slate
Pergamon
Copyright 0 I995 Elsevier Science Ltd Printed in Great Britain. All rights reserved
003%1101(95)00029-1
0038-l I01195 $9.50 + 0.00
ANALOG CHARACTERISTICS OF DRAIN ENGINEERED SUBMICRON MOSFETs FOR MIXED-SIGNAL APPLICATIONS HUNG-SHENG National
CHEN,
Semiconductor
CHIH
Corporation, Santa
SIEH TENG, JI ZHAO, RAJEEVA LAHRI 2900 Semiconductor Drive, Clara, CA 95052, U.S.A.
LARRY
MOBERLY
and
M/S E-120, P.O. Box 58090,
(Receirred 20 January 1995) Abstract-Drain engineered MOSFETs are compared in terms of their impact on analog performance for submicron mixed-signal applications. The high energy implanted lightly doped drain (LDD) devices are shown only to improve voltage gain at high drain voltage, while large-angle-tilt implanted drain (LATID) devices show that the reduced substrate current and junction depth due to the tilt angle implant can significantly improve maximum available gain and voltage swing. Also, superior analog hot-carrier immunity in LATID MOSFETs is demonstrated through offset voltage drift in source-coupled transistor pair. These results suggest that LATID technology is promising for applications to submicron mixed analog/digital circuits.
1. INTRODUCTION
Combining high performance analog circuits with high speed digital circuits at the chip level has become a key element in many VLSI applications ranging from signal processing to telecommunications. However, as MOS channel lengths are scaled to improve digital performance and packing density, key analog parameters such as output resistance, voltage gain, and hot-carrier immunity are drastically degraded[l,2]. The most common approach to these problems is the addition of analog devices onto conventional digital CMOS processes to improve drain output resistance r,, and transconductance g, at the cost of increases process complexity[3]. However, for economical reasons, the analog part of a circuit must be fully compatible with a process basically tailored for digital requirements. With recent progress in drain engineered MOSFETs, such as LDD (lightly doped drain) and LATID (Large-Angle-Tilt Implanted Drain) technologies, device performance and reliability have been dramatically improved[4,5]. However, these technologies have been focused on digital applications. In this letter, we examine the impact of drain engineered MOSFETs on analog/digital device performance in a conventional CMOS process. 2. DEVICE
FABRICATION
The device examined in this study were fabricated using a submicron 5 V CMOS process with 135 A gate oxide, After poly-gate definition, reoxidation was performed to protect the oxide near the gate
Phosphorus n implant of a total n - ion flux of 4 x 10” cme2 was done with different implant energy and tilt angle. After formation of sidewall spacers, arsenic was implanted to form n+ drain. Process conditions and electrical parameters for both LDD and LATID structures examined in this study were summarized in Table 1.
edge.
3. RESULTS
AND DISCUSSION
One of the most important characteristics in analog circuit designs are the maximum available gain and the onsets of drain voltage at which gain starts decreasing on both sides of the maximum gain, which determines the dynamic swing of the drain voltage. To evaluate the analog characteristics of the structures shown in Table 1, voltage gain was measured on MOSFETs operated in saturation region with different channel length. The current biases Id for each MOSFETs were determined by (Id. L)/ W = 40 PA, which gives Vg5- Vfhm 1.O V. This measurement scheme is consistent with the operation of basic analog subcircuits, such as current mirrors and differential amplifiers, which operate under constant bias current at saturation region. For each drain voltage ,V,,, gate voltage Vgs was iteratively determined to obtained the desired Id. Once the bias point has been determined, a 25 mV change in VBsand Vds were then applied to the bias point to determine g,,, and rO, respectively. Finally, the voltage gain was calculated by the product of g, and r,. Substrate current Isubwas also monitored simultaneously at each bias point to evaluate its impact on voltage gain. 1857
Hung-Sheng Chen et al.
1858 Table
I.
Analog digital device and W/L = 3610.65 pm2 MOSFETs Unit
implant Energy Tilt angle Device parameters LC, V,h (wO.1 ~Aipm) Id (tic V,, = vgq = 5 V) Max. Iruh ((u I’,, = 5 V) Max. R, (kzfd.L/W =40pA) Max. gain (caId.L/W=40pA) Voltage swing ((a Gain > 25)
parameters
LDD
LDD
50 I
90 7
for LATID
n
keV degree
0.48 Pm !J 0.69 PA/Pm 500 2.9 PA!P’m X.6 kR 34 b ?.I
90 45
0.42 0.36 0.65 0.65 526 514 2.4 1.3 x.4 9.1 33 39 2.3 3.0
Figures 1 and 2 show the measured voltage gain versus drain voltage for LDD and LATID structures with drawn channel length L of 0.65 and 2.88 pm, respectively. One can see that, in all the devices measured, the voltage gain is reduced at high I’,,, due to weak avalanche breakdown. The avalanche induced Isub turn on the source injection and, subsequently, I,, shows a rise with drain voltage and voltage gain drops dramatically. This substrate current induced body effect (SCBE) limits the maximum gain and voltage swing[l]. In low Vd,. the velocity saturation region near the drain extends toward the source, which reduces the effective channel length and in turn decreases the voltage gain. This channel length modulation effect (CLM) also limits the maximum available gain and voltage swing[l]. To improve the voltage gain at high V,,, the drain structures used in improving hot-carrier reliability were employed to suppress I,ub. High energy (90 keV) implant is effective in suppressing lsub because the peak electric field in the n drain shifts away from the surface, which separates the current flow from the high field region[4]. LATID is also effective in suppressing I,“,, due to its increased depletion width at
Drain Voltage
(V)
Fig. 2. Voltage gain and the ratio of substrate current to drain current vs drain voltage for different drain structure (drawn dimension W/L = 36/2.88 pm, bias condition: (I,,.L)/W=40pA and V@- V,,- I.OV).
gate/r] overlap region[5]. As shown in Figs I and 2, the lsub/ld ratio in both 90 keV implanted LDD and LATID devices are reduced significantly. As a result, voltage gain in both structures are improved at high I’,, as compared to 50 keV implanted LDD devices. Such a reduction in ISUb/& ratio not only improves voltage gain and hot-carrier reliability, but also serves to minimize the crosstalk induced by impact ionization between neighboring analog and digital circuits[6], which is of great importance in highprecision mixed-signal circuits. To improve voltage gain at high Vds by increasing implant energy can cause gain degradation in low Vds region. A semi-empirical model for the output resistance of an MOS device for a given bias current can be expressed as[7]:
F
P - 0.06 g g ? - 0.04 7 !? -
-0
1
2
3
Drain Voltage
4
0.02
2G J 0 5 a 2
5
(V)
Fig. 1. Voltage gain and the ratio of substrate current to drain current vs drain voltage for different drain structure (drawn dimension W/L = 36/0.65pm, bias condition: (I,.L)/W=40pA and Vgs- V,,- l.OV).
where L,,, To, and X, are effective channel length, oxide thickness and junction depth, respectively. One should note that r,, decreases as L,,/,,$ is reduced at a given gate oxide thickness and bias current. As shown in Fig. I, by increasing the implant energy in LDD device, voltage gain can be increased for V,, > 3 V due to the reduced SCBE. However, for Vd, < 3 V voltage gain degrades in L = 0.65 pm devices. This is explained by the reduced L,,/& due to higher implant energy. The increased X, and reduced L,, enhance channel length modulation and, as a result, r0 and voltage gain degrades. It is noted that as channel length increases, the CLM effect reduces. Therefore, as shown in Fig. 2, the voltage gain at low Vdsin 50 and 90 keV LDD devices become comparable. In LATID devices not only IsUb is reduced, the junction depth also decreases monotonously with
1859
Analog submicron MOSFETs lo2 -f-o-
LATID - 90 keV LDD - 90 keV
10’
loo10’
10’
10”
10’
lo5
Time (set) Fig. 3. Offset voltage drift of source-coupled transistor pair as a function of time for LDD and LATID devices (drawn dimension W/L = 36/0.72pm, stress condition: Vdr= 7 V, V@= 2.5 V).
increasing tilt angle[5], which provides improved resistance to CLM. As shown in Figs 1 and 2, the gain and voltage swing have been improved in LATID devices at both high and low drain voltage regions. It is noted that even though L,, has been substantially decreased from 0.42 to 0.36 pm with LATID implant in 0.65 pm devices. LATID devices are able to provide improved gain over a wider drain voltage range. Importantly, as the channel length increases, L,, becomes comparable in LDD and LATID devices. The increase in tilt angle compared to a conventional LDD design becomes key to maintaining a shallow drain junction, and thus providing further improvement in voltage gain for L = 2.88 pm devices (maximum voltage gain increases from 34 to 39 at L = 0.65pm and from 220 to 360 at L = 2.88 pm). Table 1 summarizes the device characteristics of the drain engineered MOSFETs examined in this study. It is noted that LATID device improves not only analog performance, but also increases current drive capability.
Device mismatching is a major limitation to the accuracy of analog circuits, which can be aggravated by hot-carrier effects[2]. Many aspects of CMOS analog circuits can be discerned from examining the simple source-coupled transistor pair. By comparing offset voltage before and after hot-carrier stress, the effect of drain engineering on analog hot-carrier reliability can be determined. Figure 3 compares the offset voltage drift between LDD and LATID devices. As can be seen, LDD devices have significant offset voltage drift. This is a direct reflection of higher electric field near the drain junction in LDD devices. With the introduction of LATID, electric field and substrate current is reduced. As a result, offset voltage drift improves dramatically. 4. CONCLUSIONS
In conclusion, LATID devices surpass the conventional LDD devices not only in digital performance but also in analog performance. Excellent analog device characteristics and offset voltage drift in LATID MOSFETs have been achieved without compromising digital performance or increasing process complexity. These results suggest that LATID technology is scalable for submicron mixed-signal applications. REFERENCES 1.
2. 3. 4. 5. 6. 7.
J. H. Huang, Z. H. Liu. M. C. Jeng, P. K. Ko and C. Hu, IEDM, p. 569 (1992). J. E. Chung. K. N. Quader. C. G. Sodini, P. K. Ko, and C. Hu, IEDM p. 553 (1990). L. T. Su, J. A. Yasaitis and D. A. Antoniadis, IEDM. p. 367 (1991). E. Matsuoka, K. Kasai. H. Oyamatsu, M. Kinugawa and K. Maeguchi, IEDM, p. 833 (1990). T. Hori and K. Kurimoto. IEEE Trans. Electron Dec~ices, p. 2312 (1992). K. Sakui, S. Wong and B. Wooley, IEEE Trans. Electron Devices. p. 1603 (1994). C. G. Sodini, S. S. Wong and P. K. Ko, IEEE J. Solid St. Circuits, p. 118 (1989).