- Email: [email protected]
SiGe heterojunction MOSFETs from capacitance transient
Applied Surface Science 224 (2004) 278–282
Analysis of carrier generation lifetime in strained-Si/SiGe heterojunction MOSFETs from capacitance transient L.K. Beraa,*, Shajan Mathewa, N. Balasubramaniana, G. Braithwaiteb, M.T. Currieb, F. Singaporewalab, J. Yapb, R. Hammondb, A. Lochtefeldb, M.T. Bulsarab, E.A. Fitzgeraldb a
Institute of Microelectronics, 11, Science Park Road, Singapore Science Park II, 117685 Singapore b AmberWave Systems Corp., 13 Garabedian Drive, Salem, NH, 03079, USA
Abstract Carrier generation lifetime (tg) in strained-Si/SiGe has been investigated using capacitance transient method in MOS structure. Interface properties of thermally grown gate oxide on strained-Si/SiGe has been studied prior to transient capacitance measurements. Average midgap value of interface state density (Dit) extracted from quasi-static CV measurement is around 2 1010 to 5 1010 cm2 eV1 for both strained-Si and bulk-Si samples. The observed non-linear behavior of capacitance transient characteristics for strained-Si/SiGe heterostructure are due to the carrier confinement in the potential wells caused by virtue of the valence band and conduction band discontinuities. Generation lifetime in strained-Si and SiGe buffer layer estimated from the segments of Zerbst plot having different slopes. The value of generation lifetime in strained-Si, SiGe buffer and co-processed bulk-Si is ranges from 120 to 170 ms, 20 to 90 ms and 177 ms, respectively. # 2003 Elsevier B.V. All rights reserved. PACS: 85.30; 71.20.M,N; 73.61.E Keywords: SiGe; Heterostructure; Strained-Si; Generation lifetime; Band offset
1. Introduction Silicon based heteroepitaxy of semiconductor materials has been an active area of research for the last two decades. The interest is driven by the possibility of creating novel electronic and optical devices, as well as integrating devices in different materials systems, leading to the production of integrated circuits with increased functionality and lower cost [1,2]. Recent research shows that strained-Si/SiGe hetero*
Corresponding author. Tel.: þ65-68700115; fax: þ65-67770670. E-mail address: [email protected] (L.K. Bera).
structures offer a very attractive platform for building high perfomance ICs due to its enhanced mobility of electrons and holes [3–7]. The epitaxially grown Si layer on relaxed SiGe buffer gives rise to a biaxially tensile Si film when its thickness is below a critical value. The strain is caused by the lattice mismatch of Si and SiGe. (The lattice mismatch between Si and Ge is 4.2%.) The strain in film splits conduction band energy valley and degeneracy of (HL/LH) valence band [8]. Both valley splitting and degeneracy reduces carrier effective mass along the transport direction. The separation of the conduction band minima reduces intervally scattering and deformation of valence band reduces interband scattering compared to bulk-Si. As a
0169-4332/$ – see front matter # 2003 Elsevier B.V. All rights reserved. doi:10.1016/j.apsusc.2003.08.054
L.K. Bera et al. / Applied Surface Science 224 (2004) 278–282
result the electron and hole mobilities are increased in strained Si [9–12]. As the IC industry trend points to widespread use of strained Si epitaxy in the sub-100 nm era, the understanding, characterization and quality monitoring of these epitaxial layers assume great significance. Carrier generation lifetime (tg) is one parameter which is traditionally used to characterize epi layers. This paper describes the application of the well known ‘‘Zerbst’’ technique to measure the carrier generation lifetime in strained Si/relaxed SiGe epitaxial layers. p-MOS structures formed on strained Si/SiGe grown on a Si substrate were used in this analysis. We have investigated the effect of band discontinuity on capacitance transient characteristics and estimated generation lifetime in strained-Si and relaxed-SiGe layers.
2. Device description The wafers used in this work consist of epitaxial layer stacks as shown in Fig. 1. The thickness of
279
strained Si on relaxed SiGe buffer ranges from 80 ˚ . p-MOS structures were fabricated after to 1000 A ˚ thick implanting the wafers with phosphorous. 52 A ˚ gate oxide and 2000 A thick polysilicon doped with B (by implantation) were used in the MOS structure. Fig. 1 shows the schematic cross section of the MOS test structure and the associated band line-up under a negative gate bias. Ti-silicide was formed on gate polysilicon as a part of self-aligned p-MOSFET fabrication. The Al/1%–Si was deposited in the back-side of the wafers for back contact. The samples were then annealed at 400 8C for 30 min in forming gas.
3. Results and discussions Fig. 2 shows the quasi-static C–V characteristics of MOS capacitors grown on different strained-Si and ˚ ) was control-Si wafers. The oxide thickness (57 A estimated from the accumulation capacitance, which is in quite close agreement with measured value, by ellipsometer. The minimum capacitance values are higher for thinner strained-Si wafer, which indicates
Fig. 1. Schematic cross section of the MOS test structure on strained-Si/SiGe and associated energy band line-up under a negative gate bias.
280
L.K. Bera et al. / Applied Surface Science 224 (2004) 278–282
2.40E+02
Capacitance (pF)
2.00E+02
1.60E+02
1.20E+02
Strained-Si bulk-Si
8.00E+01
4.00E+01 -3.0
-2.0
-1.0
0.0
1.0
2.0
3.0
Bias (V)
Fig. 2. Quasi-static C–V characteristics of MOS capacitors on strained-Si and bulk-Si wafers.
higher interface state density (Dit). The calculated interface state density versus energy characteristics for different samples are shown in Fig. 3. The Dit values for different samples are in the range 2 1010 to 6 1010 cm2 eV1 at mid gap. However, thinnest strained-Si sample shows higher Dit value (1 1011 to 2 1011 ) cm2 eV1. It is known that Ge diffusion
from SiGe buffer takes place at different thermal cycles during device fabrication process. Presence of Ge in gate oxide will increase Dit [13–16]. We believe that higher Dit values in thinner strained-Si samples are due to the presence of diffused Ge at gate oxide/substrate interface. The C–T measurements were performed using HP4284A LCR meter. The MOS structure is first biased to accumulation by applying a voltage of >6 V. At time t ¼ 0 it is set to deep depletion by fast switching to 6 V. At this moment, the capacitance reaches the lowest value. It takes a while to form the inversion layer by carrier generation. The time for reaching the equilibrium inversion capacitance is therefore proportional to the generation lifetime. Fig. 4 shows the transient response of different strained-Si and bulkSi samples normalized to the inversion capacitance at time t ¼ 0. An initial decrease in capacitance on the transient characteristics appeared in all strained-Si samples and is in contrast to the bulk Si capacitors. This can be explained using the band diagram of the capacitor on strained-Si/SiGe after the application of negative voltage (deep depletion condition) to the gate terminal as shown in Fig. 1. During generation of electron-hole pair in the strained-Si layer, a fraction of electrons will be confined at the strained-Si/relaxed-
1.00E+14 Strained-Si Bulk-Si
1.00E+12
-2
-1
Dit (cm eV )
1.00E+13
1.00E+11
1.00E+10
1.00E+09 0.0
0.2
0.4
0.6
0.8
1.0
1.2
Energy (eV) Fig. 3. Interface state density (Dit) vs. energy plot for different strained-Si and bulk-Si samples.
L.K. Bera et al. / Applied Surface Science 224 (2004) 278–282
281
6.0
Strained-Si strained-Si
5.0
Bulk-Si
Cox /C measured
(C/Cinitial (t=0))
1.1
1.0
Bulk-Si
4.0
(A)
3.0
(B) 2.0 1.0
0.9
0.0
0
10
20
0
30
50
100
150
Time (s) Fig. 4. Normalised capacitance (C/Cinitial (t¼0)) vs. time characteristics of strained-Si/SiGe and bulk-Si samples. All open circle data correspond to strained Si of different thickness.
SiGe interface due the large conduction band offset. However, the generated holes drift to the inversion layer at SiO2/strained-Si interface. A fraction of the holes generated in the SiGe layer will be stored up in strained-Si/SiGe interface due to the valence band offset. If one assumes a net positive charge as a result of the above charge generations in the semiconductor region, it amounts to the placement of negative image charges on the gate electrode which increases the depletion width. Thus the measured capacitance
Fig. 5. Cox/Cmeasured vs. time characteristics of strained-Si/SiGe and bulk-Si samples. (*) Correspond to strained Si of different thickness.
decreases initially until the inversion charge in the SiO2/strained-Si interface dominate over the charges in the potential wells as shown in Fig. 4. The extent of the capacitance excursion would depend upon the carrier generation dynamics in a complex system containing different epi layers, interfaces and associated defects. Fig. 5 shows the Cox/Cmeasured versus time plot to investigate the non-linear characteristics of capacitance transient response. Note that all the samples show different segments having different
0.035 y = 0.0164x - 0.0244
fe r Si Ge b
uf
Strained-Si (80A)
0.02
2
d(Cox/C) /dt, s-1
0.03 0.025
0.015 0.01
Stra
0.005
dine
Si
y = 0.0055x + 0.0005
0 0
200
Time (sec)
1
2
3
4
Cf /C-1 ˚ ). Fig. 6. Zerbst plot from transient capacitance data of strained-Si/SiGe sample (strained-Si thickness is 80 A
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L.K. Bera et al. / Applied Surface Science 224 (2004) 278–282
slopes. Based on the depletion width, calculated from the capacitance transient response we choose two sections of the each curve to calculate the lifetime. The initial steep slopes (segment-A in Fig. 5) are attributed to the fast generation rate in SiGe layer. Segment-B shows the flattening characteristics, which indicates a slow generation rate in strained Si layer. ˚ ) MOS Typical Zerbst plot of strained-Si (80 A capacitor is shown in Fig. 6. The slope of the Zerbst plot from the strained-Si segment is lower compared to the SiGe segment. This clearly indicates higher generation life time for strained-Si compared SiGe layer as expected. Generation lifetime calculated from the slope in SiGe layer ranges from 20 to 90 ms. These values, in comparison with those reported previously, indicate high quality of the SiGe buffer [17,18]. The generation lifetime in strained-Si and co-processed bulk-Si is 120–170 ms and 177 ms, respectively. Comparable values of lifetime in both strained-Si and co-processed bulk-Si indicate that the ‘‘electrical’’ quality of strained-Si film is approaching that of the bulk. The smaller bandgap of strained Si can also contribute to lower carrier lifetime compared to bulk Si.
4. Conclusions The generation lifetime (tg) in strained-Si and SiGe buffer layer has been investigated using Zerbst technique. Quasi-static C–V was used to extract interface state density (Dit) before C–t measurements to evaluate the interface quality of gate oxide and its average midgap value is around 2 1010 to 5 1010 cm2 eV1 for both strained-Si and bulk-Si samples. The capacitance transient characteristics for strained-Si/ SiGe heterostructure show a non-linear behavior. This anomalous characteristics (compared to bulk-Si) is due to the carrier confinement in the valence band and conduction band offsets in strained-Si/SiGe heterostructure. The generation lifetime in strained-Si and SiGe buffer layer is estimated from the segments of Zerbst plot having different slopes. The extracted values of generation lifetime in SiGe buffer layer, strained-Si
and co-processed bulk-Si are 20–90, 120–170 and 177 ms, respectively. The generation lifetime data obtained for SiGe buffer point to a high quality of the epitaxial layer. The same is true for the strained Si epi-layer as the generation lifetime approaches that of bulk Si of equivalent doping. The results are of great significance as it demonstrates the use of a well known technique such as ‘‘Zerbst plot’’ for heteroepitaxial process characterization and monitoring.
References [1] P.M. Mooney, J.O. Chu, Ann. Rev. Mater. Res. 30 (2000) 335–362. [2] Y.H. Xie, E.A. Fitzgerald, D. Monroe, G.P. Watson, P.J. Silverman, Jpn. J. Appl. Phys. 33 (1994) 2372. [3] M.T. Currie, C.W. Leitz, T.A. Langdo, G. Taraschi, E.A. Fitzgerald, D.A. Antoniadis, J. Vac. Sci. Technol. B 19 (2001) 2268. [4] C.W. Leitz, M.T. Currie, M.L. Lee, Z.-Y. Cheng, D.A. Antoniadis, E.A. Fitzgerald, Appl. Phys. Lett. 79 (2001) 4246. [5] J. Welser, J.L. Hoyt, S. Takagi, J.F. Gibbons, Tech. Dig. Int. Electron Devices Meet. (1994) 373. [6] C.K. Maiti, L.K. Bera, S. Chattopadhyay, Semicond. Sci. Technol. 13 (1998) 1225. [7] K. Rim, S. Koester, M. Hargrove, J. Chu, P.M. Mooney, P.M. J. Ott, T. Kanarsky, P. Ronsheim,M. Ieong, A. Grill, H.S.P. Wong, VLSI Technol. Symp. (2001) 59. [8] R. People, IEEE J. Q. Electron 22 (1986) 1696. [9] T. Vogelsang, K.R. Hofmann, Appl. Phys. Lett. 63 (1993) 186. [10] J.B. Roldan, F. Ga´ miz, J.A. Lopez-Villanueva, J.E. Carceller, J. Appl. Phys. 80 (1996) 5121. [11] F. Gamiz, J.B. Roldan, J.A. Lopez-Villanueva, P. Cartujo, Appl. Phys. Lett. 69 (1996) 797. [12] G. Abstreiter, H. Brugger, T. Wolf, Physic. Rev. Lett. 54 (1985) 2441. [13] A. Terrasi, S. Scalese, R. Adorno, E. Ferlito, M. Spadafora, E. Rimini, Mater. Sci. Eng. B89 (2002) 269. [14] R.J.P. Lander, Y.V. Ponomarev, J.G.M. van Berkum, W.B. de Boer, IEEE Trans. Electron Dev. 48 (2001) 1826. [15] Y.J. Song, J.W. Lim, S.H. Kim, H.C. Bae, J.Y. Kang, K.W. Park, K.H. Shim, Solid State Electron. 46 (2002) 1983. [16] C.G. Ahn, H.S. Kang, Y.K. Kwon, S.M. Lee, B.R. Ryum, B.K. Kang, J. Appl. Phys. 86 (1999) 1542. [17] L.S. Riley, S. Hall, J.M. Bonar, Solid State Electron. 43 (1999) 2247. [18] S.M. Salih, Z. Radzimski, J. Honeycutt, G.A. Rozgonyi, K.E. Bean, K. Lindberg, Appl. Phys. Lett. 50 (1987) 1678.
Analysis of carrier generation lifetime in strained-Si/SiGe heterojunction MOSFETs from capacitance transient L.K. Beraa,*, Shajan Mathewa, N. Balasubramaniana, G. Braithwaiteb, M.T. Currieb, F. Singaporewalab, J. Yapb, R. Hammondb, A. Lochtefeldb, M.T. Bulsarab, E.A. Fitzgeraldb a
Institute of Microelectronics, 11, Science Park Road, Singapore Science Park II, 117685 Singapore b AmberWave Systems Corp., 13 Garabedian Drive, Salem, NH, 03079, USA
Abstract Carrier generation lifetime (tg) in strained-Si/SiGe has been investigated using capacitance transient method in MOS structure. Interface properties of thermally grown gate oxide on strained-Si/SiGe has been studied prior to transient capacitance measurements. Average midgap value of interface state density (Dit) extracted from quasi-static CV measurement is around 2 1010 to 5 1010 cm2 eV1 for both strained-Si and bulk-Si samples. The observed non-linear behavior of capacitance transient characteristics for strained-Si/SiGe heterostructure are due to the carrier confinement in the potential wells caused by virtue of the valence band and conduction band discontinuities. Generation lifetime in strained-Si and SiGe buffer layer estimated from the segments of Zerbst plot having different slopes. The value of generation lifetime in strained-Si, SiGe buffer and co-processed bulk-Si is ranges from 120 to 170 ms, 20 to 90 ms and 177 ms, respectively. # 2003 Elsevier B.V. All rights reserved. PACS: 85.30; 71.20.M,N; 73.61.E Keywords: SiGe; Heterostructure; Strained-Si; Generation lifetime; Band offset
1. Introduction Silicon based heteroepitaxy of semiconductor materials has been an active area of research for the last two decades. The interest is driven by the possibility of creating novel electronic and optical devices, as well as integrating devices in different materials systems, leading to the production of integrated circuits with increased functionality and lower cost [1,2]. Recent research shows that strained-Si/SiGe hetero*
Corresponding author. Tel.: þ65-68700115; fax: þ65-67770670. E-mail address: [email protected] (L.K. Bera).
structures offer a very attractive platform for building high perfomance ICs due to its enhanced mobility of electrons and holes [3–7]. The epitaxially grown Si layer on relaxed SiGe buffer gives rise to a biaxially tensile Si film when its thickness is below a critical value. The strain is caused by the lattice mismatch of Si and SiGe. (The lattice mismatch between Si and Ge is 4.2%.) The strain in film splits conduction band energy valley and degeneracy of (HL/LH) valence band [8]. Both valley splitting and degeneracy reduces carrier effective mass along the transport direction. The separation of the conduction band minima reduces intervally scattering and deformation of valence band reduces interband scattering compared to bulk-Si. As a
0169-4332/$ – see front matter # 2003 Elsevier B.V. All rights reserved. doi:10.1016/j.apsusc.2003.08.054
L.K. Bera et al. / Applied Surface Science 224 (2004) 278–282
result the electron and hole mobilities are increased in strained Si [9–12]. As the IC industry trend points to widespread use of strained Si epitaxy in the sub-100 nm era, the understanding, characterization and quality monitoring of these epitaxial layers assume great significance. Carrier generation lifetime (tg) is one parameter which is traditionally used to characterize epi layers. This paper describes the application of the well known ‘‘Zerbst’’ technique to measure the carrier generation lifetime in strained Si/relaxed SiGe epitaxial layers. p-MOS structures formed on strained Si/SiGe grown on a Si substrate were used in this analysis. We have investigated the effect of band discontinuity on capacitance transient characteristics and estimated generation lifetime in strained-Si and relaxed-SiGe layers.
2. Device description The wafers used in this work consist of epitaxial layer stacks as shown in Fig. 1. The thickness of
279
strained Si on relaxed SiGe buffer ranges from 80 ˚ . p-MOS structures were fabricated after to 1000 A ˚ thick implanting the wafers with phosphorous. 52 A ˚ gate oxide and 2000 A thick polysilicon doped with B (by implantation) were used in the MOS structure. Fig. 1 shows the schematic cross section of the MOS test structure and the associated band line-up under a negative gate bias. Ti-silicide was formed on gate polysilicon as a part of self-aligned p-MOSFET fabrication. The Al/1%–Si was deposited in the back-side of the wafers for back contact. The samples were then annealed at 400 8C for 30 min in forming gas.
3. Results and discussions Fig. 2 shows the quasi-static C–V characteristics of MOS capacitors grown on different strained-Si and ˚ ) was control-Si wafers. The oxide thickness (57 A estimated from the accumulation capacitance, which is in quite close agreement with measured value, by ellipsometer. The minimum capacitance values are higher for thinner strained-Si wafer, which indicates
Fig. 1. Schematic cross section of the MOS test structure on strained-Si/SiGe and associated energy band line-up under a negative gate bias.
280
L.K. Bera et al. / Applied Surface Science 224 (2004) 278–282
2.40E+02
Capacitance (pF)
2.00E+02
1.60E+02
1.20E+02
Strained-Si bulk-Si
8.00E+01
4.00E+01 -3.0
-2.0
-1.0
0.0
1.0
2.0
3.0
Bias (V)
Fig. 2. Quasi-static C–V characteristics of MOS capacitors on strained-Si and bulk-Si wafers.
higher interface state density (Dit). The calculated interface state density versus energy characteristics for different samples are shown in Fig. 3. The Dit values for different samples are in the range 2 1010 to 6 1010 cm2 eV1 at mid gap. However, thinnest strained-Si sample shows higher Dit value (1 1011 to 2 1011 ) cm2 eV1. It is known that Ge diffusion
from SiGe buffer takes place at different thermal cycles during device fabrication process. Presence of Ge in gate oxide will increase Dit [13–16]. We believe that higher Dit values in thinner strained-Si samples are due to the presence of diffused Ge at gate oxide/substrate interface. The C–T measurements were performed using HP4284A LCR meter. The MOS structure is first biased to accumulation by applying a voltage of >6 V. At time t ¼ 0 it is set to deep depletion by fast switching to 6 V. At this moment, the capacitance reaches the lowest value. It takes a while to form the inversion layer by carrier generation. The time for reaching the equilibrium inversion capacitance is therefore proportional to the generation lifetime. Fig. 4 shows the transient response of different strained-Si and bulkSi samples normalized to the inversion capacitance at time t ¼ 0. An initial decrease in capacitance on the transient characteristics appeared in all strained-Si samples and is in contrast to the bulk Si capacitors. This can be explained using the band diagram of the capacitor on strained-Si/SiGe after the application of negative voltage (deep depletion condition) to the gate terminal as shown in Fig. 1. During generation of electron-hole pair in the strained-Si layer, a fraction of electrons will be confined at the strained-Si/relaxed-
1.00E+14 Strained-Si Bulk-Si
1.00E+12
-2
-1
Dit (cm eV )
1.00E+13
1.00E+11
1.00E+10
1.00E+09 0.0
0.2
0.4
0.6
0.8
1.0
1.2
Energy (eV) Fig. 3. Interface state density (Dit) vs. energy plot for different strained-Si and bulk-Si samples.
L.K. Bera et al. / Applied Surface Science 224 (2004) 278–282
281
6.0
Strained-Si strained-Si
5.0
Bulk-Si
Cox /C measured
(C/Cinitial (t=0))
1.1
1.0
Bulk-Si
4.0
(A)
3.0
(B) 2.0 1.0
0.9
0.0
0
10
20
0
30
50
100
150
Time (s) Fig. 4. Normalised capacitance (C/Cinitial (t¼0)) vs. time characteristics of strained-Si/SiGe and bulk-Si samples. All open circle data correspond to strained Si of different thickness.
SiGe interface due the large conduction band offset. However, the generated holes drift to the inversion layer at SiO2/strained-Si interface. A fraction of the holes generated in the SiGe layer will be stored up in strained-Si/SiGe interface due to the valence band offset. If one assumes a net positive charge as a result of the above charge generations in the semiconductor region, it amounts to the placement of negative image charges on the gate electrode which increases the depletion width. Thus the measured capacitance
Fig. 5. Cox/Cmeasured vs. time characteristics of strained-Si/SiGe and bulk-Si samples. (*) Correspond to strained Si of different thickness.
decreases initially until the inversion charge in the SiO2/strained-Si interface dominate over the charges in the potential wells as shown in Fig. 4. The extent of the capacitance excursion would depend upon the carrier generation dynamics in a complex system containing different epi layers, interfaces and associated defects. Fig. 5 shows the Cox/Cmeasured versus time plot to investigate the non-linear characteristics of capacitance transient response. Note that all the samples show different segments having different
0.035 y = 0.0164x - 0.0244
fe r Si Ge b
uf
Strained-Si (80A)
0.02
2
d(Cox/C) /dt, s-1
0.03 0.025
0.015 0.01
Stra
0.005
dine
Si
y = 0.0055x + 0.0005
0 0
200
Time (sec)
1
2
3
4
Cf /C-1 ˚ ). Fig. 6. Zerbst plot from transient capacitance data of strained-Si/SiGe sample (strained-Si thickness is 80 A
282
L.K. Bera et al. / Applied Surface Science 224 (2004) 278–282
slopes. Based on the depletion width, calculated from the capacitance transient response we choose two sections of the each curve to calculate the lifetime. The initial steep slopes (segment-A in Fig. 5) are attributed to the fast generation rate in SiGe layer. Segment-B shows the flattening characteristics, which indicates a slow generation rate in strained Si layer. ˚ ) MOS Typical Zerbst plot of strained-Si (80 A capacitor is shown in Fig. 6. The slope of the Zerbst plot from the strained-Si segment is lower compared to the SiGe segment. This clearly indicates higher generation life time for strained-Si compared SiGe layer as expected. Generation lifetime calculated from the slope in SiGe layer ranges from 20 to 90 ms. These values, in comparison with those reported previously, indicate high quality of the SiGe buffer [17,18]. The generation lifetime in strained-Si and co-processed bulk-Si is 120–170 ms and 177 ms, respectively. Comparable values of lifetime in both strained-Si and co-processed bulk-Si indicate that the ‘‘electrical’’ quality of strained-Si film is approaching that of the bulk. The smaller bandgap of strained Si can also contribute to lower carrier lifetime compared to bulk Si.
4. Conclusions The generation lifetime (tg) in strained-Si and SiGe buffer layer has been investigated using Zerbst technique. Quasi-static C–V was used to extract interface state density (Dit) before C–t measurements to evaluate the interface quality of gate oxide and its average midgap value is around 2 1010 to 5 1010 cm2 eV1 for both strained-Si and bulk-Si samples. The capacitance transient characteristics for strained-Si/ SiGe heterostructure show a non-linear behavior. This anomalous characteristics (compared to bulk-Si) is due to the carrier confinement in the valence band and conduction band offsets in strained-Si/SiGe heterostructure. The generation lifetime in strained-Si and SiGe buffer layer is estimated from the segments of Zerbst plot having different slopes. The extracted values of generation lifetime in SiGe buffer layer, strained-Si
and co-processed bulk-Si are 20–90, 120–170 and 177 ms, respectively. The generation lifetime data obtained for SiGe buffer point to a high quality of the epitaxial layer. The same is true for the strained Si epi-layer as the generation lifetime approaches that of bulk Si of equivalent doping. The results are of great significance as it demonstrates the use of a well known technique such as ‘‘Zerbst plot’’ for heteroepitaxial process characterization and monitoring.
References [1] P.M. Mooney, J.O. Chu, Ann. Rev. Mater. Res. 30 (2000) 335–362. [2] Y.H. Xie, E.A. Fitzgerald, D. Monroe, G.P. Watson, P.J. Silverman, Jpn. J. Appl. Phys. 33 (1994) 2372. [3] M.T. Currie, C.W. Leitz, T.A. Langdo, G. Taraschi, E.A. Fitzgerald, D.A. Antoniadis, J. Vac. Sci. Technol. B 19 (2001) 2268. [4] C.W. Leitz, M.T. Currie, M.L. Lee, Z.-Y. Cheng, D.A. Antoniadis, E.A. Fitzgerald, Appl. Phys. Lett. 79 (2001) 4246. [5] J. Welser, J.L. Hoyt, S. Takagi, J.F. Gibbons, Tech. Dig. Int. Electron Devices Meet. (1994) 373. [6] C.K. Maiti, L.K. Bera, S. Chattopadhyay, Semicond. Sci. Technol. 13 (1998) 1225. [7] K. Rim, S. Koester, M. Hargrove, J. Chu, P.M. Mooney, P.M. J. Ott, T. Kanarsky, P. Ronsheim,M. Ieong, A. Grill, H.S.P. Wong, VLSI Technol. Symp. (2001) 59. [8] R. People, IEEE J. Q. Electron 22 (1986) 1696. [9] T. Vogelsang, K.R. Hofmann, Appl. Phys. Lett. 63 (1993) 186. [10] J.B. Roldan, F. Ga´ miz, J.A. Lopez-Villanueva, J.E. Carceller, J. Appl. Phys. 80 (1996) 5121. [11] F. Gamiz, J.B. Roldan, J.A. Lopez-Villanueva, P. Cartujo, Appl. Phys. Lett. 69 (1996) 797. [12] G. Abstreiter, H. Brugger, T. Wolf, Physic. Rev. Lett. 54 (1985) 2441. [13] A. Terrasi, S. Scalese, R. Adorno, E. Ferlito, M. Spadafora, E. Rimini, Mater. Sci. Eng. B89 (2002) 269. [14] R.J.P. Lander, Y.V. Ponomarev, J.G.M. van Berkum, W.B. de Boer, IEEE Trans. Electron Dev. 48 (2001) 1826. [15] Y.J. Song, J.W. Lim, S.H. Kim, H.C. Bae, J.Y. Kang, K.W. Park, K.H. Shim, Solid State Electron. 46 (2002) 1983. [16] C.G. Ahn, H.S. Kang, Y.K. Kwon, S.M. Lee, B.R. Ryum, B.K. Kang, J. Appl. Phys. 86 (1999) 1542. [17] L.S. Riley, S. Hall, J.M. Bonar, Solid State Electron. 43 (1999) 2247. [18] S.M. Salih, Z. Radzimski, J. Honeycutt, G.A. Rozgonyi, K.E. Bean, K. Lindberg, Appl. Phys. Lett. 50 (1987) 1678.