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Capacitance and doping profiles of ion-implanted, buried-channel MOSFETs
Solid-Store Electmicr Vol. 22, pp. 47-Y 0 Pergamon Press Ltd., 1979. Printed in Great Britain
CAPACITANCE AND DOPING PROFILES OF ION-IMPLANTED, BURIED-CHANNEL MOSFETS G. LUBBERTS and B. C. BURKEY
Research Laboratories, Eastman Kodak Company, Rochester, NY 14650,U.S.A. (Received 26 November
1977; in revised form
31 March
1978)
Abstract-Detailed capacitance measurements are presented of large-area, ion-implanted, buried-channel MOSFETs. The gate capacitance was measured as a function of gate-substrate voltage with drain (source)-substrate voltage as parameter. The MOSFETswerepreparedon 10n-cm, n-type,(111)Si. Boronions with doses of 4 X 10” and 8 x 10”lcmawere implanted through the gate oxide to a depth of 0.30-0.35pm in the Si. The devices were subjected to heat treatments of 900-1100°C. Calculated capacitances based on a one-dimensional, partial-ionization model are in good agreement with experiment. The model is used to assess the validity of the C-V profiling technique based on the abrupt space-charge approximation. It is concluded that the impurity distribution can be measured quite accurately near the peak of the profile, for ion-implantation and heat-treatment conditions examined in this paper. However, the “tails” of the distribution cannot be measured with this technique. The limitations of the C-V profiling method are discussed quantitatively for a stepped profile
NOTATION
space-charge approximation and assuming a uniform, abrupt or stepped doping distribution[2]. In this paper we calculate the gate capacitance as a function of gatesubstrate voltage with drain (source)-substrate voltage as parameter for buried, p-channel, ion-implanted MOSFETs taking account of the electron and hole statistics. This procedure basically involves solving Poisson’s equation using Boltzmann statistics to describe the electrons in the conduction band and modified Fermi-Dirac statistics to describe the holes in the valence band. The theoretical capacitance data are compared with experimental results of boron implanted MOSFETs. Impurity doping profiles are usually obtained from C-V measurements using the abrupt space-charge or depletion approximation. Another method using the differential body effect has recently been proposed[3,4]. The C-V method is a nondestructive method of considerable interest because of its sensitivity and simplicity. Rapidly varying profiles, however, cannot usually be measured by this method. The limitations of the C-V method have been discussed by several authors[S-91. These studies deal with one-sided p-n junctions, n+-h junctions, Schottky barriers, and MOS capacitors with nonuniform semiconductor doping, the doping species being of the same type as that of the substrate. On the other hand, Lehovec has considered the impurity profile obtained from C-V data for a uniformly doped n-type epitaxial semiconductor layer sandwiched between a blocking metal contact and a uniformly doped semiinsulating p-type substrate[lO]. The data for this device show that the C-V profiling method becomes progressively better for the n-type epitaxial layer as NdN,, increases, but the measured impurity distribution becomes an artifact when the peak channel carrier concentration becomes less than No In this paper we consider the C-V profiling method for a related configuration consisting of an ion-implanted p-channel MOSFET, where the impurity profile depends on the implantation and annealing conditions. Our results
gate area gate capacitance CG C OX gate oxide capacitance 8 electric field EF Fermi energy Si band gap energy EG k Boltzmann’s constant acceptor impurity profile N*(x) ND donor impurity density NO implanted dose N” density of states in valence band magnitude of electronic charge R” projected range minus to, + temperature “K 1 gate oxide thickness vcm; electrostatic potential profile VD drain (source)-substrate voltage V gate-substrate voltage Y Debye length e0x permittivity of SiOs % permittivity of Si P(X) space-charge density ULl standard deviation of implanted boron D standard deviation after heat treatment Equationsare written in MKS units. A
1. lNTRODUCTION
In the last few years, capacitance measurements have been made on buried-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) as a tool for characterizing bulk-transfer charge-coupled devices [ 1,2]. In essence, these devices consist of a MOS structure with a shallow Si layer of doping opposite to that of the Si substrate and located between the oxide and the substrate. Since the structure of charge-coupled devices usually requires rather complex fabrication procedures, it is convenient to obtain important device parameters from buried-channel MOSFETs. The capacitance plays a prominent role in assessing device performance as shown by Mohsen and Morris[l]. As a first approximation, Taylor has calculated C-V curves for ion-implanted MOSFETs using the abrupt 47
48
G. LUBBERTS and B. C. BURKEY
indicate that the impurity distribution can be obtained near the peak of the doping distribution. However, the “tails” of the impurity distribution cannot be measured with this technique. 2. THEOmICALMODEL A one-dimensional model is appropriate for capacitance calculations of the buried-channel MOSFET. We consider a p-channel device with channel doping N,.Jx) formed on an n-type substrate with constant donor doping density ND The x-coordinate is perpendicular to the gate area of the MOSFET as shown in Fig. 1. The charge density and the corresponding band profile are shown schematically in Fig. 1 for a stepped acceptor profile. The drain and source are connected and biased negative relative to the substrate as shown in Fig. 2. The potential V(x) is assumed zero in the bulk Si. The upward direction of the single-ended arrows gives the positive direc-
tion for the electron potential energy and the direction of negative electrostatic potential energy. The electrostatic pote&l V(x) in the oxide (SiOJ and the semiconductor (Si) is given by Poisson’s equation - I”, < X < 0 x*0
(1)
where the charge density p is given by
P(X.VI = y [ NJ1 -exp (+qV/kT)] -
iVa(x)
(2) Equation (1) is subject to the boundary and continuity conditions V(m)= 0, V(- t,,) = v,.
(3)
V(O_)= V(O’), d V(O-) d V(O+) = 6s dx dx
Gx -
The symbols used in eqns (l)-(3) represent the following quantities. The voltage VO is the drain (source)-substrate voltage, VG the gate-substrate voltage, EC the Si bandgap, N, the density of valence band states, and EF the Fermi energy measured with respect to the conduction band edge in the bulk Si. Finally, eoXand l, are the low-frequency permittivities of SiOZand Si, respectively. Charge in the oxide, interface states, and metal-semiconductor work function difference were assumed equal Fig. 1. Schematic band protile and charge density for a buriedchannel MOSFET in the direction perpendicular to the gate area. to zero. The term ND exp (qV/kT) in eqn (2) represents the electron concentration in the conduction band. This The substrate donor concentration is uniform throughout the Si expression becomes inaccurate for large positive V, crystal, and the acceptor profile is a stepped protile as illustrated. The gate-substrate voltage, V,, and the drain-substratevoltage, when electrons build up at the Si-SiOZ interface. V, are chosen such that holes are present in the buried channel. However, this region is of little interest in this work. The The potential energy is assumed zero at the conduction band last term in eqn (2) describes the hole density in the (03) edge in the bulk Si. For simplicity, charge in the oxide and valence band. This form is suitable for both nondemetal-semiconductor work function difference are assumed equal to zero. generate and partial degenerate occupancy [ll]. For our work this simplification resulted in less than 1% error for the hole density as determined by the Fermi-Dirac integral [ 11). Since an analytic solution of eqn (1) is not possible, a numerical solution was obtained by means of the finite difference approach with over-relaxation[ 121. The x-coordinate is divided into 80-100 mesh points. The variable mesh spacing is approximately 200 A in the oxide, 10 A near the Si-Si02 boundary, 250A in the channel which extends to approximately 5OOOAbelow the Si-SiOZ interface, and 1OOOAbeyond the channel region. The resulting nonlinear finite difference equation Bt each mesh point is linearized using the Newton-Raphson method, and the set of equations is solved iteratively Fig. 2. Experimental setup for capacitance measurements of using successive over-relaxation. buried-channel MOSFETs. The capacitance data presented in this paper are obtained with points A and B connected. A 45 mV The finite difference scheme requires that the initial peak-to-peak signal of ld Hz frequency is superimposed on the potential profile is close to the actual potential, otherwise slowly varying (linear ramp) gate-substrate voltage Vo. The calicomputer overflows can occur as a result of large brated output of the lock-in amplifier gives the capacitance. exponential factors. The initial potential is obtained by Points A and D are connected when the substrate doping is assuming complete ionization; i.e. p(x) = q[No - N&)] measured as discussed in Ref. [ 141.
Capacitanceand dopingprofilesof ion-implanted,buried-channelMOSFETs corresponding to the punch-through region of the capacitance-voltage curve (see Section 3.2), with a Gaussian channel doping judiciously chosen to apl proximate N,&)[13]. The lirst two potential profiles are thus obtained for a VG in punch-through, and subsequent profiles.for the desired channel doping are obtained at 50 mV increments in V, using the preceding two potential profiles. Iterations for each profile calculation continue until the maximum change in potential between successive iterations is less than 2.5 pV. When the potential profile calculations are completed, the gate capacitance, which is defined as
can be found from the change in electric field, 8, at x = - r,, resulting from the 50 mV step in VG. The quantity A represents the active gate area. Approximately 4min of computation on an IBM 370/158 computer is required to generate a capacitance curve over a 1OV range in VG. All calculations in this paper are for T = N, = 1.138x 10’9/cm3, lox= 3OO”K, Eo=l.leV, 3.453x IO-” and 4 = 1.036x IO-“’ F/m. For lO&cm, ntype Si, EF = -0.28 eV.
3. M-AL
TECHNIQIJFS AND RESULTS
3.1. Device fabrication and measuring &rcuitry MOSFETs were fabricated on (111) n-type Si of 10acm (215%) resistivity. The buried layer was obtained by implanting 150keV boron ions (“B+) into the Si through the gate oxide. Doses of 4X 10” and 8X 10”/cm2 were used in these experiments. The implantation was done in a “random direction” by tilting the wafers 7” toward the ion beam. After implantation the devices were annealed at 900°C for 30 min. 1000°Cfor 4 hr, and 1lOOYZfor 4 hr in Nz ambient. This step was followed by Al metallization and sintering. The distance between source and drain, L, is 530 Frn, and the width, W, oi the gate oxide is 2540pm, corresponding to A = 1.346x lo-* cm*. Such large area MOSFETs are desirable for accurate capacitance measurements, in particular when the substrate doping is obtained from deep depletion (punch-through) capacitance measurements [ 141. The circuitry for capacitance measurements is shown in Fig. 2. The p+ source and drain are connected and reversed biased with respect to the substrate. The channel-substrate voltage is externally controlled through the p+ source and drain contacts. A 45 mV peak-to-peak modulating voltage of lo3 Hz frequency is superimposed on the slowly varying (linear ramp) dc gate-substrate voltage, VG, and causes a displacement current which develops a voltage across Rr. This ac voltage is detected by a lock-in amplifier tuned to the same frequency. The calibrated output of the lock-in amplifier then gives the capacitance. Feeding the output of the lock-in amplifier into a function module gives l/CO’, and with a simple differentiating circuit, the time derivative d(l/C,*)/dt, is obtained. Since SSE Vd. 22. No. I-D
49
(5) and d VJdt is constant in our experiments, d( l/C,*)/d V, and the doping profile are measured directly (Section 4.1). The capacitance data discussed in this paper are obtained by connecting points A and B in Fig. 2. Parasitic and gate-source and gate-drain overlap capacitances are subtracted from the measurements using the d.c. zero offset voltage on the lock-in amplifier. (The overlap capacitances are determined with the device in the punch-through condition, by grounding the substrate and connecting Rr between ground and the positive terminal of the source and drain voltage supply.) Points A and D in Fig. 2 are connected for substrate doping measurement as discussed in a previous paper[l4]. The gate capacitance is generally frequency dependent as a result of distributed RC effects in the device[l]. Our measurements’ and calculations indicate that 103Hz is sufficiently low for capacitance measurements in agreement with Mohsen and Morris[l:. All LkAbUrements were made at room temperature. 3.2. Capacitance data and calculations The measured gate capacitance, Cc, as a function of gate-substrate voltage, V,, is shown in Fig. 3. For each curve, the drain (source)-substrate voltage, VD, is fixed. The MOSFET was implanted with a dose, N,, of 8 x 10” boron ions/cm* and annealed at 1ooo”Cfor 4hr. Under these conditions the G--V, curve was also calculated using the method of Section 2. The acceptor doping density in eqn (2) is given by (6) The parameters used in the calculation are R, =
Fig. 3. Gate capacitance, Co, as a function of gate-substrate voltage, V,, for various dram-substratevoltages, V, The MOSFET was implanted with 8X 10” boron ions/cm2 of 150keV energy.The device was heat treatedat Iooo”Cfor 4 hr in N2 ambient. Measuredcapacitancesare given by the solid line; calculated values are indicated by the circles. A Gaussian acceptor profilewas used in the calculationwith & = 8 x IO”/cm*, R, = %@S A,and u = 2425 A (see text). Other rei&ant measured parameters used in the Co-V, curve calculation are ND = 4.5 x ~o”/cn?, and r‘,x=1120A.
50
G. LUBBERTSand B. C. BURKEY
3085 A, u = 2425 A, N, = 8 x lO”/cm’, N,= 4.5 x 101“/cm3, and the gate oxide thickness. t,, = 1120 A. The standard deviation, LT.was obtained by assuming that the Gaussian profile spreads as (T= (oO’ + 2Dt)“* during heat treatment, where D is the diffusion constant, t is the duration of heat treatment, and oh is the standard deviation prior to heat treatment. Since the range statistics of a 150 keV “B’ beam are about the same in Si and SiOZ, we find from LSS tables that crO= 834 A and the projected range R, = 3085 A[l5]. Note that R, represents the distance from the Si-SiOZ interface. Kurtz and Yee’s diffusion experiments with low boron concentrations in Si gave D = 1.8 x IO-l4 cm’jsec at 1000°C. in agreement with Wagner’s experiments on shallow boron implants[l6,17]. This value of D gives c = 2425 A. These theoretical values of R,, and (T agree with those obtained from measured doping profiles. The calculated capacitances, corresponding to the experimental values of V, are given by the circles in Fig. 3 indicating excellent agreement between theory and experiment. To allow for charge in the oxide and metal-semiconductor work function difference, all the calculated curves underwent the same shift along the voltage axis such that the VD = -4.0 V curves matched in the transition region between punch-through and depletion. Equally good agreement between calculated and measured C&-V, curves was obtained for a MOSFET subjected to a 30min heat treatment at 900°C. Also in this case, the acceptor profile was described by eqn (6) with u = 1000 A corresponding to D = 8.46 x IO- Is cm’/sec. The agreement was somewhat poorer for the sample subjected to a 4 hr heat treatment at 1100°C. since the acceptor doping is no longer Gaussian and could not be estimated near the Si-SiO, interface. The salient features of the CG-V, curves were discussed by Mohsen and Morris[ 11. For sake of completeness, the capacitance behavior will be briefly discussed in terms of Figs. 1 and 3. For large positive Vc, electrons flow laterally from the n-type Si substrate to the Si-SiOZ interface under the gate; the device is in accumulation, and no mobile charge is present in the buried channel. (In our terminology the term accumulation is referenced with respect to the substrate rather than the implanted p-type layer.) As VG decreases from large positive bias, electrons leave the Si-SiOZ interface and the capacitance drops rapidly to a low value. For sufficiently large VD still no mobile charge is in the channel, and the device is in punch-through as shown in Fig. 3. The channel resistance is very high and the diodes are isolated from the channel. A further decrease in V, causes the depletion region in the bulk Si to expand. Eventually, the channel potential becomes comparable to V, such that the Fermi level in the p+ drain is within a few tenths of a volt from the valence band edge in the channel as shown in Fig. 1. At this point charge flows into the channel and the capacitance increases rapidly. Now a reversed-biased p-n junction exists under the gate area, the reverse-bias being V, and the p-n junction no longer contributes to the differential gate capacitance. In effect, the channel is shortened to the substrate via the source and drain. A further decrease in VG causes the depletion layer be-
tween the interface and the channel to shrink and the capacitance increases. The capacitance continues to increase as VG becomes more negative until eventually holes build up at the interface (inversion with respect to substrate) and the capacitance levels off at C,,. The gate oxide thickness can then be obtained since r<,,= l,,A/C,,. The accumulation, punch-through, depletion. and inversion regime are indicated in Fig. 3 for V, = - 10.0 v. AS shown in Fig. 3, punch-through is never reached for the lower values of V, Also, when punch-through is reached, the channel is deeper in the Si for the lower values of V,. This implies that acceptor doping profile measurements, from C&-V, data in the depletion region, can be obtained over larger distances. This is particularly important for low-implant doses. 4. DOPING PROFTLE.5AND DECUSSlON
4.1. Background and procedure Impurity doping can be obtained from CG-Vc; measurements in the depletion region. Using the abrupt space-charge or depletion approximation, the acceptor impurity doping profile is given by d(llC,*) N,(x)=& r 6 [ G
1
-’ + N
’
Ih
(7)
(8)
represents the distance from the Si-SiOZ interface. The limitations of eqns (7) and (8) gave been discussed by a number of authors[5-91. These studies deal with onesided p-n junctions, Schottky barriers or MOS capacitors with nonuniform dopant distribution but dopant species being of the same type. In thermal equilibrium. a nonuniform dopant distribution implies a spatially varying majority carrier density, which, in general, will not be equal to the dopant density. The majority carrier density is determined by the electrostatic potential, which, in equilibrium, is such that no net current flows. That is. a space charge is established wherein the majority carrier drift and diffusion currents exactly cancel. Kennedy, Murley and Kleinfelder assumed that eqns (7) and (8) give the majority carrier distribution rather than the doping distribution[5]. With this assumption they gave a correction formula to recover the impurity doping profile from the carrier measured majority distribution[6]. The underlying assumption in their work corresponds to a screening length (Debye length) of majority carriers equal to zero. Numerical studies by Johnson and Panousis with n+-n junctions using stepped and ramped profiles showed that eqns (7) and (8) give neither the doping profile nor the majority carrier distribution[7]. In fact, they conclude that the Debye length imposes the limit of spatial resolution for impurity doping profiles obtained by the C-V method. Wu. Douglas and Mueller reached the same conclusion[8]. In their work special attention was given to n-type impurity
Capacitance and doping profiles of ion-implanted, buried-channel MOSFETs
profiles implanted in the n-type substrate of a Schottky barrier. In this paper, we examine the Co-V, profiling method in ion-implanted, buried-channel MOSFETs. We have examined ion-implanted profiles with varying amounts of heat treatment. Experimentally, the impurity profile is obtained by applying eqns (7) and (8) to the measured Cc-VG curve. Calculated profiles were obtained by means of the following procedure. First, a doping profile is assumed based on C,-V, measurements and fabrication conditions. Then the C,-V, curve is calculated. Finally, the apparent profile is obtained from the calculated C,- V, curve by means of eqns (7) and (8) and is compared to the assumed profile. Significant differences between apparent and assumed profile indicate where the experimental procedure fails.
51
eqns (7) and (8) is about 10% too low relative to the implanted dose. Also, it is noted that No was chosen 10% lower than the implanted dose of 8 x lO”/cm* in order for curves A and C to coincide at the peak. It is tempting to conclude that the implanted dose is 90% electrically active. However, the actual profile is not known with sufficient accuracy to warrant this conclusion. Curves A in Fig. 5 and 6 give the measured profiles for devices subjected to 4hr heat treatment at 1000°C and 1100°C.respectively. Curve A in Fig. 5 (looo”C heat treatment) is well described by a Gaussian profile with U= 2425A, R,, =3085A and No= 8x lO”/cm* as discussed in Section 3.2. The measured doping profile for an implanted dose of 4 x lO”/cm* is also included (curve D). Curve A in Fig. 6 (1100°C heat treatment) is clearly not Gaussian and is similar to the boron impurity profile measured by SIMS[18]. For purposes of interpreting
4.2. Ion-implanted profiles-theory and experiment The measured impurity doping profile obtained for a MOSFET subjected to 30 min, 900°C heat treatment is given by curve A in Fig. 4. The Gaussian profile (curve B) given by eqn (6) with u = 1000A, R,, = 3400A and N, = 7.2 x 10”/cmZ is a reasonable approximation of the measured profile, particularly since the theoretical and measured Cc-VG curves are in good agreement. The calculated doping profile obtained from the calculated CG-VG curve is given by curve C in Fig. 4. Comparison of curves B and C gives the range over which the measured profile is valid. This comparison shows that the peak acceptor concentration obtained from Fig. 5. Impurity doping profile in Si for ion-implanted MOSFETs. Devices were subjected to heat treatment at IOOOYJ for 4 hr in N2 ambient. Curve A: measured doping profile Curve B: Gaussian acceptor profile with parameters No = 8 x IO”/cm*, R, = 3085A and u = 2425A. Curve C: Apparent doping profile corresponding to profile given by Curve B. Curves A, B and C correspond to an implanted boron dose of 8 x 10”/cm2. Curves A and C were obtained with V, = -4.0 V. Other measured parameters used in the C’G-Vc calculation are: ND = 4.5 x 10”/cm3, and I,, = 1120A. Curve D is the measured doping profile for an implanted dose of 4~ IO”/cm*. In this case V, = -0.25 V, ND = 4.5 x IO”/cm’ and t,. = 1075A.
Fig. 4. Impurity doping profile in Si obtained by means of the Cd-V, techniquefor a MOSFET implanted with 8 x IO” boron ions/cm* and annealed at 900°Cfor 30 min in N2 ambient. Curve A: Doping profile measured by means of eqns (7) and (8). Curve B: Gaussian acceptor profile characterized by No= 7.2 x 10”/cmz, R,, = 34008, and o = 1000A. Curve C: Apparent doping profile obtained from calculated Co-V, relation based on Curve B. Comparison of curves B and C gives the spatial region in the Si where the measured profile (Curve A) is valid. Curves A and C were obtained with V, = -4.0 V. Measured parameters used in the Co-V, calculation are: ND = 4.1 x lO”/cm’, and r,. = 108OA. Distances are measured relative to the Si-Si02 interface.
Fig. 6. Impurity doping profile in Si for MOSFET implanted with 8 x 10” boron ions/cm* and heat treated for 4 hr at IlOU’Cin N2 ambient. Curve A: Measured doping profile. Curve B: Acceptor protile given by eqn (9). Curve C: Apparent doping profile corresponding to profile given by Curve B. Profilingmethod is valid over the distance range indicated. Curves A and C were obtained with V, = -4.0 V. Measured parameters used in the C -Vo curve calculation: ND = 4.4 x IO”/cm’, r,, = 1125Ii
52
G. LUBBERTSand B. C. BURKEY
measured doping profiles the 1100°C profile was approximated by
1 .
NA(x)=
(2To
f
+
N,4Oh 0 <
x<%
D
Ni,,2exp [-(x~$‘)*], )
(9) x~R,
where NA(0)= 1.0 x 10’6/cm3, RP = 3100 A, (T= 4000 A and N0 = 8 x lO”/cm*. In both Figs. 5 and 6 the input profiles (curves B) are compared with the apparent profiles (curves C) to indicate the distance over which the doping profile can be obtained experimentally. It is clear from Figs. 4-6 that this profiling distance depends on the implantation and heat treatment conditions. In all cases the impurity doping profile is measured quite accurately on the left side of RP up to a distance of 1200-1800.&from the Si-SiOZ interface, depending on the annealing conditions. At this distance the measured and calculated profiles show an artificial upturn which results from a breakdown in the abrupt space-charge approximation. A similar effect occurs in MOS capacitors with uniformly doped substrates [19]. On the right side of R, the CG-Vc profiling method fails since a partially depleted channel is encountered. Both regions of failure will be discussed more quantitatively for a stepped impurity doping profile in Section 4.3. Another complication in obtaining doping profiles arises when interface states affect the CG-V, measurements. This problem has been discussed for conventional MOS capacitors [20]. Unlike the MOS capacitor, the buried-channel transistor is characterized by a Fermi level for holes as well as one for electrons. Our model shows that in the depletion and inversion regimes the electron Fermi level does not appear in the band gap at the interface for our p-channel devices. The hole Fermi level is more than 0.4eV above the valence band at the interface over the profiling range. Thus, the Si-SiOZ interface can be held in a nearly depleted state over the profiling distance, minimizing charge exchange with surface states. The small difference between theoretical and experimental Cc-VG curves near the inversion regime shown in Fig. 3 could be attributed to surface states. However, the difference is small and falls in a voltage region which is of no interest as far as profiling is concerned. In addition, we have observed a small hysteresis effect in the experimental CC-VG curves indicative of surface states. However, in agreement
with the above
comments
gate oxide thickness of the MOSFET was assumed to be 1120A and the substrate doping ND = 4.5 x lO%m’. The C,- Vc curve was calculated for three values of VD The stepped impurity doping profile and the apparent profiles are compared in Fig. 7. The Cc-V, profiling method accurately gives the acceptor density from roughly 0.1 to 0.3 Frn for V, = -2.0 V. Further reduction in VD does not improve the profile. For x >0.3 Km, the Cc-V, profiling method embodied in eqns (7) and (8) becomes inaccurate for two reasons. First, as shown in Fig. 8, the maximum hole density in this region is less than the net impurity doping density because of the existence of the p-n junction. Hence, the doping profile cannot be determined from Cc-V, measurements. The spatial region over which the channel is well formed and coincides with the p-n junction depletion region extends roughly from 0.3 to 0.35 Frn. Second, for x > 0.35 pm, the capacitance is in the transition region between punch-through and depletion, and is determined by both the gate-channel
Fig. 7. Illustration of limitation of Cc-V, profiling technique for ,MOSFET with stepped acceptor distribution superimposed on uniformly doped n-type Si substrate. Application of profiling method to the calculated Co-V, curve gives the apparent doping profile corresponding to three values of V, A correction is given by dotted curve for_Vo = - 2.0 V (see text). Parameters used in calculating the C,-V, curve are: NA(x)= 1.6x lO%ms for 0 < x < 0.5 pm, Nn(x) = 0 elsewhere, _Nr,= 4.5 x lO”/cm’ and t,, = ll20A. 1.0
A’
17-7
-3.ov
,i+s
i =-2.65V
this small hysteresis
in the transition region between depletion and inversion where the Cc-V, profiling method breaks down anyway.
effect
occurs
4.3. Stepped profile-calculation Another striking example of the limitation of the C,VG protiling method is provided by the stepped acceptor doping profile superimposed on a uniformly doped ntype substrate. We assume that N,+(x)= 1.6x 10’%m3 for O
Fig. 8. Calculated hole density in the Si as a function of distance from the Si-SiOt interface with V, = -2.0 V and V, as parameter. The calculations apply to the MOSFEITof Fig. 7. The flatband voltage V, = - 2.65V.
Capacitance and doping profiles of ion-implanted, buried-channel MOSFETs
This means that the actual distance, x’, where the doping is being measured is not equal to x given by eqn (8). A correction factor has been developed which relates x’ and x. Since Co = AQ/AVG,it can be shown that and the p-n junction capacitance.
y=x+xd
(1-a > (> AQ
x’=x+x,j
(W
Cd , CG
-
where xd is the total width of the space charge region when the channel forms; AQc and AQd are the incremental charges flowing into the channel and the bulk depletion region, respectively, such that AQ = AQc + AQd. The quantity Cd is the capacitance associated with the bulk depletion region and is equal to the punch-through capacitance before the channel forms and Cd vanishes rapidly when holes flow into the channel[l4]. Equations (1Oa) and (lob) were derived under the condition that x 4 xd which is the case for our MOSFFT, since xd = 3.55 pm when the channel forms. Equation (1Oa) is applicable for the computer calculations, while eqn (lob) can be applied to experimental capacitances. It must be borne in mind that eqns (10a) and (lob) are profile corrections that do not account for Debye length limitations associated with rapidly changing doping profiles. Applying eqn (10a) to the VD = -2.0 V profile results in the corrected profile given by the dotted curve in Fig. 7, The correction is negligible when the channel is fully formed; i.e. when the p-n junction no longer contributes to the differential capacitance, CG. However, the correction occurs in a region where the profile is incorrectly determined as a result of a partially depleted channel. Therefore the determination of this correction is of little interest. Similar conclusions are reached for the experimental, ion-implanted protiles. In the range 0 < x < 0.1 pm the CG-VG profiling method breaks down because the hole density near the Si-SiOZ interface can no longer be neglected in comparison to the doping density and thus the depletion approximation is no longer valid. This means that V. should be less than the flatband voltage. The profiling limitation near the Si-SiOZ interface can be more precisely formulated in terms of the Debye length given by A = [2~skT/q2(ivA-ivD)]“2.
(11)
At the flatband voltage the hole density is determined by
NA-ND and has a constant value of 1.55x 10”%m3 at the interface extending up to several thousand angstroms into the semiconductor. The corresponding Debye length A = 464 A. Theoretical considerations for constant doping have shown that the doping profile cannot be measured for O
53
buried-channel MOSFETs subjected to various heat treatments. The model has been used to examine the validity of the Co-V0 profiling method based on the abrupt space-charge approximation. The impurity doping profile was obtained in the implanted-channel region using the Co-VG profiling technique in the depletion regime. Comparison of the apparent doping profile, obtained from the theoretical CoV, curve, with the assumed profile establishes the distance over which the measured profile is valid. This requires that a reasonable estimate of the actual profile can be made. We conclude that within the limits of this work the ion-implanted profile can be measured quite accurately near the peak of the profile. However, the “tails” of the distribution cannot he measured with this technique. For the MOSFETs examined in this paper,
the method breaks down for distances closer than 120018OOAfrom the interface depending on the annealing conditions. On the other side of the peak the method fails since a partially depleted channel is present as a result of the formation of a p-n junction. The limitation of the Co-VG profiling method is further demonstrated for a MOSFET with a buried layer characterized by a stepped profile. The profiling method gives the correct impurity concentration in the central (spatial) portion of the stepped profile. Near the abrupt step in the profile the carrier density is less than the doping density and the profiling method fails. Theoretical considerations for MOS capacitors with uniformly doped substrates have shown that the C-V profiling method breaks down for distances closer than two Debye lengths from the oxide semiconductor interface, in agreement with our model calculations for the MOSFET having a buried layer with a stepped profile. We conclude that a model which adequately describes the C&V, characteristics of buried-channel MOSFETs is required to establish the range of validity of the Cc-V, profiling method. REYEIUXCES 1. A. M. Mohsen and F. J. Morris, Solid-St. Electron. 18, 407 (1975). 2. G. W. Taylor, Solid-St. Electron. 19, 495 (1976). 3. L. Gabler, B. Hoettlinger, J. Schneider and G. Zimmer, Electron. Lett., 12, 257 (1976). 4. M. G. Buehler, Appl. Phys. Lett., 31, 848 (1977). 5. D. P. Kennedy, P. C. Murley and W. Kleinfelder, IBM 1. Res. Deu., 399 (1968). 6. D. P. Kennedy and R. R. O’Brien, IBM .I. Res. Deu., 212
(1%9). 7. W. C. Johnson and R. T. Panousis, IEEE Trans. Electron Devices RD-18, %5 (1971). 8. C. P. Wu, E. C. Douglas and C. W. Mueller, IEEE Trans. Electron Devices ED-22, 319 (1975). 9. J. Verjans and R. J. Van Overstraeten, Solid-St. Electron. 18,
911 (1975). 10. K. Lehovec, Appl. Phys. Let. 26, 82 (1975). 11. J. S. Blakemore, Semiconductor Statistics, Appendix C.3. Pergamon Press, Oxford (1%2). 12. J. McKenna and M. L. Scbryer, Bell Sys. Tech. 1. 52, 669 (1973). 13. The calculation proceeds along similar lines as discussed in the Appendix of the paper: G. Lubber& B. C. Burkey, H. K. Biicber, and E. L. Wolf, J. Appl. Phys. 45.2180 (1974). 14. G. Lubberts, .I Appl. Phys., 48.5355 (1977). IS. J. F. Gibbons, W. S. Johnson and S. W. Mylroie, Projected
54
G. LUBBERTSand 8. C. BURKEY
Range Statistics, Semiconducrors and Related Materials. Dowden, Hutchinson and Ross, Inc., Stroudsburg, Pennsylvania (1975). 16. A. D. Kurtz and R. Yee, J. Appl. Phys. 31, 303 (1960). 17. S. Wagner, 3. Electrochem. Sot. 119, 1570 (1972). 18. W. K. Hofker, H. W. Werner, D. P. Oosthoek and H. A. M. de Grefte, in Ion-Implantation in Semiconductors and Other
Materials (Edited by B. L. Crowder), p. 133. Plenum Press, New York (1973). 19. K. Ziegler, E. Klausmann and S. Kar, Solid-S?. Electron. 18. 189 (1975). 20. E. H. Nicollian, M. H. Hanes and J. R. Brews, IEEE Trans. Electron Devices. ED-U), 380 (1973).
CAPACITANCE AND DOPING PROFILES OF ION-IMPLANTED, BURIED-CHANNEL MOSFETS G. LUBBERTS and B. C. BURKEY
Research Laboratories, Eastman Kodak Company, Rochester, NY 14650,U.S.A. (Received 26 November
1977; in revised form
31 March
1978)
Abstract-Detailed capacitance measurements are presented of large-area, ion-implanted, buried-channel MOSFETs. The gate capacitance was measured as a function of gate-substrate voltage with drain (source)-substrate voltage as parameter. The MOSFETswerepreparedon 10n-cm, n-type,(111)Si. Boronions with doses of 4 X 10” and 8 x 10”lcmawere implanted through the gate oxide to a depth of 0.30-0.35pm in the Si. The devices were subjected to heat treatments of 900-1100°C. Calculated capacitances based on a one-dimensional, partial-ionization model are in good agreement with experiment. The model is used to assess the validity of the C-V profiling technique based on the abrupt space-charge approximation. It is concluded that the impurity distribution can be measured quite accurately near the peak of the profile, for ion-implantation and heat-treatment conditions examined in this paper. However, the “tails” of the distribution cannot be measured with this technique. The limitations of the C-V profiling method are discussed quantitatively for a stepped profile
NOTATION
space-charge approximation and assuming a uniform, abrupt or stepped doping distribution[2]. In this paper we calculate the gate capacitance as a function of gatesubstrate voltage with drain (source)-substrate voltage as parameter for buried, p-channel, ion-implanted MOSFETs taking account of the electron and hole statistics. This procedure basically involves solving Poisson’s equation using Boltzmann statistics to describe the electrons in the conduction band and modified Fermi-Dirac statistics to describe the holes in the valence band. The theoretical capacitance data are compared with experimental results of boron implanted MOSFETs. Impurity doping profiles are usually obtained from C-V measurements using the abrupt space-charge or depletion approximation. Another method using the differential body effect has recently been proposed[3,4]. The C-V method is a nondestructive method of considerable interest because of its sensitivity and simplicity. Rapidly varying profiles, however, cannot usually be measured by this method. The limitations of the C-V method have been discussed by several authors[S-91. These studies deal with one-sided p-n junctions, n+-h junctions, Schottky barriers, and MOS capacitors with nonuniform semiconductor doping, the doping species being of the same type as that of the substrate. On the other hand, Lehovec has considered the impurity profile obtained from C-V data for a uniformly doped n-type epitaxial semiconductor layer sandwiched between a blocking metal contact and a uniformly doped semiinsulating p-type substrate[lO]. The data for this device show that the C-V profiling method becomes progressively better for the n-type epitaxial layer as NdN,, increases, but the measured impurity distribution becomes an artifact when the peak channel carrier concentration becomes less than No In this paper we consider the C-V profiling method for a related configuration consisting of an ion-implanted p-channel MOSFET, where the impurity profile depends on the implantation and annealing conditions. Our results
gate area gate capacitance CG C OX gate oxide capacitance 8 electric field EF Fermi energy Si band gap energy EG k Boltzmann’s constant acceptor impurity profile N*(x) ND donor impurity density NO implanted dose N” density of states in valence band magnitude of electronic charge R” projected range minus to, + temperature “K 1 gate oxide thickness vcm; electrostatic potential profile VD drain (source)-substrate voltage V gate-substrate voltage Y Debye length e0x permittivity of SiOs % permittivity of Si P(X) space-charge density ULl standard deviation of implanted boron D standard deviation after heat treatment Equationsare written in MKS units. A
1. lNTRODUCTION
In the last few years, capacitance measurements have been made on buried-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) as a tool for characterizing bulk-transfer charge-coupled devices [ 1,2]. In essence, these devices consist of a MOS structure with a shallow Si layer of doping opposite to that of the Si substrate and located between the oxide and the substrate. Since the structure of charge-coupled devices usually requires rather complex fabrication procedures, it is convenient to obtain important device parameters from buried-channel MOSFETs. The capacitance plays a prominent role in assessing device performance as shown by Mohsen and Morris[l]. As a first approximation, Taylor has calculated C-V curves for ion-implanted MOSFETs using the abrupt 47
48
G. LUBBERTS and B. C. BURKEY
indicate that the impurity distribution can be obtained near the peak of the doping distribution. However, the “tails” of the impurity distribution cannot be measured with this technique. 2. THEOmICALMODEL A one-dimensional model is appropriate for capacitance calculations of the buried-channel MOSFET. We consider a p-channel device with channel doping N,.Jx) formed on an n-type substrate with constant donor doping density ND The x-coordinate is perpendicular to the gate area of the MOSFET as shown in Fig. 1. The charge density and the corresponding band profile are shown schematically in Fig. 1 for a stepped acceptor profile. The drain and source are connected and biased negative relative to the substrate as shown in Fig. 2. The potential V(x) is assumed zero in the bulk Si. The upward direction of the single-ended arrows gives the positive direc-
tion for the electron potential energy and the direction of negative electrostatic potential energy. The electrostatic pote&l V(x) in the oxide (SiOJ and the semiconductor (Si) is given by Poisson’s equation - I”, < X < 0 x*0
(1)
where the charge density p is given by
P(X.VI = y [ NJ1 -exp (+qV/kT)] -
iVa(x)
(2) Equation (1) is subject to the boundary and continuity conditions V(m)= 0, V(- t,,) = v,.
(3)
V(O_)= V(O’), d V(O-) d V(O+) = 6s dx dx
Gx -
The symbols used in eqns (l)-(3) represent the following quantities. The voltage VO is the drain (source)-substrate voltage, VG the gate-substrate voltage, EC the Si bandgap, N, the density of valence band states, and EF the Fermi energy measured with respect to the conduction band edge in the bulk Si. Finally, eoXand l, are the low-frequency permittivities of SiOZand Si, respectively. Charge in the oxide, interface states, and metal-semiconductor work function difference were assumed equal Fig. 1. Schematic band protile and charge density for a buriedchannel MOSFET in the direction perpendicular to the gate area. to zero. The term ND exp (qV/kT) in eqn (2) represents the electron concentration in the conduction band. This The substrate donor concentration is uniform throughout the Si expression becomes inaccurate for large positive V, crystal, and the acceptor profile is a stepped protile as illustrated. The gate-substrate voltage, V,, and the drain-substratevoltage, when electrons build up at the Si-SiOZ interface. V, are chosen such that holes are present in the buried channel. However, this region is of little interest in this work. The The potential energy is assumed zero at the conduction band last term in eqn (2) describes the hole density in the (03) edge in the bulk Si. For simplicity, charge in the oxide and valence band. This form is suitable for both nondemetal-semiconductor work function difference are assumed equal to zero. generate and partial degenerate occupancy [ll]. For our work this simplification resulted in less than 1% error for the hole density as determined by the Fermi-Dirac integral [ 11). Since an analytic solution of eqn (1) is not possible, a numerical solution was obtained by means of the finite difference approach with over-relaxation[ 121. The x-coordinate is divided into 80-100 mesh points. The variable mesh spacing is approximately 200 A in the oxide, 10 A near the Si-Si02 boundary, 250A in the channel which extends to approximately 5OOOAbelow the Si-SiOZ interface, and 1OOOAbeyond the channel region. The resulting nonlinear finite difference equation Bt each mesh point is linearized using the Newton-Raphson method, and the set of equations is solved iteratively Fig. 2. Experimental setup for capacitance measurements of using successive over-relaxation. buried-channel MOSFETs. The capacitance data presented in this paper are obtained with points A and B connected. A 45 mV The finite difference scheme requires that the initial peak-to-peak signal of ld Hz frequency is superimposed on the potential profile is close to the actual potential, otherwise slowly varying (linear ramp) gate-substrate voltage Vo. The calicomputer overflows can occur as a result of large brated output of the lock-in amplifier gives the capacitance. exponential factors. The initial potential is obtained by Points A and D are connected when the substrate doping is assuming complete ionization; i.e. p(x) = q[No - N&)] measured as discussed in Ref. [ 141.
Capacitanceand dopingprofilesof ion-implanted,buried-channelMOSFETs corresponding to the punch-through region of the capacitance-voltage curve (see Section 3.2), with a Gaussian channel doping judiciously chosen to apl proximate N,&)[13]. The lirst two potential profiles are thus obtained for a VG in punch-through, and subsequent profiles.for the desired channel doping are obtained at 50 mV increments in V, using the preceding two potential profiles. Iterations for each profile calculation continue until the maximum change in potential between successive iterations is less than 2.5 pV. When the potential profile calculations are completed, the gate capacitance, which is defined as
can be found from the change in electric field, 8, at x = - r,, resulting from the 50 mV step in VG. The quantity A represents the active gate area. Approximately 4min of computation on an IBM 370/158 computer is required to generate a capacitance curve over a 1OV range in VG. All calculations in this paper are for T = N, = 1.138x 10’9/cm3, lox= 3OO”K, Eo=l.leV, 3.453x IO-” and 4 = 1.036x IO-“’ F/m. For lO&cm, ntype Si, EF = -0.28 eV.
3. M-AL
TECHNIQIJFS AND RESULTS
3.1. Device fabrication and measuring &rcuitry MOSFETs were fabricated on (111) n-type Si of 10acm (215%) resistivity. The buried layer was obtained by implanting 150keV boron ions (“B+) into the Si through the gate oxide. Doses of 4X 10” and 8X 10”/cm2 were used in these experiments. The implantation was done in a “random direction” by tilting the wafers 7” toward the ion beam. After implantation the devices were annealed at 900°C for 30 min. 1000°Cfor 4 hr, and 1lOOYZfor 4 hr in Nz ambient. This step was followed by Al metallization and sintering. The distance between source and drain, L, is 530 Frn, and the width, W, oi the gate oxide is 2540pm, corresponding to A = 1.346x lo-* cm*. Such large area MOSFETs are desirable for accurate capacitance measurements, in particular when the substrate doping is obtained from deep depletion (punch-through) capacitance measurements [ 141. The circuitry for capacitance measurements is shown in Fig. 2. The p+ source and drain are connected and reversed biased with respect to the substrate. The channel-substrate voltage is externally controlled through the p+ source and drain contacts. A 45 mV peak-to-peak modulating voltage of lo3 Hz frequency is superimposed on the slowly varying (linear ramp) dc gate-substrate voltage, VG, and causes a displacement current which develops a voltage across Rr. This ac voltage is detected by a lock-in amplifier tuned to the same frequency. The calibrated output of the lock-in amplifier then gives the capacitance. Feeding the output of the lock-in amplifier into a function module gives l/CO’, and with a simple differentiating circuit, the time derivative d(l/C,*)/dt, is obtained. Since SSE Vd. 22. No. I-D
49
(5) and d VJdt is constant in our experiments, d( l/C,*)/d V, and the doping profile are measured directly (Section 4.1). The capacitance data discussed in this paper are obtained by connecting points A and B in Fig. 2. Parasitic and gate-source and gate-drain overlap capacitances are subtracted from the measurements using the d.c. zero offset voltage on the lock-in amplifier. (The overlap capacitances are determined with the device in the punch-through condition, by grounding the substrate and connecting Rr between ground and the positive terminal of the source and drain voltage supply.) Points A and D in Fig. 2 are connected for substrate doping measurement as discussed in a previous paper[l4]. The gate capacitance is generally frequency dependent as a result of distributed RC effects in the device[l]. Our measurements’ and calculations indicate that 103Hz is sufficiently low for capacitance measurements in agreement with Mohsen and Morris[l:. All LkAbUrements were made at room temperature. 3.2. Capacitance data and calculations The measured gate capacitance, Cc, as a function of gate-substrate voltage, V,, is shown in Fig. 3. For each curve, the drain (source)-substrate voltage, VD, is fixed. The MOSFET was implanted with a dose, N,, of 8 x 10” boron ions/cm* and annealed at 1ooo”Cfor 4hr. Under these conditions the G--V, curve was also calculated using the method of Section 2. The acceptor doping density in eqn (2) is given by (6) The parameters used in the calculation are R, =
Fig. 3. Gate capacitance, Co, as a function of gate-substrate voltage, V,, for various dram-substratevoltages, V, The MOSFET was implanted with 8X 10” boron ions/cm2 of 150keV energy.The device was heat treatedat Iooo”Cfor 4 hr in N2 ambient. Measuredcapacitancesare given by the solid line; calculated values are indicated by the circles. A Gaussian acceptor profilewas used in the calculationwith & = 8 x IO”/cm*, R, = %@S A,and u = 2425 A (see text). Other rei&ant measured parameters used in the Co-V, curve calculation are ND = 4.5 x ~o”/cn?, and r‘,x=1120A.
50
G. LUBBERTSand B. C. BURKEY
3085 A, u = 2425 A, N, = 8 x lO”/cm’, N,= 4.5 x 101“/cm3, and the gate oxide thickness. t,, = 1120 A. The standard deviation, LT.was obtained by assuming that the Gaussian profile spreads as (T= (oO’ + 2Dt)“* during heat treatment, where D is the diffusion constant, t is the duration of heat treatment, and oh is the standard deviation prior to heat treatment. Since the range statistics of a 150 keV “B’ beam are about the same in Si and SiOZ, we find from LSS tables that crO= 834 A and the projected range R, = 3085 A[l5]. Note that R, represents the distance from the Si-SiOZ interface. Kurtz and Yee’s diffusion experiments with low boron concentrations in Si gave D = 1.8 x IO-l4 cm’jsec at 1000°C. in agreement with Wagner’s experiments on shallow boron implants[l6,17]. This value of D gives c = 2425 A. These theoretical values of R,, and (T agree with those obtained from measured doping profiles. The calculated capacitances, corresponding to the experimental values of V, are given by the circles in Fig. 3 indicating excellent agreement between theory and experiment. To allow for charge in the oxide and metal-semiconductor work function difference, all the calculated curves underwent the same shift along the voltage axis such that the VD = -4.0 V curves matched in the transition region between punch-through and depletion. Equally good agreement between calculated and measured C&-V, curves was obtained for a MOSFET subjected to a 30min heat treatment at 900°C. Also in this case, the acceptor profile was described by eqn (6) with u = 1000 A corresponding to D = 8.46 x IO- Is cm’/sec. The agreement was somewhat poorer for the sample subjected to a 4 hr heat treatment at 1100°C. since the acceptor doping is no longer Gaussian and could not be estimated near the Si-SiO, interface. The salient features of the CG-V, curves were discussed by Mohsen and Morris[ 11. For sake of completeness, the capacitance behavior will be briefly discussed in terms of Figs. 1 and 3. For large positive Vc, electrons flow laterally from the n-type Si substrate to the Si-SiOZ interface under the gate; the device is in accumulation, and no mobile charge is present in the buried channel. (In our terminology the term accumulation is referenced with respect to the substrate rather than the implanted p-type layer.) As VG decreases from large positive bias, electrons leave the Si-SiOZ interface and the capacitance drops rapidly to a low value. For sufficiently large VD still no mobile charge is in the channel, and the device is in punch-through as shown in Fig. 3. The channel resistance is very high and the diodes are isolated from the channel. A further decrease in V, causes the depletion region in the bulk Si to expand. Eventually, the channel potential becomes comparable to V, such that the Fermi level in the p+ drain is within a few tenths of a volt from the valence band edge in the channel as shown in Fig. 1. At this point charge flows into the channel and the capacitance increases rapidly. Now a reversed-biased p-n junction exists under the gate area, the reverse-bias being V, and the p-n junction no longer contributes to the differential gate capacitance. In effect, the channel is shortened to the substrate via the source and drain. A further decrease in VG causes the depletion layer be-
tween the interface and the channel to shrink and the capacitance increases. The capacitance continues to increase as VG becomes more negative until eventually holes build up at the interface (inversion with respect to substrate) and the capacitance levels off at C,,. The gate oxide thickness can then be obtained since r<,,= l,,A/C,,. The accumulation, punch-through, depletion. and inversion regime are indicated in Fig. 3 for V, = - 10.0 v. AS shown in Fig. 3, punch-through is never reached for the lower values of V, Also, when punch-through is reached, the channel is deeper in the Si for the lower values of V,. This implies that acceptor doping profile measurements, from C&-V, data in the depletion region, can be obtained over larger distances. This is particularly important for low-implant doses. 4. DOPING PROFTLE.5AND DECUSSlON
4.1. Background and procedure Impurity doping can be obtained from CG-Vc; measurements in the depletion region. Using the abrupt space-charge or depletion approximation, the acceptor impurity doping profile is given by d(llC,*) N,(x)=& r 6 [ G
1
-’ + N
’
Ih
(7)
(8)
represents the distance from the Si-SiOZ interface. The limitations of eqns (7) and (8) gave been discussed by a number of authors[5-91. These studies deal with onesided p-n junctions, Schottky barriers or MOS capacitors with nonuniform dopant distribution but dopant species being of the same type. In thermal equilibrium. a nonuniform dopant distribution implies a spatially varying majority carrier density, which, in general, will not be equal to the dopant density. The majority carrier density is determined by the electrostatic potential, which, in equilibrium, is such that no net current flows. That is. a space charge is established wherein the majority carrier drift and diffusion currents exactly cancel. Kennedy, Murley and Kleinfelder assumed that eqns (7) and (8) give the majority carrier distribution rather than the doping distribution[5]. With this assumption they gave a correction formula to recover the impurity doping profile from the carrier measured majority distribution[6]. The underlying assumption in their work corresponds to a screening length (Debye length) of majority carriers equal to zero. Numerical studies by Johnson and Panousis with n+-n junctions using stepped and ramped profiles showed that eqns (7) and (8) give neither the doping profile nor the majority carrier distribution[7]. In fact, they conclude that the Debye length imposes the limit of spatial resolution for impurity doping profiles obtained by the C-V method. Wu. Douglas and Mueller reached the same conclusion[8]. In their work special attention was given to n-type impurity
Capacitance and doping profiles of ion-implanted, buried-channel MOSFETs
profiles implanted in the n-type substrate of a Schottky barrier. In this paper, we examine the Co-V, profiling method in ion-implanted, buried-channel MOSFETs. We have examined ion-implanted profiles with varying amounts of heat treatment. Experimentally, the impurity profile is obtained by applying eqns (7) and (8) to the measured Cc-VG curve. Calculated profiles were obtained by means of the following procedure. First, a doping profile is assumed based on C,-V, measurements and fabrication conditions. Then the C,-V, curve is calculated. Finally, the apparent profile is obtained from the calculated C,- V, curve by means of eqns (7) and (8) and is compared to the assumed profile. Significant differences between apparent and assumed profile indicate where the experimental procedure fails.
51
eqns (7) and (8) is about 10% too low relative to the implanted dose. Also, it is noted that No was chosen 10% lower than the implanted dose of 8 x lO”/cm* in order for curves A and C to coincide at the peak. It is tempting to conclude that the implanted dose is 90% electrically active. However, the actual profile is not known with sufficient accuracy to warrant this conclusion. Curves A in Fig. 5 and 6 give the measured profiles for devices subjected to 4hr heat treatment at 1000°C and 1100°C.respectively. Curve A in Fig. 5 (looo”C heat treatment) is well described by a Gaussian profile with U= 2425A, R,, =3085A and No= 8x lO”/cm* as discussed in Section 3.2. The measured doping profile for an implanted dose of 4 x lO”/cm* is also included (curve D). Curve A in Fig. 6 (1100°C heat treatment) is clearly not Gaussian and is similar to the boron impurity profile measured by SIMS[18]. For purposes of interpreting
4.2. Ion-implanted profiles-theory and experiment The measured impurity doping profile obtained for a MOSFET subjected to 30 min, 900°C heat treatment is given by curve A in Fig. 4. The Gaussian profile (curve B) given by eqn (6) with u = 1000A, R,, = 3400A and N, = 7.2 x 10”/cmZ is a reasonable approximation of the measured profile, particularly since the theoretical and measured Cc-VG curves are in good agreement. The calculated doping profile obtained from the calculated CG-VG curve is given by curve C in Fig. 4. Comparison of curves B and C gives the range over which the measured profile is valid. This comparison shows that the peak acceptor concentration obtained from Fig. 5. Impurity doping profile in Si for ion-implanted MOSFETs. Devices were subjected to heat treatment at IOOOYJ for 4 hr in N2 ambient. Curve A: measured doping profile Curve B: Gaussian acceptor profile with parameters No = 8 x IO”/cm*, R, = 3085A and u = 2425A. Curve C: Apparent doping profile corresponding to profile given by Curve B. Curves A, B and C correspond to an implanted boron dose of 8 x 10”/cm2. Curves A and C were obtained with V, = -4.0 V. Other measured parameters used in the C’G-Vc calculation are: ND = 4.5 x 10”/cm3, and I,, = 1120A. Curve D is the measured doping profile for an implanted dose of 4~ IO”/cm*. In this case V, = -0.25 V, ND = 4.5 x IO”/cm’ and t,. = 1075A.
Fig. 4. Impurity doping profile in Si obtained by means of the Cd-V, techniquefor a MOSFET implanted with 8 x IO” boron ions/cm* and annealed at 900°Cfor 30 min in N2 ambient. Curve A: Doping profile measured by means of eqns (7) and (8). Curve B: Gaussian acceptor profile characterized by No= 7.2 x 10”/cmz, R,, = 34008, and o = 1000A. Curve C: Apparent doping profile obtained from calculated Co-V, relation based on Curve B. Comparison of curves B and C gives the spatial region in the Si where the measured profile (Curve A) is valid. Curves A and C were obtained with V, = -4.0 V. Measured parameters used in the Co-V, calculation are: ND = 4.1 x lO”/cm’, and r,. = 108OA. Distances are measured relative to the Si-Si02 interface.
Fig. 6. Impurity doping profile in Si for MOSFET implanted with 8 x 10” boron ions/cm* and heat treated for 4 hr at IlOU’Cin N2 ambient. Curve A: Measured doping profile. Curve B: Acceptor protile given by eqn (9). Curve C: Apparent doping profile corresponding to profile given by Curve B. Profilingmethod is valid over the distance range indicated. Curves A and C were obtained with V, = -4.0 V. Measured parameters used in the C -Vo curve calculation: ND = 4.4 x IO”/cm’, r,, = 1125Ii
52
G. LUBBERTSand B. C. BURKEY
measured doping profiles the 1100°C profile was approximated by
1 .
NA(x)=
(2To
f
+
N,4Oh 0 <
x<%
D
Ni,,2exp [-(x~$‘)*], )
(9) x~R,
where NA(0)= 1.0 x 10’6/cm3, RP = 3100 A, (T= 4000 A and N0 = 8 x lO”/cm*. In both Figs. 5 and 6 the input profiles (curves B) are compared with the apparent profiles (curves C) to indicate the distance over which the doping profile can be obtained experimentally. It is clear from Figs. 4-6 that this profiling distance depends on the implantation and heat treatment conditions. In all cases the impurity doping profile is measured quite accurately on the left side of RP up to a distance of 1200-1800.&from the Si-SiOZ interface, depending on the annealing conditions. At this distance the measured and calculated profiles show an artificial upturn which results from a breakdown in the abrupt space-charge approximation. A similar effect occurs in MOS capacitors with uniformly doped substrates [19]. On the right side of R, the CG-Vc profiling method fails since a partially depleted channel is encountered. Both regions of failure will be discussed more quantitatively for a stepped impurity doping profile in Section 4.3. Another complication in obtaining doping profiles arises when interface states affect the CG-V, measurements. This problem has been discussed for conventional MOS capacitors [20]. Unlike the MOS capacitor, the buried-channel transistor is characterized by a Fermi level for holes as well as one for electrons. Our model shows that in the depletion and inversion regimes the electron Fermi level does not appear in the band gap at the interface for our p-channel devices. The hole Fermi level is more than 0.4eV above the valence band at the interface over the profiling range. Thus, the Si-SiOZ interface can be held in a nearly depleted state over the profiling distance, minimizing charge exchange with surface states. The small difference between theoretical and experimental Cc-VG curves near the inversion regime shown in Fig. 3 could be attributed to surface states. However, the difference is small and falls in a voltage region which is of no interest as far as profiling is concerned. In addition, we have observed a small hysteresis effect in the experimental CC-VG curves indicative of surface states. However, in agreement
with the above
comments
gate oxide thickness of the MOSFET was assumed to be 1120A and the substrate doping ND = 4.5 x lO%m’. The C,- Vc curve was calculated for three values of VD The stepped impurity doping profile and the apparent profiles are compared in Fig. 7. The Cc-V, profiling method accurately gives the acceptor density from roughly 0.1 to 0.3 Frn for V, = -2.0 V. Further reduction in VD does not improve the profile. For x >0.3 Km, the Cc-V, profiling method embodied in eqns (7) and (8) becomes inaccurate for two reasons. First, as shown in Fig. 8, the maximum hole density in this region is less than the net impurity doping density because of the existence of the p-n junction. Hence, the doping profile cannot be determined from Cc-V, measurements. The spatial region over which the channel is well formed and coincides with the p-n junction depletion region extends roughly from 0.3 to 0.35 Frn. Second, for x > 0.35 pm, the capacitance is in the transition region between punch-through and depletion, and is determined by both the gate-channel
Fig. 7. Illustration of limitation of Cc-V, profiling technique for ,MOSFET with stepped acceptor distribution superimposed on uniformly doped n-type Si substrate. Application of profiling method to the calculated Co-V, curve gives the apparent doping profile corresponding to three values of V, A correction is given by dotted curve for_Vo = - 2.0 V (see text). Parameters used in calculating the C,-V, curve are: NA(x)= 1.6x lO%ms for 0 < x < 0.5 pm, Nn(x) = 0 elsewhere, _Nr,= 4.5 x lO”/cm’ and t,, = ll20A. 1.0
A’
17-7
-3.ov
,i+s
i =-2.65V
this small hysteresis
in the transition region between depletion and inversion where the Cc-V, profiling method breaks down anyway.
effect
occurs
4.3. Stepped profile-calculation Another striking example of the limitation of the C,VG protiling method is provided by the stepped acceptor doping profile superimposed on a uniformly doped ntype substrate. We assume that N,+(x)= 1.6x 10’%m3 for O
Fig. 8. Calculated hole density in the Si as a function of distance from the Si-SiOt interface with V, = -2.0 V and V, as parameter. The calculations apply to the MOSFEITof Fig. 7. The flatband voltage V, = - 2.65V.
Capacitance and doping profiles of ion-implanted, buried-channel MOSFETs
This means that the actual distance, x’, where the doping is being measured is not equal to x given by eqn (8). A correction factor has been developed which relates x’ and x. Since Co = AQ/AVG,it can be shown that and the p-n junction capacitance.
y=x+xd
(1-a > (> AQ
x’=x+x,j
(W
Cd , CG
-
where xd is the total width of the space charge region when the channel forms; AQc and AQd are the incremental charges flowing into the channel and the bulk depletion region, respectively, such that AQ = AQc + AQd. The quantity Cd is the capacitance associated with the bulk depletion region and is equal to the punch-through capacitance before the channel forms and Cd vanishes rapidly when holes flow into the channel[l4]. Equations (1Oa) and (lob) were derived under the condition that x 4 xd which is the case for our MOSFFT, since xd = 3.55 pm when the channel forms. Equation (1Oa) is applicable for the computer calculations, while eqn (lob) can be applied to experimental capacitances. It must be borne in mind that eqns (10a) and (lob) are profile corrections that do not account for Debye length limitations associated with rapidly changing doping profiles. Applying eqn (10a) to the VD = -2.0 V profile results in the corrected profile given by the dotted curve in Fig. 7, The correction is negligible when the channel is fully formed; i.e. when the p-n junction no longer contributes to the differential capacitance, CG. However, the correction occurs in a region where the profile is incorrectly determined as a result of a partially depleted channel. Therefore the determination of this correction is of little interest. Similar conclusions are reached for the experimental, ion-implanted protiles. In the range 0 < x < 0.1 pm the CG-VG profiling method breaks down because the hole density near the Si-SiOZ interface can no longer be neglected in comparison to the doping density and thus the depletion approximation is no longer valid. This means that V. should be less than the flatband voltage. The profiling limitation near the Si-SiOZ interface can be more precisely formulated in terms of the Debye length given by A = [2~skT/q2(ivA-ivD)]“2.
(11)
At the flatband voltage the hole density is determined by
NA-ND and has a constant value of 1.55x 10”%m3 at the interface extending up to several thousand angstroms into the semiconductor. The corresponding Debye length A = 464 A. Theoretical considerations for constant doping have shown that the doping profile cannot be measured for O
53
buried-channel MOSFETs subjected to various heat treatments. The model has been used to examine the validity of the Co-V0 profiling method based on the abrupt space-charge approximation. The impurity doping profile was obtained in the implanted-channel region using the Co-VG profiling technique in the depletion regime. Comparison of the apparent doping profile, obtained from the theoretical CoV, curve, with the assumed profile establishes the distance over which the measured profile is valid. This requires that a reasonable estimate of the actual profile can be made. We conclude that within the limits of this work the ion-implanted profile can be measured quite accurately near the peak of the profile. However, the “tails” of the distribution cannot he measured with this technique. For the MOSFETs examined in this paper,
the method breaks down for distances closer than 120018OOAfrom the interface depending on the annealing conditions. On the other side of the peak the method fails since a partially depleted channel is present as a result of the formation of a p-n junction. The limitation of the Co-VG profiling method is further demonstrated for a MOSFET with a buried layer characterized by a stepped profile. The profiling method gives the correct impurity concentration in the central (spatial) portion of the stepped profile. Near the abrupt step in the profile the carrier density is less than the doping density and the profiling method fails. Theoretical considerations for MOS capacitors with uniformly doped substrates have shown that the C-V profiling method breaks down for distances closer than two Debye lengths from the oxide semiconductor interface, in agreement with our model calculations for the MOSFET having a buried layer with a stepped profile. We conclude that a model which adequately describes the C&V, characteristics of buried-channel MOSFETs is required to establish the range of validity of the Cc-V, profiling method. REYEIUXCES 1. A. M. Mohsen and F. J. Morris, Solid-St. Electron. 18, 407 (1975). 2. G. W. Taylor, Solid-St. Electron. 19, 495 (1976). 3. L. Gabler, B. Hoettlinger, J. Schneider and G. Zimmer, Electron. Lett., 12, 257 (1976). 4. M. G. Buehler, Appl. Phys. Lett., 31, 848 (1977). 5. D. P. Kennedy, P. C. Murley and W. Kleinfelder, IBM 1. Res. Deu., 399 (1968). 6. D. P. Kennedy and R. R. O’Brien, IBM .I. Res. Deu., 212
(1%9). 7. W. C. Johnson and R. T. Panousis, IEEE Trans. Electron Devices RD-18, %5 (1971). 8. C. P. Wu, E. C. Douglas and C. W. Mueller, IEEE Trans. Electron Devices ED-22, 319 (1975). 9. J. Verjans and R. J. Van Overstraeten, Solid-St. Electron. 18,
911 (1975). 10. K. Lehovec, Appl. Phys. Let. 26, 82 (1975). 11. J. S. Blakemore, Semiconductor Statistics, Appendix C.3. Pergamon Press, Oxford (1%2). 12. J. McKenna and M. L. Scbryer, Bell Sys. Tech. 1. 52, 669 (1973). 13. The calculation proceeds along similar lines as discussed in the Appendix of the paper: G. Lubber& B. C. Burkey, H. K. Biicber, and E. L. Wolf, J. Appl. Phys. 45.2180 (1974). 14. G. Lubberts, .I Appl. Phys., 48.5355 (1977). IS. J. F. Gibbons, W. S. Johnson and S. W. Mylroie, Projected
54
G. LUBBERTSand 8. C. BURKEY
Range Statistics, Semiconducrors and Related Materials. Dowden, Hutchinson and Ross, Inc., Stroudsburg, Pennsylvania (1975). 16. A. D. Kurtz and R. Yee, J. Appl. Phys. 31, 303 (1960). 17. S. Wagner, 3. Electrochem. Sot. 119, 1570 (1972). 18. W. K. Hofker, H. W. Werner, D. P. Oosthoek and H. A. M. de Grefte, in Ion-Implantation in Semiconductors and Other
Materials (Edited by B. L. Crowder), p. 133. Plenum Press, New York (1973). 19. K. Ziegler, E. Klausmann and S. Kar, Solid-S?. Electron. 18. 189 (1975). 20. E. H. Nicollian, M. H. Hanes and J. R. Brews, IEEE Trans. Electron Devices. ED-U), 380 (1973).