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Capacitance modeling of short-channel double-gate MOSFETs
Solid-State Electronics 52 (2008) 1486–1490
Contents lists available at ScienceDirect
Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
Capacitance modeling of short-channel double-gate MOSFETs Håkon Børli *, Sigbjørn Kolberg, Tor A. Fjeldly Department of Electronics and Telecommunications, Norwegian University of Science and Technology/University Graduate Center, P.O. Box 70, 2027 Kjeller, Norway
a r t i c l e
i n f o
Article history: Received 13 May 2008 Accepted 7 June 2008 Available online 25 July 2008 Review of this manuscript was arranged by A. Iliadis, C. Richter, and A. Zaslavsky Keywords: MOSFET Double-gate Nanoscale 2-D modeling Conformal mapping Capacitance
a b s t r a c t We present 2-D physics based modeling of short-channel double-gate MOSFETs of nanoscale dimensions. We have derived a precise, self-consistent framework model for the device electrostatics, the drain current, and the charge conserving capacitances, covering all regimes of device operation from subthreshold to strong inversion. The modeling has no adjustable parameters and implicitly incorporates scaling with device dimensions and material composition. The foundation of the 2-D modeling is an analytical description of the inter-electrode capacitive coupling between the four electrodes, based on conformal mapping techniques. The model is shown to be in excellent agreement with numerical simulations. Ó 2008 Elsevier Ltd. All rights reserved.
1. Introduction The double-gate (DG) MOSFET has been identified as one of the promising device structures for future nanoscale CMOS applications [1]. Precise analytical models for such devices are needed for circuit simulators and circuit design tools. So far, most of the modeling work done on DG MOSFETs has been concentrated on long-channel, undoped devices, where analytical solutions for the device electrostatics, drain current, and capacitances have been obtained based on a 1-D Poisson’s equation perpendicular to the gates [2–6]. For short-channel devices where the charge-sharing regions near source and drain are important, we are faced with a 2-D electrostatics problem, which previously was modeled using simplifying assumptions or by Fourier expansion [3,7–9]. As an alternative, we proposed a procedure where the inter-electrode capacitive coupling between the source, drain, and gates is considered separately as the solution of a 2-D Laplace equation for the device body potential. Using conformal mapping techniques [10], this leads to a precise analytical solution in terms of elliptic integrals [11–14]. This solution is dominant in subthreshold for low-doped, nanoscale devices.
* Corresponding author. E-mail addresses: [email protected] (H. Børli), [email protected] (S. Kolberg), [email protected] (T.A. Fjeldly). 0038-1101/$ - see front matter Ó 2008 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2008.06.022
Near and above threshold and in moderate inversion, where the contribution to the electrostatics from the inversion charge becomes comparable to that of the inter-electrode effect, a self-consistent solution of Poisson’s equation in combination with modeling expressions were used [14–17]. The modeling expressions are constrained by the boundary conditions imposed on the final solution. Moreover, for applied drain biases, the quasi-Fermi potential distribution and the drain current must also be incorporated in this self-consistent solution. In strong inversion, the carriers tend to screen the influence of the source and drain electrodes and the device acquires a long-channel behavior. For simplicity, the drain current was calculated using the driftdiffusion transport mechanism with constant mobility. This is justified since, fortuitously, numerical simulations indicate that the drain currents obtained for the nanoscale devices considered, agree very well with those obtained from more advanced simulations based on hydrodynamic and energy transport formalisms [16,17]. From the above modeling framework, we can also calculate the intrinsic device capacitances in all operating regimes. In subthreshold, the capacitances are dominated by the inter-electrode coupling, from which analytical expressions for the charge conserving trans- and self-capacitances can readily be derived using conformal mapping techniques. Near and above threshold, we obtain the total, vertical electric displacement field on the gate, source, and drain electrodes from the device electrostatics, from which the electrode charges and capacitances can be derived. The modeled capacitances are verified against numerical simulations. Since no fitting parameters are used, the capacitance model
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together with the corresponding drain current model is scalable over a wide range of geometric and material combinations. The specific device considered is shown in Fig. 1. It has a gate length of L = 25 nm, a silicon thickness of tsi = 12 nm, a p-type body doping of Na = 1015 cm3 and a high-k gate insulator with a relative permittivity of eox = 7 and a thickness of tox = 1.6 nm. To simplify the calculations we replace the insulator thickness tox by an electrostatically equivalent silicon layer of thickness t0 ox = toxesi/eox, where esi = 11.8 is the relative permittivity of silicon. Thereby we avoid dealing with internal interfaces when solving the 2-D Laplace equation in the extended device body bounded by the four electrodes. Idealized Schottky contacts with a work function of 4.17 eV (corresponding to that of n+ silicon) are assumed for the source and drain. This ensures equipotential surfaces on all device contacts. Metal gates with a mid-gap work function of 5.53 eV are assumed.
v
p
1
1
uL ðu0 ; 0Þ ðu u0 Þ2 þ v2
du0
ð2Þ
For a very thin gate insulator, the boundary potential distribution uL(u, 0) is only defined by the four equipotential electrodes, leading to the following analytical solution [14,18]:
1 ku 1 þ ku tan1 ðV gs2 V FB Þ p tan1 kv kv p 1 u 1 þ u þ ðV gs1 V FB Þ tan1 þ tan1 v v 1 ku 1 u tan1 þ V bi tan1 kv v 1 þ ku 1þu tan1 ð3Þ þðV bi þ V ds Þ tan1 kv v
uL ðu; vÞ ¼
1
where Vgs1 and Vgs2 are the gate-source potentials, Vds is the drainsource potential, VFB is the flat band voltage, and Vbi is the built-in voltage. In the following, we consider only symmetric gate biasing, i.e., Vgs1 = Vgs2.
2. Electrostatics 2.1. Inter-electrode coupling The basis for the present modeling of the DG MOSFET capacitances is the device body electrostatics discussed in Section 1. As indicated, the inter-electrode capacitive coupling can be determined analytically from Laplace’s equation using conformal mapping techniques. This maps the extended, rectangular device body in the (x, y)-plane (including the gate insulators, see Fig. 1) into the upper half of a transformed (u, v)-plane according to the appropriate Schwartz–Christoffel transformation [10,18]
oz 1 ¼ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ; ow 2 2 ð1 w Þð1 k w2 Þ
uL ðu; vÞ ¼
Z
or z ¼ x þ iy ¼
L Fðk; wÞ 2 KðkÞ
ð1Þ
Here, z = x + iy, w = u + iv, the modulus k is a geometric parameter between 0 and 1 determined from the extended device height/ width ratio, F(k,w) is the elliptic integral of the first kind, and K(k) = F(k,1) is the corresponding complete elliptic integral. We note that the boundary of the extended body in the (x, y)-plane maps onto the real u-axis in the (u, v)-plane, and that the four corners of the boundary map into u = ±1, ±1/k. In the (u, v)-plane, the potential distribution uL(u, v) throughout the body can be obtained from Laplace’s equation by performing the following integral along the entire boundary (u-axis):
2.2. Corner corrections For realistic gate insulator thicknesses, (3) is still a good approximation for most of the body interior, but tends to fail close to the four corners of the body. For the calculation of the drain current, this effect is minor and can be corrected by simple means [16]. However, for modeling the capacitances, a more accurate description of the boundary potential distribution across the insulator is needed. This can be obtained by considering a single corner as shown in Fig. 2a, where the boundary insulator gap is indicated as the heavy, dashed vertical line. The orthogonal field lines and equipotential lines near the corner are also shown. Assuming that all other dimensions are large compared to t0 ox, the potential distribution in this region can be modeled by performing a new conformal mapping defined by the following Schwartz–Christoffel transformation [10]
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi w1c 1 ; or z1c ¼ x1c þ iy1c w1c pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2t 0 ¼ ox f½ w1c 1 tan1 ð w1c 1Þ þ 1g
oz1c ¼ ow1c
p
ð4Þ
Here, the subscript 1c indicates that this is a one-corner transform. Again, performing the integral in (2), we find the following potential distribution in the (u1c, v1c)-plane,
1
1
uðu1c ; v1c Þ ¼ ðV gx V FB þ V bi Þ ðV gx V FB 2 p V bi Þtan1
u1c ; v1c
ð5Þ
where Vgx becomes Vgs for a source side corner or Vgd for a drain side corner. The equipotential lines are radials and the electric field lines are semicircles as shown in Fig. 2b. Mapping the potential distribution along the insulator part of the boundary back to the (x1c, y1c)-plane results in the profile shown in the inset of Fig. 2a. This distribution can be approximated quite well by the polynomial
uox ð0; y1c Þ ¼ ayn1c þ by1c þ V gs V FB
Fig. 1. Schematic view of the DG MOSFET cross-section.
ð6Þ
where a and b are parameters determined by the potentials at the drain or source contacts and from an arbitrary point inside the insulator using (5) in combination with (4). The parameter n is chosen for minimum deviation from the true potential profile in the insulator defined by (5). n = 6 appears to be a suitable choice. Since this
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Fig. 2. Equipotential lines and field lines from the one-corner analysis in the (x1c, y1c)-plane with inset showing the potential profile along the four-corner boundary through the insulator gap (a). Transformed fields and potentials in the (u1c, v1c)plane (b). The bold solid curve shows the field line emanating from the corner. The bold dashed curve shows the insulator part of the boundary through the insulator.
value is obtained from a consideration of the one-corner electrostatics, it will be invariant with respect to the device dimensions. Next, the distribution (6) is mapped into the four-corner (u, v)plane, this time using an expansion of the mapping function (1) valid for the vicinity of the corners. The resulting potential distribution along the insulator boundary in the (u, v)-plane then yields analytical correction terms to uL(u, v) when applied to the integral in (2). The corrected potential distribution in the (x, y)-plane is shown in Fig. 3a for Vgs = 0 V and Vds = 0.2 V. A comparison with numerical simulations for the source-to-drain (S–D) and the gate-to-gate (G–G) symmetry axes in Fig. 3b indicates a near-perfect match. Close to the corners, we find deviation on the millivolt level. These are attributed to the scaling of the insulator thickness, resulting from the brake-down of the assumption of a vertical field at the insulator/silicon interface in these regions. 2.3. Self-consistency Well into subthreshold, where the inversion charge density is relatively small, the inter-electrode capacitive coupling dominates the electrostatics in the device body. However, a small contribution that arises from the inversion electrons near source and drain can
Fig. 3. Analytical modeling with corner corrections of the inter-electrode potential distribution in the DG MOSFET for Vgs = 0 V and Vds = 0.2 V (a), and comparison between model (solid curves) and numerical simulations (symbols) along the two symmetry axes (b).
be included as an adjustment of the source and drain boundary potentials [14,16]. Near and above threshold, the electron contribution to the body electrostatics must be included in a self-consistent manner relying on the 2-D Poisson’s equation and the use of analytical modeling expressions [14,16]. In strong inversion, the electrostatics will be dominated by the inversion charge except for regions close to the source and drain electrodes. 3. Intrinsic capacitances The intrinsic capacitances are calculated from charges determined by the vertical electric displacement field on the electrode surfaces. This displacement field can be derived from the device electrostatics discussed in Section 2. One part of electrode charges is associated with the inter-electrode coupling and the other part with the body charges. Charge conservation requires that the former add up to zero charge and the latter to the total body charge when summed over all electrodes. For symmetric gate biasing, the DG MOSFET can be considered a three-terminal device. Imposing charge conservation [19], such a device will have nine capacitances CXY as indicated in the equivalent circuit in Fig. 4 [20]. Of these, four are independent. The
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The above results represent the dominant contributions to the capacitances in subthreshold owing to the relatively insignificant body charge. 5. Capacitances near and above threshold
Fig. 4. Equivalent circuit of the DG MOSFET with symmetric gate biasing, indicating the nine self-and trans-capacitances.
self- (X = Y) and trans-capacitances (X 6¼ Y) reflect the change of the charge on electrode X with a small variation in the voltage on electrode Y.
From near threshold to strong inversion, the contribution of the inversion charges will steadily increase in importance for the intrinsic device capacitances. From the self-consistent device electrostatics, we find the perpendicular electric field on the electrodes, from which the total electrode charges QS, QD, and QG and the intrinsic capacitances are determined. However, especially at the source and drain the charges may be difficult to determine precisely this way because of strong corner effects. Instead, using the above result for QG, we subtract the contribution from the interelectrode coupling to obtain the mirror charges QGc associated with the body inversion charges QBc. Hence, from charge conservation we have QSc + QDc = QBc + QGc. Furthermore, at zero drain-source bias QSc0 = QDc0. With applied drain-source bias, QB, QG, and QD will change, while QS remains almost the same, leading to QDc = QBc + QGc QSc0. To find the total charges, we have to add the constant contributions from the inter-electrode coupling. Fig. 5 shows the model capacitances versus Vgs for different values of Vds, covering operating conditions from deep subthreshold to strong inversion. The results are shown to compare very well
4. Capacitances associated with the inter-electrode coupling Using the approximate potential distribution in (3), we obtain the perpendicular electric field E\ at the electrodes, from which we derive the following analytical expression for the electrode charges associated with the inter-electrode coupling [21],
ouL du ov v!0 z umin min iesi ðu 1Þðku þ 1Þ uþ1 þ V S ln V G ln ¼ ðu þ 1Þðku 1Þ ku þ 1 p u u 1 max þV D ln ku 1
Q X ¼ esi
Z
zmax
E? dz ¼ iesi
Z
umax
ð7Þ
umin
Here, VG = Vgs – VFB, VS = Vbi, VD = Vds + Vbi. The limits of integration are the appropriate dimensions of the electrodes over which the intrinsic charges are distributed. For the drain and source electrodes, the integration runs from y = t’ox to tsi + t’ox for x = ±L/2, respectively, or between the corresponding coordinates on the uaxis in the four-corner (u, v)-plane. The latter are obtained from the transformation in (1). For the gate electrodes, we notice from Fig. 2a that the charges close to the corners between the bold solid and dashed lines correspond to field lines that terminate on the sides of the source/drain electrodes. Therefore, in order to preserve intrinsic total charge neutrality, these charges should be excluded and assigned to the extrinsic capacitances. From the one-corner analysis, we find that the integration for the intrinsic gate charge should run between x = L/2 + x0 and L/2 x0 for the two gates, where x0 = 0.339t’ox, or between the corresponding coordinates along the u-axis in the (u, v)-plane. The capacitances are found by taking the derivatives of the electrode charges with respect to the various electrode potentials, i.e., CXY = ±dQX/dVY, where the plus sign applies when X = Y. For the inter-electrode coupling, QX is a linear function in VY, which means that all the capacitances are bias independent. Owing to symmetry and charge conservation, we find that CGS = CGD = CSG = CDG, CDS = CSD, and CSS = CDD = CGG/2. For the device defined in Section 1, the values are per 1 lm channel width: CGS = 0.25 fF, CDS = 0.005 fF, CGG = 0.5 fF.
Fig. 5. Modeled DG MOSFET capacitances (symbols) from subthreshold to strong inversion for VDS = 0 V (a), and 0.2 V (b). The solid curves are obtained from numerical simulations (Silvaco Atlas).
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with simulations performed using the Silvaco Atlas device simulator. 6. Conclusions We have developed a precise, compact 2-D current and capacitance model for nanoscale DG MOSFETs that covers all operating regimes from sub-threshold to strong inversion. The 2-D modeling is based on a precise conformal mapping description of the interelectrode capacitive coupling, including a special treatment of the corner regions. In moderate to strong inversion, a self-consistent procedure to model the charge along the gate contact is introduced. The capacitances calculated by the present method show excellent agreement with numerical simulations (Silvaco Atlas). Acknowledgements This work was supported by European Commission under Contract No. 506844 (SINANO) and the Norwegian Research Council under Contract No. 159559/130 (SMIDA). We acknowledge the donation of TCAD tools from Silvaco and useful discussions with Prof. Benjamin Iñiguez at Univeritat Rovira i Virgili, Tarragona, Spain. References [1] The International Technology Roadmap for Semiconductors; 2005.. [2] Taur Y. An analytical solution to a double-gate MOSFET with undoped body. IEEE Electron Dev Lett 2000;21:245–7. [3] Taur Y, Liang X, Wang W, Lu H. A continuous, analytic drain-current model for DG-MOSFETs. IEEE Electron Dev Lett 2004;25:107–9. [4] Ortiz-Conde A, Garcia Sanchez FJ, Muci J. Rigorous analytic solution for the drain current of undoped symmetric dual-gate MOSFETs. Solid-State Electron 2005;49:640–7.
[5] Ortiz-Conde A, Garcia Sanchez FJ, Muci J, Malobabic S, Liou JJ. A review of core compact models for double-gate SOI MOSFETs. IEEE Trans Electron Dev 2007;54:131–9. [6] Moldovan O, Jiménez D, Guitart JR, Chaves FA, Iñiguez B. Explicit analytical charge and capacitance models of undoped double-gate MOSFETs. IEEE Trans Electron Dev 2007;54:1718–24. [7] Liang YP, Taur Y. A 2-D analytical solution for SCEs in DG MOSFETs. IEEE Trans Electron Dev 2004;51:1385–91. [8] Frank DJ, Taur Y, Wong H-SP. Generalized scale length for two-dimensional effects in MOSFETs. IEEE Electron Dev Lett 1998;19:385–7. [9] Oh S-H, Monroe D, Hergenrother JM. Analytic description of short-channel effects in fully-depleted double-gate and cylindrical, surrounding-gate MOSFETs. IEEE Electron Dev Lett 2000;21:445–7. [10] Weber E. Electromagnetic fields, vol. 1. New York: Wiley; 1950. [11] Kolberg S, Fjeldly TA. 2D modeling of nanoscale double gate silicon-oninsulator MOSFETs using conformal mapping. Phys Scr 2006; T126:54-0. [12] Fjeldly TA, Kolberg S, Iñiguez B. Precise 2-D compact modeling of nanoscale DG MOSFETs based on conformal mapping techniques. Proc NSTI-Nanotech 2006;3:668–73. [13] Iñiguez B, Fjeldly TA, Lazaro A, Danneville F, Deen MJ. Compact modeling solutions for double gate and gate-all-around MOSFETs. IEEE Trans Electron Dev 2006;53:2128–42. [14] Kolberg S. Modeling of electrostatics and drain current in nanoscale doublegate MOSFETs. PhD thesis. Norwegian University of Science and Technology; 2007. [15] Børli H, Kolberg S, Fjeldly TA. Analytical Modeling Framework for shortchannel DG and GAA MOSFETs. Proc NSTI-Nanotech 2007;3:505–9. [16] Børli H, Kolberg S, Fjeldly TA, Iñiguez B. Precise modeling framework for shortchannel double-gate and gate-all-around MOSFETs. IEEE Trans Electron Dev [submitted for publication]. [17] Børli H, Kolberg S, Fjeldly TA. Physics based current and capacitance modeling of short-channel double gate and gate-all-around MOSFETs. Proc IEEE Int Nanoelectr Conf (INEC) 2008:844–9. [18] Kolberg S, Fjeldly TA, Iñiguez B. Self-consistent 2D compact model for nanoscale double gate MOSFETs. Lect Notes Comp Sci 2006;3994:607–14. [19] Ward DE, Dutton RW. A charge-oriented model for MOS transistor capacitances. IEEE J Solid-State Circ 1978;13:703–8. [20] Nawaz M, Fjeldly TA. A new charge conserving capacitance model for GaAs MESFETs. IEEE Trans Electron Dev 1997;44:1813–21. [21] Børli H, Vinkenes K, Fjeldly TA. Physics based capacitance modeling of short-channel double-gate MOSFETs. Phys Status Solidi [accepted for publication].
Contents lists available at ScienceDirect
Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
Capacitance modeling of short-channel double-gate MOSFETs Håkon Børli *, Sigbjørn Kolberg, Tor A. Fjeldly Department of Electronics and Telecommunications, Norwegian University of Science and Technology/University Graduate Center, P.O. Box 70, 2027 Kjeller, Norway
a r t i c l e
i n f o
Article history: Received 13 May 2008 Accepted 7 June 2008 Available online 25 July 2008 Review of this manuscript was arranged by A. Iliadis, C. Richter, and A. Zaslavsky Keywords: MOSFET Double-gate Nanoscale 2-D modeling Conformal mapping Capacitance
a b s t r a c t We present 2-D physics based modeling of short-channel double-gate MOSFETs of nanoscale dimensions. We have derived a precise, self-consistent framework model for the device electrostatics, the drain current, and the charge conserving capacitances, covering all regimes of device operation from subthreshold to strong inversion. The modeling has no adjustable parameters and implicitly incorporates scaling with device dimensions and material composition. The foundation of the 2-D modeling is an analytical description of the inter-electrode capacitive coupling between the four electrodes, based on conformal mapping techniques. The model is shown to be in excellent agreement with numerical simulations. Ó 2008 Elsevier Ltd. All rights reserved.
1. Introduction The double-gate (DG) MOSFET has been identified as one of the promising device structures for future nanoscale CMOS applications [1]. Precise analytical models for such devices are needed for circuit simulators and circuit design tools. So far, most of the modeling work done on DG MOSFETs has been concentrated on long-channel, undoped devices, where analytical solutions for the device electrostatics, drain current, and capacitances have been obtained based on a 1-D Poisson’s equation perpendicular to the gates [2–6]. For short-channel devices where the charge-sharing regions near source and drain are important, we are faced with a 2-D electrostatics problem, which previously was modeled using simplifying assumptions or by Fourier expansion [3,7–9]. As an alternative, we proposed a procedure where the inter-electrode capacitive coupling between the source, drain, and gates is considered separately as the solution of a 2-D Laplace equation for the device body potential. Using conformal mapping techniques [10], this leads to a precise analytical solution in terms of elliptic integrals [11–14]. This solution is dominant in subthreshold for low-doped, nanoscale devices.
* Corresponding author. E-mail addresses: [email protected] (H. Børli), [email protected] (S. Kolberg), [email protected] (T.A. Fjeldly). 0038-1101/$ - see front matter Ó 2008 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2008.06.022
Near and above threshold and in moderate inversion, where the contribution to the electrostatics from the inversion charge becomes comparable to that of the inter-electrode effect, a self-consistent solution of Poisson’s equation in combination with modeling expressions were used [14–17]. The modeling expressions are constrained by the boundary conditions imposed on the final solution. Moreover, for applied drain biases, the quasi-Fermi potential distribution and the drain current must also be incorporated in this self-consistent solution. In strong inversion, the carriers tend to screen the influence of the source and drain electrodes and the device acquires a long-channel behavior. For simplicity, the drain current was calculated using the driftdiffusion transport mechanism with constant mobility. This is justified since, fortuitously, numerical simulations indicate that the drain currents obtained for the nanoscale devices considered, agree very well with those obtained from more advanced simulations based on hydrodynamic and energy transport formalisms [16,17]. From the above modeling framework, we can also calculate the intrinsic device capacitances in all operating regimes. In subthreshold, the capacitances are dominated by the inter-electrode coupling, from which analytical expressions for the charge conserving trans- and self-capacitances can readily be derived using conformal mapping techniques. Near and above threshold, we obtain the total, vertical electric displacement field on the gate, source, and drain electrodes from the device electrostatics, from which the electrode charges and capacitances can be derived. The modeled capacitances are verified against numerical simulations. Since no fitting parameters are used, the capacitance model
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together with the corresponding drain current model is scalable over a wide range of geometric and material combinations. The specific device considered is shown in Fig. 1. It has a gate length of L = 25 nm, a silicon thickness of tsi = 12 nm, a p-type body doping of Na = 1015 cm3 and a high-k gate insulator with a relative permittivity of eox = 7 and a thickness of tox = 1.6 nm. To simplify the calculations we replace the insulator thickness tox by an electrostatically equivalent silicon layer of thickness t0 ox = toxesi/eox, where esi = 11.8 is the relative permittivity of silicon. Thereby we avoid dealing with internal interfaces when solving the 2-D Laplace equation in the extended device body bounded by the four electrodes. Idealized Schottky contacts with a work function of 4.17 eV (corresponding to that of n+ silicon) are assumed for the source and drain. This ensures equipotential surfaces on all device contacts. Metal gates with a mid-gap work function of 5.53 eV are assumed.
v
p
1
1
uL ðu0 ; 0Þ ðu u0 Þ2 þ v2
du0
ð2Þ
For a very thin gate insulator, the boundary potential distribution uL(u, 0) is only defined by the four equipotential electrodes, leading to the following analytical solution [14,18]:
1 ku 1 þ ku tan1 ðV gs2 V FB Þ p tan1 kv kv p 1 u 1 þ u þ ðV gs1 V FB Þ tan1 þ tan1 v v 1 ku 1 u tan1 þ V bi tan1 kv v 1 þ ku 1þu tan1 ð3Þ þðV bi þ V ds Þ tan1 kv v
uL ðu; vÞ ¼
1
where Vgs1 and Vgs2 are the gate-source potentials, Vds is the drainsource potential, VFB is the flat band voltage, and Vbi is the built-in voltage. In the following, we consider only symmetric gate biasing, i.e., Vgs1 = Vgs2.
2. Electrostatics 2.1. Inter-electrode coupling The basis for the present modeling of the DG MOSFET capacitances is the device body electrostatics discussed in Section 1. As indicated, the inter-electrode capacitive coupling can be determined analytically from Laplace’s equation using conformal mapping techniques. This maps the extended, rectangular device body in the (x, y)-plane (including the gate insulators, see Fig. 1) into the upper half of a transformed (u, v)-plane according to the appropriate Schwartz–Christoffel transformation [10,18]
oz 1 ¼ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ; ow 2 2 ð1 w Þð1 k w2 Þ
uL ðu; vÞ ¼
Z
or z ¼ x þ iy ¼
L Fðk; wÞ 2 KðkÞ
ð1Þ
Here, z = x + iy, w = u + iv, the modulus k is a geometric parameter between 0 and 1 determined from the extended device height/ width ratio, F(k,w) is the elliptic integral of the first kind, and K(k) = F(k,1) is the corresponding complete elliptic integral. We note that the boundary of the extended body in the (x, y)-plane maps onto the real u-axis in the (u, v)-plane, and that the four corners of the boundary map into u = ±1, ±1/k. In the (u, v)-plane, the potential distribution uL(u, v) throughout the body can be obtained from Laplace’s equation by performing the following integral along the entire boundary (u-axis):
2.2. Corner corrections For realistic gate insulator thicknesses, (3) is still a good approximation for most of the body interior, but tends to fail close to the four corners of the body. For the calculation of the drain current, this effect is minor and can be corrected by simple means [16]. However, for modeling the capacitances, a more accurate description of the boundary potential distribution across the insulator is needed. This can be obtained by considering a single corner as shown in Fig. 2a, where the boundary insulator gap is indicated as the heavy, dashed vertical line. The orthogonal field lines and equipotential lines near the corner are also shown. Assuming that all other dimensions are large compared to t0 ox, the potential distribution in this region can be modeled by performing a new conformal mapping defined by the following Schwartz–Christoffel transformation [10]
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi w1c 1 ; or z1c ¼ x1c þ iy1c w1c pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2t 0 ¼ ox f½ w1c 1 tan1 ð w1c 1Þ þ 1g
oz1c ¼ ow1c
p
ð4Þ
Here, the subscript 1c indicates that this is a one-corner transform. Again, performing the integral in (2), we find the following potential distribution in the (u1c, v1c)-plane,
1
1
uðu1c ; v1c Þ ¼ ðV gx V FB þ V bi Þ ðV gx V FB 2 p V bi Þtan1
u1c ; v1c
ð5Þ
where Vgx becomes Vgs for a source side corner or Vgd for a drain side corner. The equipotential lines are radials and the electric field lines are semicircles as shown in Fig. 2b. Mapping the potential distribution along the insulator part of the boundary back to the (x1c, y1c)-plane results in the profile shown in the inset of Fig. 2a. This distribution can be approximated quite well by the polynomial
uox ð0; y1c Þ ¼ ayn1c þ by1c þ V gs V FB
Fig. 1. Schematic view of the DG MOSFET cross-section.
ð6Þ
where a and b are parameters determined by the potentials at the drain or source contacts and from an arbitrary point inside the insulator using (5) in combination with (4). The parameter n is chosen for minimum deviation from the true potential profile in the insulator defined by (5). n = 6 appears to be a suitable choice. Since this
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Fig. 2. Equipotential lines and field lines from the one-corner analysis in the (x1c, y1c)-plane with inset showing the potential profile along the four-corner boundary through the insulator gap (a). Transformed fields and potentials in the (u1c, v1c)plane (b). The bold solid curve shows the field line emanating from the corner. The bold dashed curve shows the insulator part of the boundary through the insulator.
value is obtained from a consideration of the one-corner electrostatics, it will be invariant with respect to the device dimensions. Next, the distribution (6) is mapped into the four-corner (u, v)plane, this time using an expansion of the mapping function (1) valid for the vicinity of the corners. The resulting potential distribution along the insulator boundary in the (u, v)-plane then yields analytical correction terms to uL(u, v) when applied to the integral in (2). The corrected potential distribution in the (x, y)-plane is shown in Fig. 3a for Vgs = 0 V and Vds = 0.2 V. A comparison with numerical simulations for the source-to-drain (S–D) and the gate-to-gate (G–G) symmetry axes in Fig. 3b indicates a near-perfect match. Close to the corners, we find deviation on the millivolt level. These are attributed to the scaling of the insulator thickness, resulting from the brake-down of the assumption of a vertical field at the insulator/silicon interface in these regions. 2.3. Self-consistency Well into subthreshold, where the inversion charge density is relatively small, the inter-electrode capacitive coupling dominates the electrostatics in the device body. However, a small contribution that arises from the inversion electrons near source and drain can
Fig. 3. Analytical modeling with corner corrections of the inter-electrode potential distribution in the DG MOSFET for Vgs = 0 V and Vds = 0.2 V (a), and comparison between model (solid curves) and numerical simulations (symbols) along the two symmetry axes (b).
be included as an adjustment of the source and drain boundary potentials [14,16]. Near and above threshold, the electron contribution to the body electrostatics must be included in a self-consistent manner relying on the 2-D Poisson’s equation and the use of analytical modeling expressions [14,16]. In strong inversion, the electrostatics will be dominated by the inversion charge except for regions close to the source and drain electrodes. 3. Intrinsic capacitances The intrinsic capacitances are calculated from charges determined by the vertical electric displacement field on the electrode surfaces. This displacement field can be derived from the device electrostatics discussed in Section 2. One part of electrode charges is associated with the inter-electrode coupling and the other part with the body charges. Charge conservation requires that the former add up to zero charge and the latter to the total body charge when summed over all electrodes. For symmetric gate biasing, the DG MOSFET can be considered a three-terminal device. Imposing charge conservation [19], such a device will have nine capacitances CXY as indicated in the equivalent circuit in Fig. 4 [20]. Of these, four are independent. The
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The above results represent the dominant contributions to the capacitances in subthreshold owing to the relatively insignificant body charge. 5. Capacitances near and above threshold
Fig. 4. Equivalent circuit of the DG MOSFET with symmetric gate biasing, indicating the nine self-and trans-capacitances.
self- (X = Y) and trans-capacitances (X 6¼ Y) reflect the change of the charge on electrode X with a small variation in the voltage on electrode Y.
From near threshold to strong inversion, the contribution of the inversion charges will steadily increase in importance for the intrinsic device capacitances. From the self-consistent device electrostatics, we find the perpendicular electric field on the electrodes, from which the total electrode charges QS, QD, and QG and the intrinsic capacitances are determined. However, especially at the source and drain the charges may be difficult to determine precisely this way because of strong corner effects. Instead, using the above result for QG, we subtract the contribution from the interelectrode coupling to obtain the mirror charges QGc associated with the body inversion charges QBc. Hence, from charge conservation we have QSc + QDc = QBc + QGc. Furthermore, at zero drain-source bias QSc0 = QDc0. With applied drain-source bias, QB, QG, and QD will change, while QS remains almost the same, leading to QDc = QBc + QGc QSc0. To find the total charges, we have to add the constant contributions from the inter-electrode coupling. Fig. 5 shows the model capacitances versus Vgs for different values of Vds, covering operating conditions from deep subthreshold to strong inversion. The results are shown to compare very well
4. Capacitances associated with the inter-electrode coupling Using the approximate potential distribution in (3), we obtain the perpendicular electric field E\ at the electrodes, from which we derive the following analytical expression for the electrode charges associated with the inter-electrode coupling [21],
ouL du ov v!0 z umin min iesi ðu 1Þðku þ 1Þ uþ1 þ V S ln V G ln ¼ ðu þ 1Þðku 1Þ ku þ 1 p u u 1 max þV D ln ku 1
Q X ¼ esi
Z
zmax
E? dz ¼ iesi
Z
umax
ð7Þ
umin
Here, VG = Vgs – VFB, VS = Vbi, VD = Vds + Vbi. The limits of integration are the appropriate dimensions of the electrodes over which the intrinsic charges are distributed. For the drain and source electrodes, the integration runs from y = t’ox to tsi + t’ox for x = ±L/2, respectively, or between the corresponding coordinates on the uaxis in the four-corner (u, v)-plane. The latter are obtained from the transformation in (1). For the gate electrodes, we notice from Fig. 2a that the charges close to the corners between the bold solid and dashed lines correspond to field lines that terminate on the sides of the source/drain electrodes. Therefore, in order to preserve intrinsic total charge neutrality, these charges should be excluded and assigned to the extrinsic capacitances. From the one-corner analysis, we find that the integration for the intrinsic gate charge should run between x = L/2 + x0 and L/2 x0 for the two gates, where x0 = 0.339t’ox, or between the corresponding coordinates along the u-axis in the (u, v)-plane. The capacitances are found by taking the derivatives of the electrode charges with respect to the various electrode potentials, i.e., CXY = ±dQX/dVY, where the plus sign applies when X = Y. For the inter-electrode coupling, QX is a linear function in VY, which means that all the capacitances are bias independent. Owing to symmetry and charge conservation, we find that CGS = CGD = CSG = CDG, CDS = CSD, and CSS = CDD = CGG/2. For the device defined in Section 1, the values are per 1 lm channel width: CGS = 0.25 fF, CDS = 0.005 fF, CGG = 0.5 fF.
Fig. 5. Modeled DG MOSFET capacitances (symbols) from subthreshold to strong inversion for VDS = 0 V (a), and 0.2 V (b). The solid curves are obtained from numerical simulations (Silvaco Atlas).
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with simulations performed using the Silvaco Atlas device simulator. 6. Conclusions We have developed a precise, compact 2-D current and capacitance model for nanoscale DG MOSFETs that covers all operating regimes from sub-threshold to strong inversion. The 2-D modeling is based on a precise conformal mapping description of the interelectrode capacitive coupling, including a special treatment of the corner regions. In moderate to strong inversion, a self-consistent procedure to model the charge along the gate contact is introduced. The capacitances calculated by the present method show excellent agreement with numerical simulations (Silvaco Atlas). Acknowledgements This work was supported by European Commission under Contract No. 506844 (SINANO) and the Norwegian Research Council under Contract No. 159559/130 (SMIDA). We acknowledge the donation of TCAD tools from Silvaco and useful discussions with Prof. Benjamin Iñiguez at Univeritat Rovira i Virgili, Tarragona, Spain. References [1] The International Technology Roadmap for Semiconductors; 2005.
[5] Ortiz-Conde A, Garcia Sanchez FJ, Muci J, Malobabic S, Liou JJ. A review of core compact models for double-gate SOI MOSFETs. IEEE Trans Electron Dev 2007;54:131–9. [6] Moldovan O, Jiménez D, Guitart JR, Chaves FA, Iñiguez B. Explicit analytical charge and capacitance models of undoped double-gate MOSFETs. IEEE Trans Electron Dev 2007;54:1718–24. [7] Liang YP, Taur Y. A 2-D analytical solution for SCEs in DG MOSFETs. IEEE Trans Electron Dev 2004;51:1385–91. [8] Frank DJ, Taur Y, Wong H-SP. Generalized scale length for two-dimensional effects in MOSFETs. IEEE Electron Dev Lett 1998;19:385–7. [9] Oh S-H, Monroe D, Hergenrother JM. Analytic description of short-channel effects in fully-depleted double-gate and cylindrical, surrounding-gate MOSFETs. IEEE Electron Dev Lett 2000;21:445–7. [10] Weber E. Electromagnetic fields, vol. 1. New York: Wiley; 1950. [11] Kolberg S, Fjeldly TA. 2D modeling of nanoscale double gate silicon-oninsulator MOSFETs using conformal mapping. Phys Scr 2006; T126:54-0. [12] Fjeldly TA, Kolberg S, Iñiguez B. Precise 2-D compact modeling of nanoscale DG MOSFETs based on conformal mapping techniques. Proc NSTI-Nanotech 2006;3:668–73. [13] Iñiguez B, Fjeldly TA, Lazaro A, Danneville F, Deen MJ. Compact modeling solutions for double gate and gate-all-around MOSFETs. IEEE Trans Electron Dev 2006;53:2128–42. [14] Kolberg S. Modeling of electrostatics and drain current in nanoscale doublegate MOSFETs. PhD thesis. Norwegian University of Science and Technology; 2007. [15] Børli H, Kolberg S, Fjeldly TA. Analytical Modeling Framework for shortchannel DG and GAA MOSFETs. Proc NSTI-Nanotech 2007;3:505–9. [16] Børli H, Kolberg S, Fjeldly TA, Iñiguez B. Precise modeling framework for shortchannel double-gate and gate-all-around MOSFETs. IEEE Trans Electron Dev [submitted for publication]. [17] Børli H, Kolberg S, Fjeldly TA. Physics based current and capacitance modeling of short-channel double gate and gate-all-around MOSFETs. Proc IEEE Int Nanoelectr Conf (INEC) 2008:844–9. [18] Kolberg S, Fjeldly TA, Iñiguez B. Self-consistent 2D compact model for nanoscale double gate MOSFETs. Lect Notes Comp Sci 2006;3994:607–14. [19] Ward DE, Dutton RW. A charge-oriented model for MOS transistor capacitances. IEEE J Solid-State Circ 1978;13:703–8. [20] Nawaz M, Fjeldly TA. A new charge conserving capacitance model for GaAs MESFETs. IEEE Trans Electron Dev 1997;44:1813–21. [21] Børli H, Vinkenes K, Fjeldly TA. Physics based capacitance modeling of short-channel double-gate MOSFETs. Phys Status Solidi [accepted for publication].