BiMOS and SMOSC structures for MOS parameter measurement

Solid-State ElectronicsVol. 35, No. 3, pp. 357-369, 1992 Printed in Great Britain.All rights reserved

0038-1101/92 $5.00+ 0.00 Copyright © 1992PergamonPress pie

INVITED PAPER BiMOS A N D SMOSC STRUCTURES FOR MOS PARAMETER M E A S U R E M E N T TOSHIKAZUNISHIDA Department of Electrical Engineering and Florida Solid-State Electronics Laboratory, University of Florida, Gainesville, FL 3261l, U.S.A.

(Received 28 August 1991; in revised form 27 September 1991) A~tract--Measurements of gate oxide stability in MOS VLSI development and manufacturing using substrate injection on two test structures are reviewed: the d.c. substrate injection via bipolar injector-MOS transistor (BiMOS) and the pulsed a.c. substrate injection via sourced-MOS capacitors (SMOSC). These techniques overcome the limitations of the MOS capacitor (MOSC) technique in measuring the fundamental dependencies of oxide trap charging and generation on the oxide electric field. They allow independent control of the oxide electric field, gate injection current, and electron energy. Application examples are described.

l. INTRODUCTION Since the discovery of thermally-grown SiO2 on Si substrate as a high-quality, manufacturable insulator in the metal(polycrystalline Si)-oxide(insulator)semiconductor field-effect transistor (MOSFET) [1,2], extensive efforts have been made to characterize the electrical properties of the gate oxide which affect the MOSFET operation and reliability. Technology advances toward shorter channel lengths and thinner oxides have resulted in higher channel and oxide electric fields which have accentuated the need for comprehensive measurement techniques for the gate oxide reliability under research and manufacturing conditions. Measurement techniques employing the two-terminal metal-oxide-semiconductor capacitor (MOSC)[3,4] gained wide usage due to the ease of fabricating the MOSC test structure, executing the measurement and analyzing the data. MOSC measurements on single devices include the highfrequency capacitance vs voltage (HFCV)[4], d.c. current vs voltage ( l - V ) and a.c. conductance and capacitance vs small-signal frequency (G-m and C-xo)[5]. Analyses of the data obtained on unstressed MOSC give the initial (tstre~= 0) areal oxide charge density and the density of interface traps as a function of the trap energy level[5-7]. Measurements on a large number of unstressed MOSCs under identical conditions give the statistical distribution of electrical properties, and histogram of the oxide breakdown electric field, and the manufacturing yield using an assumed defect distribution model. When the measurements are made as a function of stress and anneal time, tst~ and tann~l, under application of electrical stress (voltage, current and temperature), the rate of change of the oxide electrical

properties may be monitored which gives the fundamental kinetic parameters of charging, discharging, generation and annealing mechanisms of the electronic traps in the oxide and at the oxide/Si interface. The instability of the oxide under stress is deleterious to the operation of the MOS transistor, hence understanding oxide degradation under electrical stress is critical to improving MOS transistor and MOS integrated circuit reliability. Snow et al.[8] discovered and demonstrated in 1964 that oxide charge redistribution due to mobile sodium ion drift was the main source of threshold voltage instability in early MOS transistors. They used the voltage shift of HFCV curves of MOSC under high-voltage stress. The mobile ion contamination is essentially eliminated in VLSI technology through careful chemical and oxidation ambient purity control. In state-of-the-art submicron VLSI technology, the dominant transistor degradation mechanisms causing threshold voltage instability are injection and charging and generation of electronic[9-11] and protonic[12] traps in the oxide. The key MOS stress parameters must be accurately known and held constant in order to delineate the physics of the mechanisms which govern oxide instability. These stress parameters are the oxide electric field, gate injection current and initial kinetic energy of the injected electron (or hole). These parameters must be controllable over a wide range (several orders of magnitude) so that the dependence of the fundamental oxide trap charging coefficients (capture coefficient, emission rate and generation rate) on the oxide field, injection current and kinetic energy may be extracted. These are the criteria by which the oxide measurement techniques are evaluated. Charge injection in MOSC is accomplished via the avalanche electron and hole injection (AEI and

357

358

TOSHIKAZU NISHIDA

AHI)[13] and Fowler-Nordheim tunneling electron and hole[14] injection (FNTEI and FNTHI) methods. Extensive results on charge trapping in MOSC oxides have been obtained from these methods and have been recently reviewed[15-18]. Although measurement of the two-terminal MOSC has the advantage of fabrication ease and measurement simplicity compared with three- or four-terminal devices, it does not afford independent control of the MOS stress parameters. In MOSC, the stress current and electric field in the gate oxide are interdependent during avalanche and FowlerNordheim tunneling stress. In avalanche injection stress, the oxide field is not constant but varies with the pulsed voltage applied across the MOSC in order to drive the Si surface layer into deep depletion and to inject[13] the thermally generated carriers over the oxide/Si potential barrier (3.1 eV for electrons and 4.7 eV for holes). In Fowler-Nordheim tunneling stress, a large oxide field ( > 6 MV cm -1) is required to obtain measurable quantum-mechanical tunneling current through the thin oxide/Si interfacial potential barrier[14]. The substrate injection measurement techniques using the d.c. bipolar injector-MOS transistor (BiMOS) and pulsed a.c. sourced-MOS capacitor (SMOSC) test structures overcome the limitations of the MOSC[ 19-24]. They provide comprehensive control of the MOS stress parameters. The application of BiMOS and SMOSC for measuring oxide reliability properties are described in the following sections. 2. d.c. SUBSTRATE ELECTRON INJECTION VIA BIPOLAR INJECTOR-MOS TRANSISTOR (BiMOS)

The BiMOS is an integrated bipolar-MOS transistor used by Sah in 1961 in earlier MOS device studies[25]. The structure was employed by Verwey in 1973 to measure the mean free path of electrons in Si substrate[26]. Hsu et al. reported the first uniform substrate p i n junction injection of electrons into wet oxide at varying oxide electric fields to investigate oxide trap charging and generation[20]. Areally uniform injection is crucial for obtaining the fundamental parameters from experimental data. Subsequent experiments have used the substrate electron injection via BiMOS for investigating the oxide field and temperature dependencies of oxide trap charging, discharging and generation[20-24], interface trap generation[27,28], instability of MOS transistor patterned by synchrotron X-ray lithography[29,30], and a new technique to measure the energy distribution of the oxide trap by electric field-stimulated emission (described in Section 2.4.2)[31,32]. A laterally located p i n junction on the surface has also been used to investigate the fluence dependence of electron trapping, positive charge formation, trapping and detrapping dynamics and trap generation[33-38] whose geometry hinders uniform substrate injection. Optically-generated carriers in the substrate were

employed by Ning and Yu to supply the minority carriers for substrate injection[39]. Optical substrate injection has been employed to investigate the emission probability of hot electrons from Si into SIO2[15], oxide trap charging and generation[40,41] and the effect of X-rays from an A1-Ka source on threshold voltage instability[42]. The optical substrate injection is uniform, but the test structure is difficult to fabricate. The operation of the forwardbiased p/n junction substrate injection via a BiMOS test structure is given in the next section. 2.1. Structure

A cross-section of the BiMOS test structure is shown in Fig. 1. The biasing for uniform substrate electron injection from a forward-biased structure emitter/base junction has been described previously[21] which is reiterated. The n ÷ source and n + drain are held at the same potential, VD - V s = VDS= 0. An applied voltage across the gate oxide induces an inversion layer between the n + source and the n + drain and determines the oxide electric field. The n + source, electron inversion layer and n + drain form the collector for the emitter-down n +/p/n-/n + vertical bipolar transistor. The vertical bipolar transistor acts as the substrate electron injector. Electrons are injected from the forward-biased substrate n +/pwell emitter-base junction into the p-well. An Si surface space-charge layer is formed by the reverse bias applied to the n +~p-well collector-base junction. The electrons that diffuse through the p-well base and reach the surface space-charge layer are accelerated towards the gate oxide in the thin Si surface spacecharge layer underneath the gate oxide. Those electrons attaining kinetic energies exceeding the barrier height at the oxide/Si interface (3.1 eV) are injected into the gate oxide. These injected electrons give the gate current used to measure the charging, discharging, generation and annealing rates of the traps in the gate oxide. In summary: the oxide electric field is controlled by the gate bias applied between the gate electrode and the n ÷ source and drain; the injected gate current is controlled by the emitter-base forward bias and the collector-base reverse bias; DRAIN (collector)

SOURCE (collector) GATE

BASE

_L P-well

.[~ ~;i~: it Inversion layer

IS

N-epitaxial layer

I N+ substrate

~"~ Electron Injection

EMITTER Fig. 1. Cross-section of p-well n-channel bipolar-MOSFET substrate injector test structure.

BiMOS and SMOSC for MOS parameter measurement and the energy distribution of the electrons at the Si/SiO2 interface is determined by the thickness of the space-charge layer and the electric field in the space-charge layer, or by the Si energy bandbending in the surface space-charge layer which is controlled by the collector-base reverse bias. Thus, the BiMOS test structure provides independent control of the key MOS stress parameters, the oxide electric field, gate current and the initial kinetic energy distribution.

2.2. Fabrication Polycrystalline Si-gate self-aligned bipolarMOSFET (BiMOS) test structures were fabricated on an oxidized (100) oriented B-implanted p-well on an n-In ÷ substrate and B-doped p - epitaxiai layer on an n ÷ substrate[21-24,31,32]. Oxides of various thicknesses and oxide processes were obtained at several American VLSI companies of the Semiconductor Research Corporation. These include 950°C partial steam, 900°C dry and 850°C dry/wet/dry oxidation processes. The 950, 900°C dry and 850°C dry/wet/dry oxides were grown with 0.0 and 0.3% trichloroethane in the oxidation ambient. The oxide thicknesses ranged from 80 to 315 ,~. Immediately following gate oxidation, a 3500/~ thick polysilicon layer was deposited and doped with POC13. The oxidized wafers with the polysilicon layer provided by the SRC collaborators were then processed by this author and his graduate students in the class 100 cleanroom facility at the University of Florida to fabricate the self-aligned n ÷ polysilicon gate BiMOS test structures. The fabrication steps are as follows: the source and drain junctions were implanted with 100keV P at 1 x 10~Scm-2 dose. Lower energy implant doses have also been used with same gate oxide reliability results. The implant was annealed at 850°C and followed by a drive-in diffusion at 950°C. Contact windows for source, drain and base were patterned and etched into the polysilicon and oxide using standard photolithography. Highpurity VLSI-MOS grade A1 was then thermally evaporated from a shuttered resistance-heated tungsten boat. The contacts were defined by etching away the excess A1. Die attach on a TO-5 header was performed using an Ag epoxy. Gold wires 1 mm in diameter were bonded by ultrasonic compression between the bonding posts and bonding pads.

2.3. Measurement and results The control of the oxide electric field in BiMOS allows the physics of the oxide degradation mechanisms to be investigated, in particular the oxide field dependence of the fundamental oxide charging processes and mechanisms. Four fundamental processes and mechanisms are identified. These are the charging process of existing unoccupied oxide electron traps by capture of injected electrons, the discharging process of filled oxide electron traps by elastic tunneling, thermal or trap-to-band Auger

359

impact mechanisms, the generation (creation) process of new oxide traps and the annealing or annihilation process of oxide traps by atomic reconfiguration (reconstruction) or chemical reaction (hydrogen atom). Unstressed BiMOS devices were stressed at a constant gate current flux and constant voltage across the gate oxide. The constant gate current was maintained via digital feedback control of the emitter current through the forward-bias of the substrate p well/n-/n ÷ epitaxial emitter junction using a MicroVAX-2 computer and an IEEE-488 bus. The electrical stress is characterized by the gate injection fluence, the applied oxide electric field and the accelerating collector-base reverse-bias potential across the surface space-charge layer. The gate injection fluence or number of electrons injected into the gate oxide per unit area, NINj(t), is simply given by N, Nj(t) = JG t/q where JG is the constant gate current, t is the stress time and q is the electronic charge. This constant J~ eliminates one uncertainty in the measurements of previous researchers who used NINJ(t) = q -1 ~rJo (t ') d t' where Jo (t') ~ constant and the rates depend on IJGI. The injection stress was interrupted periodically to measure the draincurrent-gate-voltage and gate-capacitance-gatevoltage characteristics. Annealing during measurements could be important but is not important during the measurement time and temperature of the data presented. An operational threshold voltage was defined as the gate voltage necessary to induce a drain-source channel current of 1/~A at an applied drain-source voltage of V D - Vs = VDS-'- 100 mV. During electrical stress, the gate oxide is charged by trapping the injected electrons at the existing oxide electron traps or at new traps generated by the energetic or hot electrons. The charging of the gate oxide gives rise to a gate voltage shift of the drain current and gate capacitance vs gate voltage curves (Io--VG and Cg-VG). The gate-,¢oltage shift and distortion of the drain current and gate capacitance were extracted as a function of the injected electron fluence at a constant oxide electric field over a range of oxide electric fields ( 1 - 8 . 5 M V c m - l ) . The shift of the C~VG curves was compared to the shift of the [D--VG curves. They were identical, which confirms that substrate injection is uniform because the drain current is sensitive to charge localized near the source junction, and the gate capacitance is sensitive to oxide charge throughout the entire channel. For all experiments, the shift of the threshold voltage was small compared to the total applied gate voltage; thus, the generated oxide charge is small, and the oxide electric field may be assumed constant. The threshold voltage shift of the MOS transistor stressed by substrate electron injection into the gate oxide includes contributions from charged oxide and charged interface traps. The threshold voltage shift A VGT was measured at the operation condition (I D = 1 t~A, VDS= 100 mV). The distortion of the

360

TOSHIKAZUNISHIDA

subthreshold Io-VG characteristics was obtained by using a two-point method (10 = 100 p A and 1 ttA at Vos = 100 mV). The AVcx(100 pA) - AV~T(I pA) shift or second derivative gives the net contribution of charged interface traps to the total threshold voltage shift in this drain current or gate voltage range[21]. Since increased interface trap density results in a nonparallel shift of the drain-currentgate-voltage curve, the difference in gate voltage shift at the two drain currents (nonparallel shift), AVcr(100pA ) -AVoT(1 #A), gives the net contribution of charged donor and acceptor interface traps to the threshold voltage shift for interface traps located in the Si energy gap between the two corresponding energies or surface potentials. The effect of mobility reduction due to neutral scattering by interface and oxide traps on the subthreshold slope is not included. The increase in charged oxide trap density, AnoT, is obtained from the gate voltage shift with interface trap contribution subtracted with the tacit assumption that the interface trap contribution is proportionally scaled by the measured contribution between 100 pA and 1 #A. The equation for evaluating the oxide traps is:

at 900°C in an industrial dry oxidation process[21]. This set of data are representative of those measured on 86-315 A oxides from the three oxidation processes at several oxide field strengths from 1.5 to 8.5 MV cm -1. Three dependencies of the gate voltage shift on oxide electric field were observed[21]: (i) at low oxide field, less than about 1.5-3 MV cm -~, the gate voltage shift increases with fluence initially and then nearly saturates at high fluences; (ii) in this low oxide field range, the saturation value has its maximum at the lowest field employed in the gate electron injection stress, l . S M V c m -l. The lowest field measured is determined by the lowest oxide field necessary to invert the Si surface layer. The saturation value decreases with increasing oxide field and reaches a minimum value between 3 and 4 MV cm-~; and (iii) above about 3-4 MV cm -~, the gate voltage shift no longer saturates but continues to increase with fluence. At higher oxide electric fields, the gate voltage shift vs electron fluence curves have larger slopes. The net charge trapped in the gate oxide is governed by the balance of the charging and discharging rates of oxide traps[21,37]. The density of oxide electron traps which are available to trap electrons is determined by the balance of the generation and Anox(t) = (1/qXor) X[PoT(X, t) -- PoT(X, 0)] dx thermal annealing rates of the traps. When the den= (Eo/q) (A VG-Or/XoT), (1) sity of oxide traps is constant, i.e. when the oxide trap generation and annealing rates are balanced or zero, where q is the magnitude of electronic charge, )Cox the net oxide charge is determined solely by the oxide is the centroid of the trapped oxide charge trap charging and discharging processes. Initially, measured from the gate-conductor/oxide interface, when the oxide is uncharged, the oxide charge inX o is the oxide thickness, Pox is the volume trapped creases linearly as the injected electrons are captured oxide charge density and Eo is the static dielectric at the oxide traps. The rate of oxide charging depermittivity of SiO 2. creases as fewer oxide traps are unoccupied and the 2.3.1. Oxide field dependence: (a) room temperature detrapping rate of occupied oxide traps increases. A (294K). The gate voltage shift A Vc.ox due to the steady-state is asymptotically reached when the rate charged oxide trap with gate voltage distortion due to of oxide trap charging balances the rate of oxide trap the interface trap subtracted as described in Section discharging. Analytically, it is given by the solution 2.3 is shown in Fig. 2 vs gate electron fluence NINj of the trap charging rate equation for the case of at oxide field strengths of 1.7-8.0MVcm -~ and constant trap density which is a single exponential for T = 294 K for the 86 A thick oxide thermally grown single-trap species with a single discrete capture crosssection[21]. This solution saturates asymptotically at large fluence. Therefore, the saturation of the gate 0 , 1 5 '"1 .... I .... I .... I.... I.... I.... I .... I .... I .... voltage shift at low oxide electric fields in Fig. 2 is • 6 . 9 V; 8 . 0 M V / c m T = 294K attributed to the attainment of a steady-state density _ • 6 . 0 V; 6.9 M V / c m ~ 0.12 • 5 . 0 V; 5 . 8 I d V / c m ~ " of charged oxide traps that is determined by the $ 3.3 V; 3.8 J opposing process of: (i) charging the unoccupied • 2.2 V; 2.5 ~ oxide traps by capturing the injected electron; and (ii) discharging the occupied oxide trap via thermal, tunneling and Auger impact electron-emission mechanisms[21]. At intermediate oxide electric fields and small 0.03 generation rates, an increase in oxide electric field decreases the saturation value of the oxide trapped O.b,,--. - - 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 charge by increasing the tunneling discharging rate of NIN J/(1017 cm -2) the oxide trap. This shifts the balance of the charging and discharging rate towards smaller net oxide charge Fig. 2. Gate voltage shift vs injected electron fluence for 86 A thermally-grown dry oxide (900°C, 0.0% TCA) as a density. Thus, the decrease of the saturation gate voltage shift with increasing oxide electric field function of oxide field[21].

f0

BiMOS and SMOSC for MOS parameter measurement

E

0

5.0

I

4.0

&86 A e193A

I

I

I

I

I

I

I

~)

/

I 0.0: ) 0,0 1,0 2.o 3.0

4.o

5.0

6.o

7.o a.o 9.0

Eox/(1 MV/em) Fig. 3. Steady-state gate voltage shift vs oxide field at constant electron fluence of 6 x t0 ~7cm -2 for thermally grown dry oxide (900°C, 0.0% TCA) with thicknesses of 86 and 193 A[21].

between 1.5 and 3 MV cm -] in Fig, 2 is attributed to the increasing tunneling discharging rate. The steadystate trapped oxide charge density is plotted in Fig. 3 as a function of the oxide field. It is calculated from the gate voltage shift at an electron fluence of 6 x 10~7cm -2 using eqn (1). The results shown in Fig. 3 are for dry oxide samples with thicknesses of 86 and 193 A. Previous work by Nishida and Thompson indicated that the steady-state charged oxide trap density reaches a minimum density at about 3 . 5 M V c m -I and then increases rapidly at larger oxide fields[21]. A decrease of the gate voltage shift with increase in oxide field has been observed by Hsu et al.[30] for oxide fields below 4 MV cm -l and by Nissan-Cohen et al. based on the flatband voltage shift[38]. They did not observe a minimum due to their limited range of electric field. The decrease of the charged oxide trap density with an increase in oxide electric field to the left of the minimum is due to the increase in the field-dependent tunneling discharging rate with an increase in oxide electric field when the generation rate is small. The increase of the charged oxide trap density to the right of the minimum with an increase in oxide electric field is explained by the increasing generation rate of oxide traps with increasing field and the subsequent charging of the newly-generated traps. A thickness dependence of the charged trap density was also observed[21]. The magnitude of the charged oxide trap density calculated by eqn (1) is larger for the thicker oxide from 86 to 193 A. This may be due to a spatial (thickness direction) distribution of the oxide traps in the oxide; however, centroid measurements are required to determine the probable distribution. The results showed a smaller threshold voltage shift at the same oxide field for the thinner oxide. The nonsaturation of the gate voltage shift in the high-field range (greater than 4 MV cm -~) in Fig. 2 is attributed to the generation of oxide traps by hot electrons accelerated in the oxide field[21]. This oxide

361

field does not delineate the threshold oxide field for trap generation because the gate voltage shift includes the balance of the charging, discharging, generation and annealing processes. The net oxide charge is determined by the balance of the charging, discharging and generation and annealing rates. When the generation rate becomes large, the total oxide trap density no longer remains constant, but increases due to the generation of new oxide traps by hot electrons. Thus, the gate voltage shift does not saturate at large fluence, and the gate voltage shift vs fluence curve has a nonzero slope. The effective trap generation efficiency ~/is computed from the slope of the linear portion of the gate voltage shift vs electron fluence curves. It is given by: r / = d(CoA VG.oT)/d(qNlm),

(2)

where Co is the gate oxide capacitance per unit area. In order to measure the charging of generated traps as opposed to the charging of existing traps, the trap generation efficiency is computed at a fluence above which the gate voltage shift nearly saturates at a low oxide (low field slope is nearly zero)[21]. Co = Eo/Xo would be replaced by COT=Eo/XoT if the trap centroid is measured. The fluence employed is 6 x l0 ]7 cm -2. The trap generation efficiency vs oxide field is plotted in Fig. 4 for 900°C dry oxide[21]. Similar results are observed for 950°C partial steam and 850°C dry/wet/dry oxides. The effective trap generation efficiency is proportional to the product of the trap generation rate and the ratio of charged oxide trap to total oxide trap density[21]. As seen in Fig. 4, the effective trap generation efficiency increases rapidly above about 4 M V c m -~. The extrapolated threshold oxide field for trap generation is consistent with the threshold field of about 1.5 MV cm-l extrapolated from the high field[20,40,41]. When plotted vs oxide field, the normalized trap generation efficiency is similar for all oxide thicknesses greater than about 150/~. Sub-onehundred Angstrom oxides showed a reduced trap generation rate and a smaller saturation oxide charge 0.6

1

1

I

I

I

I

I

I'

dry oxide (900C) 0.5 ~Z

0.4

• 86 A e193A u282A T-294K

e/ 32A/282A *,':,OA /

"O ~O 0.5

mm

7o7-

~.~ 0.1 0.0~ 0.0

-

[ ,~ r ~ ~ l 1.0 2.0 3.0 4,0

s.o

r 6.0

I 7.0

I 8.0

9.0

Eox/(1 MV/crn)

Fig. 4. Oxide field dependence of slope of gate voltage shift vs electron fluence calculated at constant electron fluence of 6 x 10t7 cm -2 for 900°C, 0.0% TCA dry oxide with thicknesses of 86, 193 and 282 A[21].

362

TOSHIKAZU

density compared to the thicker oxides[21]. Since the analysis of the trap generation rates also depends on the spatial distribution of the trapped charge in the oxide, the decrease of the generation efficiency in the thinner oxides (<100,~) compared to the thicker oxides may come from a different spatial variation of the trap concentration in the thin oxides than in the thick oxides due to the proximity of the gate and the substrate. 2.3.1(b). Low temperature (77K). The discharging rate of oxide traps by thermal emission of trapped electrons is negligible at 7 7 K for oxide traps with thermal activation energy greater than about 0.1 eV[31]. The measured thermal activation energy for shallow oxide traps is 0.3-0.4eV[19,31]. The generation rate of new oxide traps is minimized by injecting electrons at low temperature (77 K)[22,41,43]. Annealing of oxide traps is also negligible. Thus, the dominant processes that determine the net oxide charge at 77 K are the charging and field-dependent discharging processes[22,31,32]. Electrons are injected into the gate oxide at low oxide fields, 1-5 M V c m -~, to charge the existing oxide traps at low temperature, 77 K. The electron injection is periodically stopped to measure the gate capacitance vs gate voltage (Cg-Vo) and drain current vs gate voltage (ID--VO) curves at the stress temperature. Parallel and identical positive gate voltage shifts of the Cs-VG curves are observed which indicate charging of existing oxide electron traps and not the generation of new interface traps at 77 K. Figure 5 shows the oxide electric field dependence (1.3-4.6 M V c m -~) of the gate voltate shift vs electron fluence at 77 K measured on 150 ,~ oxide grown at 850°C in a dry/wet/dry oxidation ambient. The saturation of the gate voltage shift after an injected electron fluence greater than 2 × 1016cm -2 is due to the steady-state balance of the field- and temperaturedependent charging and discharging processes of the oxide traps. The saturation indicates negligible generation of new oxide traps[21,22]. The temperaturedependent discharging of oxide traps by thermal emission is minimized by injecting electrons into the I I I

1.5

NISHIDA

gate oxide at 77 K. Therefore, the decrease in the saturated gate voltage shift with an increase in oxide electric field at constant temperature (77 K) in Fig. 5 corresponds to an increasing discharge-rate with increasing oxide electric field. The discharge mechanism is the exponentially increasing trap-to-band tunnel emission rate with an increasing oxide electric field[31,32].

2.3.2. Temperature dependence: (a) Low oxide electric field. At low oxide electric field, less than about 3 MV cm -~, trap generation is small, as seen in Figs 2 and 4. Furthermore, if the annealing rate is negligible, then the net oxide charge is determined by the balance of the charging and discharging processes. As discussed in Section 2.3.2(b), the fielddependent discharging rate increases exponentially with oxide field. At low oxide electric field strengths, the field-dependent discharging rate is small. Figure 6 shows the temperature dependence (77-298 K) of the gate voltage shift vs electron fluence for electron injection into the gate oxide at low oxide electric field, 2.1 MV cm-1131 ]. The dominant processes that determine the net oxide charge are the charging and temperature-dependent discharging processes. The decrease in the saturated gate voltage shift at low constant oxide electric field (2.1 MV cm -1) in Fig. 6 corresponds to an increasing discharge rate with an increasing temperature. The discharge mechanism is the exponentially increasing discharge rate with increasing temperature. 2.3,2(b). High oxide electric field. At high oxide field and room temperature, nonsaturation of the gate voltage shift was observed in Fig. 2 [Section 2.3.1(a)] which was attributed to the generation of new oxide traps by hot electrons accelerated in the oxide electric field. The temperature dependence of trap generation is investigated by stressing the gate oxide for a range of temperatures from 77 to 373 K in the high-field region, above 4 MV cm- 1, where trap generation is significant at room temperature (294 K) as seen in Figs 2 and 4. The gate voltage shift vs injected electron fluence for the gate oxide stressed at a high oxide electric field of 7.5 M V c m -1 is shown

i t t f [ t I I I ] I I I t I t P I I

2.0

T=77K Eox=1.6 to 4.7MV/cm 1.0

.~

1.6

-

'

'

'

I

''

j

1.2 "~ (.9 "~ 0.5

'

Eox=2.1MV/cm VG=3 1V

'

I

'

'

'

'

f'

'

'

T=77K . J ~ - ~ • T=77K

• T= 150K mT=210K $ T=298K

'

-

0.8

~

<3

T=150K 0.,

0.0

2.0

4.0

&O

8.0

10.0

NtN J /(10'%m 2)

Fig. 5. Gate voltage shift vs electron fluence for 150/~ dry/wet/dry (850°C) oxide and gate voltages between 2.5 and 7.0V at 77 K[31].

~.=,-~F.

=F.,=.,~ I.-.

0,~ . . . . . . . . . . . . . . . . . . 0.0 5.0 10.0 15.0 NIN J /(lO'ecrn 2)

-I 20.0

Fig. & Gate voltage shift vs electron fluence for 150~ dry/wet/dry (850°C) oxide and temperature between 77 and 294 K at 2. l MV cm-i oxide electric field[3 l].

BiMOS and SMOSC for MOS parameter measurement 0.2 '"'1'"'1'"'1""1'"'1""1'"'1"")""1'"

"- 93 A dryD.tot/dryo x i d e " ~ T=373 K 0.16 "---oT=333 K o T=294 K CT=150K ~.~ 0.12 .vT=77KXO.1 FLUE

373 K 333 " ~ = ==,e' K = ~ ~

><~ 0.08

._

"

.~~~~

0.04

[ ~ . ~ ,T, ; ,¥~ ~;T,, 0.(, 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0

NINJ / (10t7cm-a) Fig. 7. Temperature dependence of trap generation between 77 and 373 K at oxide electric field of 7.5 MV cm -t for 93 A dry/wet/dry (850°C) oxide[23]. in Fig. 7 with the stress temperature as the parameter[22]. A significantly smaller gate voltage shift is observed at low temperature (below about 150 K) and high oxide electric field. This suggests that trap generation is suppressed below 150 K. The nonsaturation gate voltage shift at high oxide electric field is observed to become very small at 77 K. The oxide field was reduced to the low oxide field region to check the effect of field-assisted detrapping. Trap generation was found to be almost completely suppressed at 77 K[22]. This is in agreement with results obtained using optical substrate injection[41,43]. There are two important temperature effects: (i) electron trap generation is suppressed at low temperatures (below about 150 K) and high oxide field (above 4 M V c m - l ) ; and (ii) electron trapping at existing oxide traps increases at low temperatures and low oxide electric field due in part to a decreased discharging rate by thermal emission at the applied oxide field. 2.4. Analysis and discussion We next illustrate the analyses of the data to show how the results of the substrate injection are used to obtain fundamental kinetic parameters of instability in MOS oxides. 2.4.1. Trap generation. The control of the oxide field in the substrate injection method has provided the means to measure the oxide electric field dependence of oxide trap generation. DiMaria[40] reported an electron heating threshold oxide field of 1.5 MV cm-~ at 1 C cm -2 electron fluence from trap density vs oxide field data for dry oxides stressed by substrate optical injection. Hsu et aL[20] reported a trap generation threshold oxide field of 1.5 MV cm -l from the slope of the gate voltage shift extrapolated to Nmj = 0 for a wet oxide stressed by forward-biased substrate p/n junction injection. Badihi et a1.[44] and Nissan-Cohen et ai.[38] reported an increase of the trap density (at 0.03 C cm -2) and generation probability with an increase in oxide field in MOSFETs stressed from a laterally located p/n junction. These data may be extrapolated down to give a threshold

363

field of 2-3 MV cm- i. Liang et al. reported a critical field of 5 M V c m - l at 0 . 3 C c m -2 for accelerated oxide degradation[45], also from lateral p/n junction injection measurements on dry oxide. Since the net oxide charge is determined by the cumulative effect of the charging, discharging, generation and annealing processes, these reported threshold oxide fields indude not only the generation rate but also may include the charging, discharging and annealing rates of the oxide traps. This may explain the range of threshold oxide fields reported which are clustered around 1 . 5 - 2 M V c m -1. Carrier x-separation, electrohiminescence and vacuum emission experiments indicate a threshold oxide field of about 1.5 MV cm-1 for electron heating[46-49]. This correlation of the voltage shift in electrical I - V measurements with electron heating suggests that above the threshold oxide field for electron heating, the electron in the oxide conduction band gains energy, is no longer in thermal equilibrium with the oxide lattice and becomes energetically "hot". The conduction electron energy is stabilized at higher oxide electric fields via scattering by acoustic phonon and nonpolar intervalley phonons[46-50]. Some electrons may gain energy in excess of the threshold for bond-breaking and rupture strained intrinsic bonds or weak extrinsic hydrogen bonds by impact, generating unpaired or dangling bonds that have a quantum-mechanical electronic bound state[51,52]. Models involving hydrogen release and trapping have been proposed for trap generation[20,41,51,52]. The nonsaturation of the gate voltage shift vs electron fluence curves at high oxide electric field measured using BiMOS and shown in Fig. 2 led to the extension[21] of the electron trapping rate equation to include a trap generation kinetic model. The electron trapping rate equation was first introduced by Sah[53] in the analysis of noise in the junction-gate fieldeffect-transistor due to charge fluctuation at the Shockley-Read-Hall (SRH) center. The extension involved the inclusion of a time-dependent electron trap density nx(t ) obtained from first-order trap generation kinetics[51,52]. The first-order expansion of the trap generation kinetics, nx(t ) " Nxo + kx Nxx t, gives the following rate equation with constant trap generation rate[21]: dnox(t)/dt = ct~n[Nxo + k x N x x t - nox(t )] - e t n o r ( t ) - e~nnox(t ),

(3)

where nox (t) is the areal density of trapped electrons (cm-2), ct~ is the thermal capture coefficient (cm 3 s-l), Nxo is the initial electrically-active trap density, kx is the oxide trap generation rate, Nxx is the total oxide trap density, e t is the field-dependent thermal emission coefficient of trapped electrons ( s - ' ) , e] is the electron impact emission coefficient of trapped electrons (cm 3 s-1) and n is the electron concentration in SiO2 (cm-3). This notation is identical to the notation employed in the analysis of the trapping kinetics of

364

TOSHIKAZU NISHIDA

SRH centers[54]. The solution of eqn (3) is readily obtained and is given by[21]: noT(t)

=

nl {1 -- exp[-(ct.j/qO.)(Nxo/noT®)t} + gl t,

(4) where nl = nOT= - - (qO,/J)(kxNxx/ct)(nor~/Nxo) 2

(5)

gl = kxNxxnor~/Nxo,

(6)

nOT® = Nxo/[1 + (e~/c t) + (et /ct )(qO,/J)].

(7)

The gate voltage shift, A l/o.oT, is proportional to the change in the charged oxide trap density, AnoT(t ) = nOT(Q--noT(O ). This model qualitatively describes the nearly linear rise of the gate voltage shift with fluence given by the linear term gl t in eqn (4) above a fluence of 6 x 1017cm -2 as seen in Fig. 2 for the 86/~ dry oxide at oxide fields above about 4 MV cm -l. An exact numerical solution was also computed[21] which gave good agreement over the entire curve.

2.4.2. Electric-field-stimulated spectroscopy

tunneling

,

'1 . . . .

I''

''1''''1''''1

....

• 204A PARTIAL STEAM • 196A DRY • 150A DRY/WET/DRY "~

>

1.0

T = 77K

(8)

v

where 09 is the tunneling emission rate derived in the Price-Sah tunneling emission model[55], DoT(ET) is the density-of-states of an oxide electron trap at energy ET, and E c and Ev are the energies of the oxide conduction and valence band edges. The form of the tunneling emission rate is shown below[55]:

e9 = (n2/h 3) (my/m~)l/Z(Eox/ET) W 2 exp(-- 2 0 ) ,

(9)

0 = (4n/3)(2mx)l/ZEar/2(hEox) -l,

(10)

where h is the Planck constant, my and m= are the tunneling electron effective masses of SiO2 in the tangential y - z plane (parallel to the Si/SiO: interface) directions, Eox is the oxide electric field and ET is the energy level of the oxide electron trap measured from the oxide conduction band. W 2 is the square of the tunneling transition matrix element. The density-ofstates of the oxide trap as a function of trap energy, DoT(ET~ ), is calculated from the slope of the charged trap density vs oxide field curve, Onor/OEox. It can be shown that Onox/dEox measured in the isochronal electric-field-stimulated-emission technique is proportional to DoT(ETa)[31,32]:

~nor / OEox

(3

~

(1 -- e-~t)DoT(ET) dET,

noT(t ) =

emission

The oxide field dependence of detrapping via tunnel emission measured on BiMOS devices and shown in Fig. 5 was employed in a new electric-fieldstimulated emission (EFSE) technique developed by Thompson and Nishida[31,32] to characterize the tunneling emission of electrons from oxide traps and to analyze the energy spectrum of oxide traps. In this technique: (1) the oxide electron traps are first charged at a constant temperature and low oxide electric field by substrate electron injection into the gate oxide; (2) the electron injection is stopped and the BiMOS is cooled to 77 K to minimize detrapping via thermal emission; (3) the oxide electric field (discharge field) is increased in 0.1 MV cm -~ steps and maintained constant for 300 s at each step; and (4) at the end of each 300 s step, the gate voltage at a drain current of 1.0 # A is measured. Figure 8 shows 1.5

the gate voltage shifts from the unstressed value vs discharge oxide electric field in three oxides first charged at 7 7 K and a low oxide electric field (1.25 M V c m - l ) , and then discharged by increasing the oxide electric field in 0.1 M V c m -1 steps[31]. These curves give the gate voltage shift due to differential detrapping of electrons from occupied oxide electron traps vs the oxide electric field via tunnel emission. The gate voltage shift decreases for an increasing discharge oxide electric field as the electrons are detrapped. The curve is nearly horizontal at low oxide fields and also at high oxide electric fields when relatively few electrons are detrapped and has a maximum slope at a discharge oxide field of approx. 2.0 MV cm-~ which occurs when the largest number of electrons are detrapped in a unit energy range[31]. The areal density of oxide traps which have emitted the trapped electron after a time t at a discharge oxide electric field Eox is given by[31,32]:

0.5

=

te-~'(O~o/OEox)DoT(ET) dET oc DoT(ETI ), ~ v '

0.0

1.0

2.0

,3.0

4.0

5.0

6.0

E o x /u MV/em)

Fig. 8. (Co/q)AV o measured at the end of each 300s discharge vs average discharge oxide electric field for 204/~ partial steam (950°C), 196/~ dry (900°C) and 150/~, dry/wet/dry (850°C) oxides. Substrate injection at 77 K to fill traps: Vox/Xo = 1.2 MV cm -I, 1o = 5.0 hA, injection time = 2000 s[31].

(ll)

where ET~ is obtained from

(O~OFT)[e- ~'(0o9/OEox)] = 0. Thompson and Nishida employed the isochronal electric-field-stimulated emission experiment to give the number of traps discharged in a constant discharge time interval of 300 s at a given electric field,

BiMOS and SMOSC for MOS parameter measurement 0'5// ........

I'' ....... I' . . . . . . . traps at Eox=1.2 to 2.0MV/cm and T~77K

l.~,.."~::::.,_.~_--'---.~---.-.~=~.~V~cm

o 1s ~ r ~ ' *

LU

' ~

o ~=1 s_uv/cm

• "

r.

III Eox=l.7MV/cm # Eox=l.8MV/cm " E°xi20MV/cm I

'

__~.nb="" , , , , , 1 , , O.O

.......

1.0

........

2.0 /(1 x 1012cm'iev1)

DOT

3.0

Fig. 9. Density of charged oxide electron traps DOTvs energy for 150 A dry/wet/dry (850°C) oxide with charging oxide electric field as a parameter. Substrate injection at gate voltages between 1.85 and 3.0 V to fill traps at 77 K[31]. Anor (Eoxi), from the voltage shift of the I o - Vc curve. The density-of-states is then computed from[31,32]: DoT(ETi) ~ [Anori+ l -- AnoTi]/[Exi+l

-

-

ETi]

= (Co/q)[AVoi+~ - A VGi]/ [ETi+, -- ETi],

(12)

at each trap energy in the oxide energy gap. The density-of-states of the charged oxide trap vs trap energy is plotted in Figs 9 and 10131]. W2=I0-24V2cm3155] and m x = m y = m ~ = m o was used[M]. Figure 9 shows the charging oxide electric field dependence (1.2, 1.5, 1.7, 1.8 and 2.0 MV cm -1) of the energy spectra of the charged oxide electron traps measured at 77 K to minimize thermal emission. The DoT reaches an asymptotic shape at the lowest oxide electric field, 1.2 MV cm -~, measured. Since thermal emission at 77 K is negligible for traps with thermal activation energies greater than 0.1 eV and since field-emission via electron tunneling from the trap-to-oxide conduction band is minimized at low oxide fields, the Dot energy spectrum at the lowest field (1.2 MVcm -l) and lowest temperature (77 K) measured is essentially the spectrum of the total oxide 0.5

Illllllllllll=llIJ[

I[llllll

** • 1.0 ~

iLl~ 1.5

2.0 0,0

Eox=l.2MV/cm

7

7

•

K

ARGE TRAPS T=77 K CHARGE TRAPS T= 110 K

• CHARGETRAPST= 150 K e CHARGETRAPST=200K

DOT

2.0

electron traps. This curve is found to peak at about 0.9 eV below the bottom of the oxide conduction band[31]. If the Si-to-SiO2 band-to-band (rather than band-to-band in SiO2) tunneling electron mass reported by Weinberg[56], mx = my = m~ = 0.5m0, were used, the peak shifts to 1.2 eV. Figure 10 shows the temperature dependence (77, 110, 150 and 200 K) of the energy spectra of the charged oxide traps at the lowest oxide electric field, 1.2 MV cm-~. Since fielddependent tunnel emission is minimized at low oxide electric field, the decrease in charged oxide traps with increasing temperature is due primarily to thermal emission. The fraction of oxide traps charged at a given temperature (1 + etq/a,J)-l[21] where tr, is the electron capture cross-section, J is the oxide current density and et is the thermal emission rate. A thermal activation energy of about 0.4 eV was calculated by Thompson and Nishida[31] from the reduction in trapped charge from 77 to 150 K in EFSE measurement and about 0.3 eV by Ning[19] from dVG/dt at constant conductance, gd in thermally-stimulated emission measurement for these shallow oxide traps. The difference in the trap energy, 0.9 eV, and the thermal activation energy is attributed to lattice relaxation during thermal activation, i.e. the Jahn-Teller effect[31]. The ratio of trap energy to thermal activation energy, 2.2, was found to agree very well with the Mott-Gurney ratio[57] of the static-to-high-frequency dielectric constant of SiO2, 1.9131]. 3. a.c. PULSED SUBSTRATEELECTRON INJECTION VIA SOURCED-MOS CAPACITOR(SMOSC) The sourced MOS capacitor (SMOSC) is a drainless metal-oxide-Si transistor. Equivalently, a MOS transistor may be operated as a SMOSC by connecting the source and drain electrodes. Substrate injection is obtained by forward-bias pulsed electron injection. This injection structure and technique was suggested by Howard to Ning[l 9]. The unique feature of the SMOSC is its simple structure compared to BiMOS, while still allowing independent control of the oxide electric field, gate injection current and the electron energy distribution. A standard MOS transistor or large-area capacitor with a single diffused area may be used with varying substrate resistivity, oxide thickness and oxidation process. This makes the SMOSC a viable test structure to measure and monitor oxide properties in an industrial manufacturing application. The structure and forward-bias injection are discussed in the next section. 3.1. Structure

,~,~,,,I,,,,,L,,,[,,,,,,,, 1.0

365

5.0

/(1 xlOl=crn=eV-1)

Fig. 10. Density' of charged oxide electron traps DoT vs energy for 150 A dry/wet/dry (850°C) oxide with charging temperature as a parameter. Substrate injection at temperatures between 77 and 200K to fill traps at 1.2MVcm -t oxide electric field[31].

A cross-section of the SMOSC is shown in Fig. 11. A positive voltage is applied between the gate and the source to induce a surface inversion layer underneath the gate oxide and give an oxide electric field. Figure 12 illustrates the energy band diagram during one injection cycle. During the first half of the cycle,

366

TOSHIKAZU NISHIDA

SOURCE

SOURCE ~ATE

I----'1

Inversiffnlayer Spacechargelayer P-epitaxiellayer P+ eubstrate Vsub(t) ~3~t

(~

Fig. l l. Cross-section of p-epitaxial layer n-channel sourced-MOSC substrate injector test structure. the n ÷ source-n-inversion layer/p-epitaxial layer junction is forward biased. Minority carriers (electrons) are injected from the n ÷ source and n-inversion layer into the p-epitaxial substrate. In the second half of the cycle, the junction is reverse-biased. Electrons located in the Si space-charge layer below the gate oxide are accelerated towards the Si/SiO2 interface. Those electrons that gain kinetic energy in excess of the barrier height are injected into the gate oxide. Therefore, the gate oxide current is controlled independently from the oxide electric field by the pulsed forward-bias technique in SMOSC. The duty cycle and the magnitude of the forward bias are adjusted in a feedback loop to maintain a constant gate current. 3.2. Fabrication

Polycrystalline Si gate sourced-MOS capacitor (SMOSC) test structures were fabricated on an oxidized (100) oriented p - / p ÷ substrate[23]. The p - / p ÷ epitaxial wafer was implanted with 70 keV B at a dose

N+ Poly SiO 2

of 1.76 x 1013B atmcm -2. The implant increases the surface concentration for increased injection efficiency during hot electron injection. Nominal 200/~ gate oxides were grown at 920°C in dry oxygen ambient with 0, 3, 6 and 9% HC1. Gate oxidation was followed by deposition of a 5500/~ thick polysilicon layer that was doped by POCI 3. The oxidized wafers with a polysilicon layer were then processed to fabricate the self-aligned n ÷ polysilicon gate SMOSC test structures. The source and drain junctions were implanted with 100 keV P at 1 x 1015cm -2 dose. The implant was annealed at 850°C and followed by a drive-in diffusion at 950°C. Contact windows for source and gate were patterned and etched into the polysilicon and oxide. High-purity VLSI-MOS grade AI was then thermally evaporated from a shuttered resistance-heated W boat. The contacts were defined by etching away the excess A1. After dicing the wafer slice, die attach on a TO-5 header was performed using an Ag epoxy. Gold wires 1 mm in diameter were bonded by ultrasonic compression between the bonding posts and bonding pads. 3.3. Measurement and results

The pulsed a.c. electron injection stress technique has been employed on the SMOSC test structure to characterize electron trapping at 77 K, first investigated by Ning[19], and the oxide field dependence of trap charging and generation rate at oxide field strengths of 4 - 7 M V c m -~ at room temperature (294 K)[23]. The pulsed substrate injection voltage is periodically interrupted to measure the highfrequency capacitance-voltage (HFCV) curves. The flatband and threshold voltage shifts are extracted from the HFCV curves as a function of the gate electron fluence.

N+ Poly Si02 P-Type Epitaxial Si

P-Type Epitaxial Si

•~1~ ,~1~

~1~ ~1~ , ,

/

r~c

EF Ec

J

¢,~oooeeeee FN oooooo

Ev

oe e

Ec o

-

Fp Ev

~'

EF Ec

-

E

/

•

Vn _

...I-

20tas

sokH

"1

Fig. 12. Energy band diagram for SMOSC during one injection cycle.

t

BiMOS and SMOSC for MOS parameter measurement 0.05

.... I .... T = 294K

I ....

0.45

I a ~.,~-'='~ ~,q,~-~

0.(~ ~

~>

'

'

'

'

I '

367 '

'

'

I '

A EOX : 4 tdV/cm o t o x : 5 MY/era 0.3 - t= Eox = 6 MV/cm = 0

'

'

'

I ' ~ ' ~

~)~''~...~.~....~. ~ ~..---"~_~.~ ,~,,/~.~,,..,......~ ~

0.15

>

4<3

~

-0.1 k-

~

~

'qlP~' -0.15' 0.0

5.0 Ninj/(1

>

.

o Eox : 4 . 8 5 . V Z c r n

eEox=5,731dV/cm ~, Eox : 6.14 MV~cm • Eox = 6.61 MV/cm 10.0 016~/cm

15.0

0.0 T = 294K -o.15 , , , , I , , , , I p , , , I , , , , 0.0 5.0 10.0 15.0 20.0

20.0

N~nj/(1017~/cm 2)

2)

Fig. 13. Flatband voltage shift vs electron fluence at low fluence (<2 x 1 0 1 7 c m - 2 ) indicating positive charging for 228/~ dry oxide with 3% HCI as a function of oxide electric field between 4.85 and 6.61 MV cm-t[23].

Fig. 14. Flatband voltage shift vs electron fluence at intermediate fluence (<20 x 1017cm-2) indicating turnaround and negative charging for 228/~ dry oxide with 3% HCI as a function of oxide electric field between 4.0 and 7.0 MV cm-t[23].

3.3.1. OxidefieM dependence. Figure 13 shows the flatband voltage shift vs electron injection fluence for the 3% HC1 228/~ dry oxide as a function of oxide electric field between 4.85 and 6.61 MV cm-~[23]. At low fluences ( < 2 x 1017cm -2) and for oxide fields greater than 4.85 M V c m -~, an initial negative flatband voltage shift is observed which indicates positive charge trapping. The positive charge generation rate is dependent on the oxide thickness and oxide electric field. Positive charge generation at low fluence is also observed in the BiMOS test structure in thicker oxides ( > about 200 ~,) at high oxide electric field. The magnitude of the negative flatband voltage shift increases with increasing oxide electric field above 4.85 M V c m -1. Several models for positive charge trapping have been proposed. These include impact generation of electron-hole pairs in the oxide, in the polysilicon gate and excitation of interfacial plasmons at the gate-conductor/oxide interface by energetic electrons which then decay into electronhole pairs, and the hole is injected into the gate oxide[58]. As the electron fluence increases, the fiatband voltage shift becomes less negative and then positive, indicating the net charge in the oxide changes sign and turns around. The turnaround and electron trapping is clearly seen in Fig. 14 where the flatband voltage shift is plotted vs electron fluence up to 20 x 1017cm -2 for the 3% HC1 dry oxide as a function of oxide electric field between 4.0 and 7.0 MV cm-1123]. Electron trapping dominates at the higher electron injection fluences. The field dependence of the flatband voltage shift on a SMOSC test structure is consistent with that measured using the BiMOS test structure. The flatband voltage shift nearly saturates at a lower oxide electric field ( 4 M V c m -~) after large injection fluence. This is attributed to the steady-state density of charged oxide traps due to the opposing charging and discharging rates of existing traps as discussed in Section 2.3.1 for BiMOS. At higher oxide fields (4, 6 and 7 MV cm-~), the flatband voltage does not saturate, and the slope of the flatband voltage shift with electron fluence

increases with an increase in oxide field. The nonsaturation indicates the generation and charging of new oxide electron traps. Figure 15 shows the threshold voltage (Vs=2VF) vs electron fluence curves as a function of oxide electric field between 4.0 and 7.0 MV cm-~[23]. The threshold voltage shift is similar to the flatband voltage shift. The difference is due to interface traps charged between the threshold and flatband.

3.4. Analysis and discussion A detailed characterization of the oxide field dependence is necessary to evaluate the effect of the oxidation process on gate oxide instability. Section 3.3.1 provided examples of measurements of the oxide field dependence for a given oxidation process condition. The simple SMOSC structure allows the use of SMOSC to characterize, evaluate and monitor process variations. The chlorine dependence of the high-field degradation of dry oxide was investigated using the SMOSC[23]. In Fig. 16, the threshold voltage shift normalized to the measured oxide capacitance is plotted vs electron fluence for nominal 200/~ oxides grown at 920°C with 0, 3, 6 and 9% HCi 0.45

'

'''

I '

'

'

'

I '

'

'

'

zxEox = 4 MV/cm o Eox = 5 MV/cm 0.5 - o Eox = 6 MV/cm

I '

'

''-

~ "

--

0.15 > 0.0 T = 294K -0.15 , 0.0

,

,

,

[

5.0

,

,

,

,

I

,

10.0

,

,

,

I

15.0

,

,

,

,

20.0

N,nj/(1017~/cm 2) Fig. 15. Threshold voltage shift vs electron fiuence at intermediate fluence (<20 x 10]Tcm-~) indicating turnaround and negative charging for 228 ,~ dry oxide with 3% HC1 as a function of oxide electric field between 4.0 and 7.0 MV cra-1123].

368

TOSHIKAZU

0.4

'

'

~

'

I

'

'

'

'

I

'

'

'

'

I

'

'

'

.

-~-'~o 0.3 0.2 17" "~ C.~ <3

0.1

0,(;

-0.1

~

~a.q~

o HCI=3~. D HCI=6~

r

¢.HC1=9~

,

~ ,

I , 25.0

,

Ninj(1

,

,

I , , 50.0

017:~/C

,

, I , 75.0

,

,

, 100.0

m 2)

Fig. 16. Chlorine dependence of threshold voltage shift vs electron fluence at high-oxide electric field, 7.0 MV cm -L, for 0, 3, 6 and 9% HCI in oxidation ambient at 920°C[23]. in dry oxygen ambient and subjected to electron injection stress at 7 MV c m - 1 oxide electric field. The 6 and 9°/'0 HCI oxides were found to have a smaller threshold voltage shift at 7 M V c m -~ oxide field compared to the 0 and 3°/'0 HCI oxides[23]. Chlorine may replace the weaker hydrogen bonds at the Si/SiO2 interface = S i O - - C I and Si---C1 or bond to hydrogen as ~ S i O - - H - - C 1 and ~ S i - - H - - C 1 via hydrogen bond[59]. The S M O S C may also be employed to investigate the effect of substrate resistivity on M O S transistor instability since the injection efficiency for pulsed a.c. substrate injection is not as strongly dependent on substrate resistivity compared to the BiMOS d.c. substrate injection.

4.

wafers with a polysilicon gate layer were provided by industrial mentors and collaborators. The author wishes to thank the industrial mentors for their continued support, his graduate students Scott E. Thompson and Jack T. Kavalieros for data described in this article, Yi Lu and K. Michael Han for research participation, and Professor C. T. Sah for helpful suggestions.

REFERENCES

T = 294K ,

0.0

-

NISHIDA

C O N C L U S I O N S

The substrate injection methods employing d.c. bipolar injector (BiMOS) and pulsed a.c. forwardbias injection (SMOSC) have been discussed in detail. These structures provide comprehensive control of key M O S stress parameters, the oxide electric field, gate injection current and electron energy. The physics of the oxide electric field and temperature dependencies on oxide trap charging, discharging and generation have been delineated. Variation of the temperature and oxide field in controlled measurements have shown the importance of both temperature-dependent thermal emission and field-dependent tunnel emission processes on the determination of the steady-state oxide charge. The control of the oxide electric field during charging and discharging experiments allows fundamental studies of the tunnel emission of electrons from occupied oxide traps and analysis of their energy distribution in the electricfield-stimulated-emission technique. Furthermore, these test structures provide an additional tool for monitoring the effect of process chemistry on the electrical properties and stability of the gate oxide in VLSI manufacturing applications. Acknowledgements--This work is supported by the Semiconductor Research Corporation under Contract 91-SJ-145 with the author at the University of Florida. Oxidized

1. M. M. Atalla, M. Tannenbaum and E. J. Scheibner, Bell Syst. Tech. J. 38, 123 (1959). 2. For a comprehensive review on the evolution history of MOS transistor, see C. T. Sah, Proc. 1EEE 76, 1280 (1988). 3. J. Moll, 1959 WESCON Record Part 3, p. 32 (1959). 4. L. M. Terman, Solid-St. Electron. 5, 285 (1962). 5. E. H. Nicollian and J. R. Brews, MOS Physics and Technology, Chaps 4 and 5, pp. 99-234. Wiley, New York (1982). 6. C. T. Sah, J. Y. C. Sun and J. J. T. Tzou, J. appl. Phys. 54, 2547 (1983). 7. C. T. Sah et al., comprehensive review in datareview handbook, Properties of Silicon, Sections 17.1-17.5, 17.7-17.21, pp. 497-639. INSPEC, London (1988). 8. E. H. Snow, B. E. Deal, A. S. Grove and C. T. Sah, J. appl. Phys. 36, 1664 (1965). 9. T. H. Ning, P. W. Cook, R. H. Dennard, C. M. Osburn, S. E. Schuster and H. N. Yu, IEEE Trans. Electron Dev. ED-26, 346 (1979). 10. R. H. Dennard, Physica 129B, 3 (1985). 11. D. R. Young, Proc. Symp., 173rd Mtg of The Electrochem. Soc., p. 487. Plenum, New York (1988). 12. C. T. Sah, Properties of Silicon, Sections 17.16, 584. INSPEC, London (1988). 13. A. Goetzberger and E. H. Nicollian, Appl. Phys. Lett. 9, 444 (1966). 14. M. Lenzlinger and E. H. Snow, J. appl. Phys. 40, 278 (1969). 15. T. H. Ning, C. M. Obsurn and H. N. Yu, J. appl. Phys. 48, 286 (1977). 16. C. T. Sah and C. C. H. Hsu, In Properties of Silicon, Section 17.5, p. 532. INSPEC, London (1988). 17. D. A. Buchanan and D. J. DiMaria, J. appl. Phys. 67, 7439 (1990). 18. C. T. Sah, Solid-St. Electron. 33, 147 (1990). 19. T. H. Ning, J. appl. Phys. 49, 5997 (1978). 20. C. C. H. Hsu, T. Nishida and C. T. Sah, J. appl. Phys. 63, 5882 (1988). 21. T. Nishida and S. E. Thompson, J. appl. Phys. 3986 (1991). 22. T. Nishida and S. E. Thompson, 1991 Int. Reliability Physics Syrup. 29th Annual Proc., p. 310. IEEE, New York (1991). 23. T. Nishida, S. E. Thompson and J. T. Kavalieros, 1991 Material Research Society Spring Meeting, Syrup. G: Material Reliability Issues in Microelectronics, Proc., Vol. 225, p. 271. Materials Research Society, Pittsburg (1991). 24. T. Nishida, S. E. Thompson, J. T. Kavalieros, Y. Lu and K. M. Hart, Proc. Ninth Biennial University/ Government~Industry Microelectronics Syrup., p. 84. IEEE, New York (1991). 25. C. T. Sah, IRE Trans. Electron Dev. ED-9, 94 (1962). See also Ref.[2] and 1963 McGraw-Hill Yearbook of Science and Technology, p. 560. McGraw-Hill, New York (1963). 26. J. F. Verwey, J. appl. Phys. 44, 2681 (1973). 27. C. C. H. Hsu, T. Nishida and C. T. Sah, Unpublished (1987). 28. N. Yasuda, H. Nakamura, K. Taniguchi, C. Hamaguchi and M. Kakumu, Jpn. J. appl. Phys. 27, L2395 (1988). 29. C. C. H. Hsu, L. K. Wang, M. R. Wordeman and T. H. Ning, IEEE Electron Dev. Lett. EDL-10, 327 (1989).

69,

BiMOS and SMOSC for MOS parameter measurement 30. C. C.-H. Hsu, D. S. Wen, M. R. Wordeman, Y. Taur and T. H. Ning, In Technical Digest of Int. Electron Devices Mtg 1989, p. 75. IEEE, New York (1989). 31. S. E. Thompson and T. Nishida, Appl. Phys. Lett. 58, 1262 (1991). 32. S. E. Thompson and T. Nishida, J. appl. Phys. In press. 33. B. Eitan, D. Frohman-Bentchkowsky, J. Shappir and M. Balog, Appl. Phys. Lett. 411, 523 (1982). 34. Y. Nissan-Cohen, J. Shappir and D. FrohmanBentchkowsky, J. appl. Phys. 54, 5793 (1983). 35. M. S. Liang, C. Chang, W. Yang, C. Hu and R. W. Brodersen, In Technical Digest of lnt. Electron Devices Mtg 1983, p. 186. IEEE, New York (1983). 36. Y. Nissan-Cohen, J. Shappir and D. FrohmanBentchkowsky, J. appl. Phys. 57, 2830 (1985). 37. Y. Nissan-Cohen, J. Shappir and D. FrohmanBentchkowsky, J. appl. Phys. 58, 2252 (1985). 38. Y. Nissan-Cohen, J. Shappir and D. FrohmanBentchkowsky, J. appl. Phys. 60, 2024 (1986). 39. T. H. Ning and H. N. Yu, J. appl. Phys. 45, 5373 (1974). 40. D. J. DiMaria, Appl. Phys. Lett. 51, 655 (1987). 41. D. J. DiMaria and J. W. Stasiak, J. appl. Phys. 65, 2342 (1989). 42. M. Waiters and A. Reisman, J. appl. Phys. 67, 2992 (1990). 43. D. J. DiMaria, J. appl. Phys. 68, 5234 (1990). 44. A. Badihi, B. Eitan, I. Cohen and J. Shappir, Appl. Phys. Lett. 40, 396 (1982).

369

45. M. S. Liang and C. Hu, In Technical Digest of Int. Electron Devices Mtg 1981, p. 396. IEEE, New York (1981). 46. D. J. DiMaria, T. N. Theis, J. R. Kirtley, F. L. Pesavento, D. W. Dong and S. D. Brorson, J. appL Phys. 57, 1214 (1985). 47. S. D. Brorson, D. J. DiMaria, M. V. Fischetti, F. L. Pesavento, P. M. Solomon and D. W. Dong, J. appl. Phys. 58, 1302 (1985). 48. D. J. DiMaria, M. V. Fischetti, E. Tierney and S. D. Brorson, Phys. Rev. Lett. 56, 1284 (1986). 49. D. J. DiMaria, M. V. Fischetti, M. Arienzo and E. Tierney, J. appl. Phys. 60, 1719 (1986). 50. A review is given by C. T. Sah, In Properties of Silicon, Section 17.11, p. 570. INSPEC, London (1988). 51. C. T. Sah, S. C.-S. Pan and C. C.-H. Hsu, J. appl. Phys. 57, 5148 (1985). 52. C.T. Sah, W. W.-L. Lin, C. C.-H. Hsu and S. C.-S. Pan, Appl. Phys. Lett. 48, 1736 (1986). 53. C. T. Sah, IEEE Trans, Electron Dev. ED-52, 795 (1964). 54. C. T. Sah, Proc. IEEE 55, 654 (1967). 55. C. T. Sah, Phys. Rev. 123, 1594 (1961). 56. Z. A. Weinberg, Solid-St, Electron. 20, I1 (1977). 57. N. F. Mort and R. W. Gurney, Electronic Processes in Ionic Crystals. Clarendon, Oxford (1940). 58. M. V. Fischetti, Phys. Rev. B31, 2099 (1985). 59. A. J. Chen, S. Dadgar, C. C.-H. Hsu, S. S.-C. Pan and C. T. Sah, J. appl. Phys. 58, 1262 (1986).