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Static characterization and parameter extraction in MOS transistors
ELSEVIER
Microelectronic Engineering 40 (1998) 181-186
Static characterization and parameter extraction in MOS transistors Kjell O. Jeppson Chalmers University of Technology, School of Electrical and Computer Engineering Department of Microelectronics, Solid-State Electronics Laboratory S-412 96 Grteborg, Sweden Abstract: This paper describes the basic concepts for efficient parameter extraction. The focus is on efficiency in parameter extraction and often analytical manipulation of the model equations can be used to increase efficiency. In particular, extraction of the linear region miniset parameters, and how series resistance and effective geometry can be derived from these parameters, will be discussed. Furthermore, extraction of the saturation and subthreshold region parameters are discussed and the importance of the underlying model is highlighted. 1. I N T R O D U C T I O N Improved methods and techniques for MOSFET characterization is continously developed as device geometry scales deeper into the submicron regime. In this paper, an introduction to the static characterization of MOSFET devices will be presented. Techniques and methods currently used for the static characterization and parameter extraction of advanced MOS transistors will be reviewed. This concerns, for example, the extraction of device parameters like the threshold voltage, mobility, series resistance, effective channel length and width, etc.
be used to denote a value of the transistor gain [3. Another simple but somewhat arbitrary method to determine the threshold voltage is to measure the gate voltage for which a certain low current flows through the transistor. This method is usually called the constant current method. The current value is usually normalized by the channel width-to-length ratio to account for the aspect ratio of the channel. These methods and the relation of the extracted threshold voltage to the threshold voltage defined by the surface inversion condition (t~s= 2t~B) is discussed by Deen and Yan [1].
2.2 The underlying transistor model 2. M O S F E T
PARAMETER
EXTRACTION
2.1 Threshold voltage When characterizing an MOS transistor, the threshold voltage, being the gate voltage when the transistor starts to conduct, is very often the first parameter to be determined. Assuming a linear transistor model, for strong inversion and small drain voltages, the threshold voltage could be determined by linear extrapolation to zero drain current. However, due to subthreshold currents and high field mobility degradation this linear region could be hard to identify. Therefore, the threshold voltage is most commonly determined using the so-called peak-gm method. In this method the threshold voltage is determined by extrapolating the IDS vs VGS characteristics in the linear region to zero current using the tangent at the maximum slope. The slope of the tangent could also
The importance of extracting transistor parameters with respect to an underlying model has been discussed in great detail by McAndrew and Layman [2]. A simple, but yet accurate, transistor model suitable for serving as a basis for our discussions could be written
t,Gs-VTIDS =
atVDs'~r
),os
I+0(VGs.VT ) + ~VDs
(1)
where 13is the transistor gain, V T the threshold voltage, 0 the mobility reduction factor due to the transverse electric field, ~ models the velocity saturation, and at models the bulk charge bias dependence. Initially, we usually assume ~ and at be equal to zero, and use measurements in the linear region to determine the other so-called miniset parameters V T, 1~,
0167-9317/98/$-see front matter Copyright © 1998 Elsevier Science B.V. All rights reserved. PII: S0167-9317(98)00269-X
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K.O. Jeppson / Microelectronic Engineering 40 (1998) 181-186
and 0 in the model [3]. However, once parameters tx and ~ are known their values can be inserted, and used to (slightly) modify the values extracted for V T, 6, and 0. The transistor model in (1) applies for the intrinsic MOSFET. In the case of extrinsic source and drain series resistances R S the internal voltages should be used. However, most of the influence of a series resistance can be accomplished for by replacing 0 with an effective 0"=0+213RS. 2.3 Extraction of miniset parameters Several methods to extract the miniset parameters have been suggested through the years. Bauza and Ghibaudo [4] rely on the transconductance gm = ~IDs/3VGs for extracting the miniset parameters. First, an IDS/~ gm vs VGT plot (where VGT =VGsVT) is used to yield 13 and V T, while 0 is obtained from l/~/g m (or IDs/gmVGT -1)/VGT ) vs VGT plots. Other methods use the peak-g m method to determine the threshold voltage before extracting I] and 0. Numerous such methods have been suggested - one is to use Rtot=VDs/IDs vs 1/VGT plots. The CMP method [5] is a similar method where ~ and 0 are determined from the slope and intercept of 1/VGT vs 1/IDs using linear regression. The threshold voltage is initially determined by the peak-g m method but then the extraction of ~ and 0 is repeated for a number of assumed values of V T in the vicinity of the value determined by the peak-g m method. Those parameter values resulting in a minimum difference between measured and calculated currents is then chosen for the miniset parameters. However time-consuming the CMP method focuses our attention on the fact that the miniset parameters should be extracted in conjunction rather than in isolation for minimum error. The threshold voltage defined by the peak-g m method is a relatively arbitrary definition of the threshold voltage not related to any underlying model. Therefore this value of V T does not necessarily result in a minimum error fit between measured and simulated data. As already pointed out, the importance of extracting model parameters with respect to an underlying model has been discussed in great detail by McAndrew and Layman [2]. In their own method they used a multi-step optimization procedure (using a generalpurpose nonlinear optimizer) to determine the model parameters.
2.4 Direct extraction A. The linear region Single device extraction. A rapid and more convenient method for simultaneous extraction of all miniset parameters V T, [~ and 0 has been presented by Karlsson and Jeppson [6]. The method is based on earlier work by Hamer [7] and Tuinhout et al. [8]. By introducing three observables,
a=
tx b=VT + ~- VDS and
1 C=VT- ~ ; ,
(2)
the current model can be transformed into a simple rational function, VGS-b IDS = a VGS. - - c VDS,
(3)
from which a, b, and c (and thereby VT, [$ and 0) can be easily determined using nonlinear optimization. By repeating this procedure for each single device the miniset parameters for this particular device or device geometry can be extracted. These parameter values are then saved for subsequent geometry processing. The single device parameter extraction procedure can also be repeated for different substrate biases. From such measurements the bias dependence of VT, 1~and 0 can be determined together with the parameter o~. In BSIM3v3 [9], for instance, the basic threshold voltage for a long channel device is given by VT = VTO+K1 [(¢s-Vbseff)1/2-¢s 1/2]_K2Vbseff (4) where VTO, K1, and K2 are the voltage-independent threshold model parameters and Vbseff=VBS is an "effective" substrate bias [9, eq. (2.1.26)]. Series resistance extraction. In their method Suciu and Johnston [10] plotted E=VGTRtot -
I+eWGT B
(5)
vs VGT to determine 076 and 1/1~(having determined VT by using the peak-g m method). In the next step, by plotting 0"/6 vs lib for a number of transistors having the same series resistances (and channel widths) but different channel lengths, they could determine the series resistance R S from the intercept with the ordinate.
K.O, Jeppson / Microelectronic Engineering 40 (1998) 181-186
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I
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I
¢/
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"" 030 0.25 O a~ 0.20 LL
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..Q O
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0 o
I
I
I
I
I
I
0.5 Gain [ m A N 2]
I
I
1.0
Fig. 1. The effective mobility reduction factor plotted versus the gain with the channel width as a parameter for n-channel devices. The series resistances are obtained from the slopes [6]. Their method could easily be improved by using the parameters determined by our method and then plotting 0" vs ~ to determine 0 and RS. See Fig. 1. Both of these methods determine the series resistance RS from a number of transistors having the same series resistance, assuming it is constant. Otten [11] and Raychaudhuri et al [12] have worked on methods to determine the series resistance using data from only one transistor. Geometry processing. Once the miniset parameters are known for a number of transistors of different geometry, the effective geometries can be determined from the transistor gain. The transistor gain is related to the effective geometry of the transistor through the relation • ,Wm-AW 13= K ~
(6)
where k" is the intrinsic transistor gain, W m the nominal (mask) channel width, Lm the nominal (mask) channel length and AW and AL are the channel narrowing and channel shortening, respectively. This model assumes that AW and AL are process induced parameters constant for all transistor geometries.
183
Equation (6), being a rational function, is of the same type as (3) which indicates that k', AW and AL can be determined by using the same nonlinear optimization procedure that yielded 13, VT and 0 earlier. This method opens the opportunity of determining one single value of AL (and AW) common for all geometries (see Fig. 2) while the conventional 1/I] method must be repeated for each channel width (length) and thereby yields one value of AL (AW) for each channel width (length). In older transistor models AW and AL are usually modeled as constants while the third generation transistor model BSIM3v3 offers the user the possibility of modeling a geometry (and bias) dependence of AW and AL. Iterative improvements. Once the series resistance is known, the internal voltages are also known and the extraction procedure can be repeated using the calculated internal voltages instead of the external voltages. From the new 0" vs ~ relationship a correction term to the series resistance can be obtained together with a new value of 0. This procedure can then be repeated until the R S correction term is negligible. This is usually obtained already after a few rounds, since only negligible improvements are expected with parameter extraction based on measurements well in the linear region (VGT>>VDS) The accuracy of the extraction procedure can also be increased by accounting for the body effect of each device. This can be done (using the same approximation as McAndrew and Layman) by repeating the single device parameter extraction step for a second substrate bias VSB to determine an approximation for Dv=OVT/OVsB. The threshold voltage shift AVT due to the body effect can then be taken as AVT = DVIDSRS,
(7)
and the parameters be reextracted using the expression x-b - VDS, IDS = a -y-c
(8)
where x=VGS- AVT and y=VGS-IDsRs-AVT. Again, with measurements performed deep into the linear region (VGT>>VDS) the body effect is not expected to alter the values of the extracted parameter more than marginally (since VGT>>RSIDS, AVT).
K.O. Jeppson / Microelectronic Engineering 40 (1998) 181-186
184
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5
10
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30
10
15
20
25
30
Channel Width [!am]
Channel Length [gm] Fig. 2. (a) Plots of the reciprocal gain ( l / t ) versus channel length, and (b) the gain (fi) versus channel width yields the channel shortening AL and channel narrowing AW, respectively [6]. The influence of the substrate bias on the mobility and the mobility reduction factor for each device can be handled similarly. If, by repeating the single device parameter extraction step at a second substrate bias, we find that the internal substrate bias IDsR S causes a shift A~=3[~/~VsB-RSIDS or A0=~0/~VSB. RSIDS of the transistor gain and mobility reduction factor, respectively, the model parameters could be reextracted using x=VGs-AVT+~I~(VGS
- VT-~
-~)
(9)
where [3(VDS) is the drain voltage dependent gain and IDSAT is the saturation current given by the linear region current model using VDS=VDSAT . As an example, some simple transistor models use [3(VDS) = [~(I+XVDs ) to model channel length modulation (CLM) while other models like BSIM use more complex expressions. Usually, not only the gain but also the threshold voltage VT is VDs-dependent this is to model the drain-induced barrier-lowering (DIBL). In BSIM1 [13] the saturation voltage is defined by using the velocity saturation condition which results in an expression of the following type,
and VDSAT y = V'GS- AVT - ~
(V'GS - VT).
(12)
(lo)
B. The saturation region Most transistor models define a saturation voltage, VDSAT, using the pinch-off or velocity saturation condition, for which the drain current (more or less) saturates. In the saturation region, i. e. for drain voltages VDS>VDSAT, most earlier generation transistor models use an expression of the following type to model the drain current, IDSAT IDS = NVDS) 13fVDSAT)
VGS-VT oCt-K- '
(11)
where K is a VGs-dependent variable. If we instead use the simplified pinch-off condition we obtain K=I. In BSIM1 the saturation current can then be written VGT2 IDSAT = [3 2~K '
( 13)
which is very much reminding of the square-law Shockley long-channel model (disregarding the voltage dependencies hidden in the model parameters). The saturation region miniset parameters V T, [5 and ~ can be determined for each drain voltage using nonlinear optimization. This "optimization" proce-
185
K.O. Jeppson / Microelectronic Engineering 40 (1998) 181-186
dure could either be performed using standard optimizers or be performed more efficiently using "direct methods" based on analytical manipulation of the model equations [8, 14]. Such a procedure is, in principle, a more advanced form of the ~Ir)s vs VGS extrapolation used to determine VT and [~ for long channel devices in the early seventies. See Fig. 3. More advanced (third generation) transistor models like BSIM3 use more complex smoothing functions (instead of joining two different current expressions) to avoid discontinuities in the transconductance expression (or its derivatives). One such smoothing function is given by the following expression for VDSeff, an effective drain voltage which, when used instead of the drain voltage, results in one single current expression valid in both the linear region and the saturation regions [9, eq. (3.6.4)]:
1
VDSeft= VDSAT- ~ { VDSAT - VDS - ~i + ~/(VDSAT- VDS- 6) 2 + 46VDSAT}.
(14)
However, extraction procedures similar to those described before still hold as shown by McCarthy et al. [15] for the Philips MOS model 9 which is another popular third generation MOS model [3, 16]. C. The subthreshoM region For the subthreshold region the subthreshold swing parameter, m, is extracted to guarantee the correct current slope in the subthreshold region, see Fig. 4. For improved modeling in the transfer region between subthreshold and saturation smoothing func-
J
r,.)
tions are used in modern MOSFET models. One such smoothing function is given by the following expression used in Philips MOS model 9 VGT VGT = 2mVt ln(1 + exp 2--~t )
(15)
where Vt=kT/q is the thermal voltage. More details about MOSFET modeling with SPICE and about parameter extraction can be found in the book by Floty [17].
2.5 Effective geometry and series resistance again Much effort has been spent through the years to extract reliable values for effective geometry and series resistance. An excellent review of different methods for measuring the effective channel length of MOSFETs has been presented by Ng and Brews [18]. McAndrew and Layman [2] have made extensive comparisons between different methods and their sensivity to measurement noise. One method that is often used is the TMC method proposed by Terada and Muta [ 19] and Chern et al. [20]. This is a method to separate the channel resistance from the series resistance, even if the series resistance is gate-voltage dependent (and not necessarily constant as we assumed in section 2.4). RS and AL are obtained from the intercept of Rtot vs L plots performed at different gate voltages. Brut [21] has shown that the VGs-dependence of RS and zS~Lcannot be simultanously obtained and proposed a new method [22]. A variation of this method was recently presented by Yamaguchi et
~
10"lI
10-2t 10-3[ e. 10-4[
105 t "
o
2
Drain Source Voltage Fig. 3. Model parameter extraction in the saturation region [14].
~-~ 10"6 o .~ 10-7
1o-81 10-90
1
2
3
4
5
Gate Source Voltage IV] Fig. 4. Model parameter extraction in the subthreshold region [14].
186
K.O. Jeppson / Microelectronic Engineering 40 (1998) 181-186
al. [23].
Jeppson et al. [24] used a similar technique to separate the channel resistance from the series resistance. From the so extracted channel resistance they could then determine the gate-voltage dependence of the effective gate width could be studied.
7. 8. 9. 10.
3. CONCLUSIONS The basic concepts for efficient parameter extraction have been described. The focus has been on "direct methods" using reduced datasets and analytical manipulation of the model equations. In particular, the linear and saturation region miniset parameters have been discussed together with the voltage swing parameter for the subthreshold region. Also, the importance of extracting transistor parameters with respect to the underlying transistor model has been discussed.
REFERENCES .
2. 3.
.
.
6.
M. J. Deen and Z. X. Yah, Solid-State Electronics, 33, 503-511, 1990. C. C. McAndrew and P. A. Layman, IEEE Trans. on Electr. Dev., 39, 2298-2311, 1992. A. J. Scholten and D. B. M. Klaassen, Proc. ICMTS, 77-82, 1998. See also: http:/! www. semiconductors.philips.com/Philips_Models. D. Bauza and G. Ghibaudo, Microelectronics Journal, 25, 41-61, 1994. See also: G. Ghibaudo, in course notes MIGAS, 1997. C. Ciofi, M. Macucci and B. Pellegrini, Solid-State Electronics, 33, 1065-1069, 1990. P. R. Karlsson and K. O. Jeppson, IEEE Trans. on Semiconductor Manufacturing, 9, 215-222, 1996. See also P. R. Karlsson, Ph. D. thesis, CTH, Gtiteborg, 1994.
11. 12. 13.
14.
15.
16.
17. 18. 19. 20.
21. 22. 23. 24.
M.F. Hamer, IEE Proceedings I, 133, 49-54, 1986. H . P . Tuinhout, S. Swaving, and J. J. M. Joosten, in Proc. ICMTS, 127-131, 1988. Y. Cheng et al., BSIM3v3 Manual, University of California, Berkeley, 1995, 1996. P.I. Suciu and R. L. Johnston, IEEE Trans. on Electron Devices, 27, 1846-1848, 1980. J. Otten, Ph.D. thesis, TU, Eindhoven 1995. A. Raychaudhuri, M. J. Deen, M. I. H. King, and J. Kolk, ESSDERC, 749-752, 1995. B.J. Sheu, D. L Scharfetter, P-K. Ko, and M-C Jeng, IEEE Journal Solid-State Circuits, 22, 558-566, 1987. P . R . Karlsson and K. O. Jeppson, IEEE Trans. on Electron Devices, 39, 2070-2076, 1992. See also: P. R. Karlsson and K. O. Jeppson, Analog Integrated Circuits and Signal Processing, 5, 199-212, 1994. K.G. McCarthy, E. V. Saavedra Diaz, D. B. M. Klaassen and A. Mathewson, in Proc. ICMTS, 127-131, 1998. R . M . D . A . Velghe, D. B. M. Klaassen, and F. M. Klaassen, IEDM Technical Digest, 485-488, 1993. D. Floty, MOSFET Modeling with SPICE, Prentice Hall, Inc., Upper Saddle River, 1997 K.K. Ng and J. R. Brews, IEEE Circuits and Devices Magazine, 6, 33-38, 1990. K. Terada and H. Muta, Jap. J. Appl. Phys., 18, 953-959, 1979. J . G . J . Chern, P. Chang, R. F. Motta and N. Godinho, IEEE Electron Device Letters, 1, 170-173, 1980. H. Brut, Ph.D. thesis, Grenoble Dec. 1996. H. Brut, A. Juge, and G. Ghibaudo, in Proc. ICMTS, 188-193, 1997. K. Yamaguchi, H. Asimiro, M. Yamawaki, and S. Asai, in Proc. ICMTS, 123-126, 1997 K . O . Jeppson, A. W. Bogren, and P. R. Karlsson, in Proc. ICMTS, 151-156, 1997.
Microelectronic Engineering 40 (1998) 181-186
Static characterization and parameter extraction in MOS transistors Kjell O. Jeppson Chalmers University of Technology, School of Electrical and Computer Engineering Department of Microelectronics, Solid-State Electronics Laboratory S-412 96 Grteborg, Sweden Abstract: This paper describes the basic concepts for efficient parameter extraction. The focus is on efficiency in parameter extraction and often analytical manipulation of the model equations can be used to increase efficiency. In particular, extraction of the linear region miniset parameters, and how series resistance and effective geometry can be derived from these parameters, will be discussed. Furthermore, extraction of the saturation and subthreshold region parameters are discussed and the importance of the underlying model is highlighted. 1. I N T R O D U C T I O N Improved methods and techniques for MOSFET characterization is continously developed as device geometry scales deeper into the submicron regime. In this paper, an introduction to the static characterization of MOSFET devices will be presented. Techniques and methods currently used for the static characterization and parameter extraction of advanced MOS transistors will be reviewed. This concerns, for example, the extraction of device parameters like the threshold voltage, mobility, series resistance, effective channel length and width, etc.
be used to denote a value of the transistor gain [3. Another simple but somewhat arbitrary method to determine the threshold voltage is to measure the gate voltage for which a certain low current flows through the transistor. This method is usually called the constant current method. The current value is usually normalized by the channel width-to-length ratio to account for the aspect ratio of the channel. These methods and the relation of the extracted threshold voltage to the threshold voltage defined by the surface inversion condition (t~s= 2t~B) is discussed by Deen and Yan [1].
2.2 The underlying transistor model 2. M O S F E T
PARAMETER
EXTRACTION
2.1 Threshold voltage When characterizing an MOS transistor, the threshold voltage, being the gate voltage when the transistor starts to conduct, is very often the first parameter to be determined. Assuming a linear transistor model, for strong inversion and small drain voltages, the threshold voltage could be determined by linear extrapolation to zero drain current. However, due to subthreshold currents and high field mobility degradation this linear region could be hard to identify. Therefore, the threshold voltage is most commonly determined using the so-called peak-gm method. In this method the threshold voltage is determined by extrapolating the IDS vs VGS characteristics in the linear region to zero current using the tangent at the maximum slope. The slope of the tangent could also
The importance of extracting transistor parameters with respect to an underlying model has been discussed in great detail by McAndrew and Layman [2]. A simple, but yet accurate, transistor model suitable for serving as a basis for our discussions could be written
t,Gs-VTIDS =
atVDs'~r
),os
I+0(VGs.VT ) + ~VDs
(1)
where 13is the transistor gain, V T the threshold voltage, 0 the mobility reduction factor due to the transverse electric field, ~ models the velocity saturation, and at models the bulk charge bias dependence. Initially, we usually assume ~ and at be equal to zero, and use measurements in the linear region to determine the other so-called miniset parameters V T, 1~,
0167-9317/98/$-see front matter Copyright © 1998 Elsevier Science B.V. All rights reserved. PII: S0167-9317(98)00269-X
182
K.O. Jeppson / Microelectronic Engineering 40 (1998) 181-186
and 0 in the model [3]. However, once parameters tx and ~ are known their values can be inserted, and used to (slightly) modify the values extracted for V T, 6, and 0. The transistor model in (1) applies for the intrinsic MOSFET. In the case of extrinsic source and drain series resistances R S the internal voltages should be used. However, most of the influence of a series resistance can be accomplished for by replacing 0 with an effective 0"=0+213RS. 2.3 Extraction of miniset parameters Several methods to extract the miniset parameters have been suggested through the years. Bauza and Ghibaudo [4] rely on the transconductance gm = ~IDs/3VGs for extracting the miniset parameters. First, an IDS/~ gm vs VGT plot (where VGT =VGsVT) is used to yield 13 and V T, while 0 is obtained from l/~/g m (or IDs/gmVGT -1)/VGT ) vs VGT plots. Other methods use the peak-g m method to determine the threshold voltage before extracting I] and 0. Numerous such methods have been suggested - one is to use Rtot=VDs/IDs vs 1/VGT plots. The CMP method [5] is a similar method where ~ and 0 are determined from the slope and intercept of 1/VGT vs 1/IDs using linear regression. The threshold voltage is initially determined by the peak-g m method but then the extraction of ~ and 0 is repeated for a number of assumed values of V T in the vicinity of the value determined by the peak-g m method. Those parameter values resulting in a minimum difference between measured and calculated currents is then chosen for the miniset parameters. However time-consuming the CMP method focuses our attention on the fact that the miniset parameters should be extracted in conjunction rather than in isolation for minimum error. The threshold voltage defined by the peak-g m method is a relatively arbitrary definition of the threshold voltage not related to any underlying model. Therefore this value of V T does not necessarily result in a minimum error fit between measured and simulated data. As already pointed out, the importance of extracting model parameters with respect to an underlying model has been discussed in great detail by McAndrew and Layman [2]. In their own method they used a multi-step optimization procedure (using a generalpurpose nonlinear optimizer) to determine the model parameters.
2.4 Direct extraction A. The linear region Single device extraction. A rapid and more convenient method for simultaneous extraction of all miniset parameters V T, [~ and 0 has been presented by Karlsson and Jeppson [6]. The method is based on earlier work by Hamer [7] and Tuinhout et al. [8]. By introducing three observables,
a=
tx b=VT + ~- VDS and
1 C=VT- ~ ; ,
(2)
the current model can be transformed into a simple rational function, VGS-b IDS = a VGS. - - c VDS,
(3)
from which a, b, and c (and thereby VT, [$ and 0) can be easily determined using nonlinear optimization. By repeating this procedure for each single device the miniset parameters for this particular device or device geometry can be extracted. These parameter values are then saved for subsequent geometry processing. The single device parameter extraction procedure can also be repeated for different substrate biases. From such measurements the bias dependence of VT, 1~and 0 can be determined together with the parameter o~. In BSIM3v3 [9], for instance, the basic threshold voltage for a long channel device is given by VT = VTO+K1 [(¢s-Vbseff)1/2-¢s 1/2]_K2Vbseff (4) where VTO, K1, and K2 are the voltage-independent threshold model parameters and Vbseff=VBS is an "effective" substrate bias [9, eq. (2.1.26)]. Series resistance extraction. In their method Suciu and Johnston [10] plotted E=VGTRtot -
I+eWGT B
(5)
vs VGT to determine 076 and 1/1~(having determined VT by using the peak-g m method). In the next step, by plotting 0"/6 vs lib for a number of transistors having the same series resistances (and channel widths) but different channel lengths, they could determine the series resistance R S from the intercept with the ordinate.
K.O, Jeppson / Microelectronic Engineering 40 (1998) 181-186
0.35
I
I
I
¢/
W=2.4pm 3.2pm 4.8pm
"" 030 0.25 O a~ 0.20 LL
"~ 0.15 n" •
..Q O
0.10 0.05 I
0 o
I
I
I
I
I
I
0.5 Gain [ m A N 2]
I
I
1.0
Fig. 1. The effective mobility reduction factor plotted versus the gain with the channel width as a parameter for n-channel devices. The series resistances are obtained from the slopes [6]. Their method could easily be improved by using the parameters determined by our method and then plotting 0" vs ~ to determine 0 and RS. See Fig. 1. Both of these methods determine the series resistance RS from a number of transistors having the same series resistance, assuming it is constant. Otten [11] and Raychaudhuri et al [12] have worked on methods to determine the series resistance using data from only one transistor. Geometry processing. Once the miniset parameters are known for a number of transistors of different geometry, the effective geometries can be determined from the transistor gain. The transistor gain is related to the effective geometry of the transistor through the relation • ,Wm-AW 13= K ~
(6)
where k" is the intrinsic transistor gain, W m the nominal (mask) channel width, Lm the nominal (mask) channel length and AW and AL are the channel narrowing and channel shortening, respectively. This model assumes that AW and AL are process induced parameters constant for all transistor geometries.
183
Equation (6), being a rational function, is of the same type as (3) which indicates that k', AW and AL can be determined by using the same nonlinear optimization procedure that yielded 13, VT and 0 earlier. This method opens the opportunity of determining one single value of AL (and AW) common for all geometries (see Fig. 2) while the conventional 1/I] method must be repeated for each channel width (length) and thereby yields one value of AL (AW) for each channel width (length). In older transistor models AW and AL are usually modeled as constants while the third generation transistor model BSIM3v3 offers the user the possibility of modeling a geometry (and bias) dependence of AW and AL. Iterative improvements. Once the series resistance is known, the internal voltages are also known and the extraction procedure can be repeated using the calculated internal voltages instead of the external voltages. From the new 0" vs ~ relationship a correction term to the series resistance can be obtained together with a new value of 0. This procedure can then be repeated until the R S correction term is negligible. This is usually obtained already after a few rounds, since only negligible improvements are expected with parameter extraction based on measurements well in the linear region (VGT>>VDS) The accuracy of the extraction procedure can also be increased by accounting for the body effect of each device. This can be done (using the same approximation as McAndrew and Layman) by repeating the single device parameter extraction step for a second substrate bias VSB to determine an approximation for Dv=OVT/OVsB. The threshold voltage shift AVT due to the body effect can then be taken as AVT = DVIDSRS,
(7)
and the parameters be reextracted using the expression x-b - VDS, IDS = a -y-c
(8)
where x=VGS- AVT and y=VGS-IDsRs-AVT. Again, with measurements performed deep into the linear region (VGT>>VDS) the body effect is not expected to alter the values of the extracted parameter more than marginally (since VGT>>RSIDS, AVT).
K.O. Jeppson / Microelectronic Engineering 40 (1998) 181-186
184
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30
Channel Width [!am]
Channel Length [gm] Fig. 2. (a) Plots of the reciprocal gain ( l / t ) versus channel length, and (b) the gain (fi) versus channel width yields the channel shortening AL and channel narrowing AW, respectively [6]. The influence of the substrate bias on the mobility and the mobility reduction factor for each device can be handled similarly. If, by repeating the single device parameter extraction step at a second substrate bias, we find that the internal substrate bias IDsR S causes a shift A~=3[~/~VsB-RSIDS or A0=~0/~VSB. RSIDS of the transistor gain and mobility reduction factor, respectively, the model parameters could be reextracted using x=VGs-AVT+~I~(VGS
- VT-~
-~)
(9)
where [3(VDS) is the drain voltage dependent gain and IDSAT is the saturation current given by the linear region current model using VDS=VDSAT . As an example, some simple transistor models use [3(VDS) = [~(I+XVDs ) to model channel length modulation (CLM) while other models like BSIM use more complex expressions. Usually, not only the gain but also the threshold voltage VT is VDs-dependent this is to model the drain-induced barrier-lowering (DIBL). In BSIM1 [13] the saturation voltage is defined by using the velocity saturation condition which results in an expression of the following type,
and VDSAT y = V'GS- AVT - ~
(V'GS - VT).
(12)
(lo)
B. The saturation region Most transistor models define a saturation voltage, VDSAT, using the pinch-off or velocity saturation condition, for which the drain current (more or less) saturates. In the saturation region, i. e. for drain voltages VDS>VDSAT, most earlier generation transistor models use an expression of the following type to model the drain current, IDSAT IDS = NVDS) 13fVDSAT)
VGS-VT oCt-K- '
(11)
where K is a VGs-dependent variable. If we instead use the simplified pinch-off condition we obtain K=I. In BSIM1 the saturation current can then be written VGT2 IDSAT = [3 2~K '
( 13)
which is very much reminding of the square-law Shockley long-channel model (disregarding the voltage dependencies hidden in the model parameters). The saturation region miniset parameters V T, [5 and ~ can be determined for each drain voltage using nonlinear optimization. This "optimization" proce-
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K.O. Jeppson / Microelectronic Engineering 40 (1998) 181-186
dure could either be performed using standard optimizers or be performed more efficiently using "direct methods" based on analytical manipulation of the model equations [8, 14]. Such a procedure is, in principle, a more advanced form of the ~Ir)s vs VGS extrapolation used to determine VT and [~ for long channel devices in the early seventies. See Fig. 3. More advanced (third generation) transistor models like BSIM3 use more complex smoothing functions (instead of joining two different current expressions) to avoid discontinuities in the transconductance expression (or its derivatives). One such smoothing function is given by the following expression for VDSeff, an effective drain voltage which, when used instead of the drain voltage, results in one single current expression valid in both the linear region and the saturation regions [9, eq. (3.6.4)]:
1
VDSeft= VDSAT- ~ { VDSAT - VDS - ~i + ~/(VDSAT- VDS- 6) 2 + 46VDSAT}.
(14)
However, extraction procedures similar to those described before still hold as shown by McCarthy et al. [15] for the Philips MOS model 9 which is another popular third generation MOS model [3, 16]. C. The subthreshoM region For the subthreshold region the subthreshold swing parameter, m, is extracted to guarantee the correct current slope in the subthreshold region, see Fig. 4. For improved modeling in the transfer region between subthreshold and saturation smoothing func-
J
r,.)
tions are used in modern MOSFET models. One such smoothing function is given by the following expression used in Philips MOS model 9 VGT VGT = 2mVt ln(1 + exp 2--~t )
(15)
where Vt=kT/q is the thermal voltage. More details about MOSFET modeling with SPICE and about parameter extraction can be found in the book by Floty [17].
2.5 Effective geometry and series resistance again Much effort has been spent through the years to extract reliable values for effective geometry and series resistance. An excellent review of different methods for measuring the effective channel length of MOSFETs has been presented by Ng and Brews [18]. McAndrew and Layman [2] have made extensive comparisons between different methods and their sensivity to measurement noise. One method that is often used is the TMC method proposed by Terada and Muta [ 19] and Chern et al. [20]. This is a method to separate the channel resistance from the series resistance, even if the series resistance is gate-voltage dependent (and not necessarily constant as we assumed in section 2.4). RS and AL are obtained from the intercept of Rtot vs L plots performed at different gate voltages. Brut [21] has shown that the VGs-dependence of RS and zS~Lcannot be simultanously obtained and proposed a new method [22]. A variation of this method was recently presented by Yamaguchi et
~
10"lI
10-2t 10-3[ e. 10-4[
105 t "
o
2
Drain Source Voltage Fig. 3. Model parameter extraction in the saturation region [14].
~-~ 10"6 o .~ 10-7
1o-81 10-90
1
2
3
4
5
Gate Source Voltage IV] Fig. 4. Model parameter extraction in the subthreshold region [14].
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K.O. Jeppson / Microelectronic Engineering 40 (1998) 181-186
al. [23].
Jeppson et al. [24] used a similar technique to separate the channel resistance from the series resistance. From the so extracted channel resistance they could then determine the gate-voltage dependence of the effective gate width could be studied.
7. 8. 9. 10.
3. CONCLUSIONS The basic concepts for efficient parameter extraction have been described. The focus has been on "direct methods" using reduced datasets and analytical manipulation of the model equations. In particular, the linear and saturation region miniset parameters have been discussed together with the voltage swing parameter for the subthreshold region. Also, the importance of extracting transistor parameters with respect to the underlying transistor model has been discussed.
REFERENCES .
2. 3.
.
.
6.
M. J. Deen and Z. X. Yah, Solid-State Electronics, 33, 503-511, 1990. C. C. McAndrew and P. A. Layman, IEEE Trans. on Electr. Dev., 39, 2298-2311, 1992. A. J. Scholten and D. B. M. Klaassen, Proc. ICMTS, 77-82, 1998. See also: http:/! www. semiconductors.philips.com/Philips_Models. D. Bauza and G. Ghibaudo, Microelectronics Journal, 25, 41-61, 1994. See also: G. Ghibaudo, in course notes MIGAS, 1997. C. Ciofi, M. Macucci and B. Pellegrini, Solid-State Electronics, 33, 1065-1069, 1990. P. R. Karlsson and K. O. Jeppson, IEEE Trans. on Semiconductor Manufacturing, 9, 215-222, 1996. See also P. R. Karlsson, Ph. D. thesis, CTH, Gtiteborg, 1994.
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14.
15.
16.
17. 18. 19. 20.
21. 22. 23. 24.
M.F. Hamer, IEE Proceedings I, 133, 49-54, 1986. H . P . Tuinhout, S. Swaving, and J. J. M. Joosten, in Proc. ICMTS, 127-131, 1988. Y. Cheng et al., BSIM3v3 Manual, University of California, Berkeley, 1995, 1996. P.I. Suciu and R. L. Johnston, IEEE Trans. on Electron Devices, 27, 1846-1848, 1980. J. Otten, Ph.D. thesis, TU, Eindhoven 1995. A. Raychaudhuri, M. J. Deen, M. I. H. King, and J. Kolk, ESSDERC, 749-752, 1995. B.J. Sheu, D. L Scharfetter, P-K. Ko, and M-C Jeng, IEEE Journal Solid-State Circuits, 22, 558-566, 1987. P . R . Karlsson and K. O. Jeppson, IEEE Trans. on Electron Devices, 39, 2070-2076, 1992. See also: P. R. Karlsson and K. O. Jeppson, Analog Integrated Circuits and Signal Processing, 5, 199-212, 1994. K.G. McCarthy, E. V. Saavedra Diaz, D. B. M. Klaassen and A. Mathewson, in Proc. ICMTS, 127-131, 1998. R . M . D . A . Velghe, D. B. M. Klaassen, and F. M. Klaassen, IEDM Technical Digest, 485-488, 1993. D. Floty, MOSFET Modeling with SPICE, Prentice Hall, Inc., Upper Saddle River, 1997 K.K. Ng and J. R. Brews, IEEE Circuits and Devices Magazine, 6, 33-38, 1990. K. Terada and H. Muta, Jap. J. Appl. Phys., 18, 953-959, 1979. J . G . J . Chern, P. Chang, R. F. Motta and N. Godinho, IEEE Electron Device Letters, 1, 170-173, 1980. H. Brut, Ph.D. thesis, Grenoble Dec. 1996. H. Brut, A. Juge, and G. Ghibaudo, in Proc. ICMTS, 188-193, 1997. K. Yamaguchi, H. Asimiro, M. Yamawaki, and S. Asai, in Proc. ICMTS, 123-126, 1997 K . O . Jeppson, A. W. Bogren, and P. R. Karlsson, in Proc. ICMTS, 151-156, 1997.