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Effect of substrate generation current on oxide I-V measurement on p-type MOS structures
Solid.State Electronics Vol. 22, pp. 38%389 © Pergamon Press Ltd.. 1979. Printed in Great Britain
0038-1101/79/0401-0385/$02.00/0
EFFECT OF SUBSTRATE GENERATION CURRENT ON OXIDE I - V MEASUREMENT ON p-TYPE MOS STRUCTURES HAN-SHENG LEE Electronics Department, General Motors Research Laboratories, Warren, MI 48090, U.S.A. (Received 31 August 1978; in revisedform 12 October 1978) Abstract--The values of the bulk generation current and surface generation current extracted from slow ramp I- V and C-V measurements of p-type substrate MOS capacitors are found to be consistent with the results from transient capacitance measurement. The shape of the I- V curve for high positivegate biases is found to depend on the formation of a deep depletion region in the p-type substrate.
INTRODUCTION
With positive bias applied to the metal of a MetalOxide-Semiconductor (MOS) structure, electrons injected from the silicon side into the oxide and then subsequently collected by the metal gate are responsible for the observed Fowler-Nordheim (F-N) tunneling current at high electric fields[l]. Since electrons are the majority carriers in n-type substrates, injection electrons can be supplied very fast. Also, because of the formation of an accumulation layer beneath the gate oxide, almost all of the applied gate bias drops across the oxide. When the substrate is p-type, with high positive bias applied to the metal gate, injected electrons must be supplied through generation processes in order to maintain a steady oxide current. These electrons can be generated through the surface generation centers or the bulk generation centers of the substrate. In measurements of oxide leakage current of MOS capacitors as a function of gate voltage (I-V curves, gate positively biased, sample in darkness), we find an apparent dependence of the I-V characteristics on substrate conductivity type. Leakage currents on n-type substrate samples follow the Fowler-Nordheim model. I - V curves from p-type substrate samples differ from the n-type case and among each other. We find that the surface generation current is correlated with this substrate-type dependence and sample-to-sample variability of the p-type samples and can account for the major differences in the I-V characteristics of the two types of capacitors. In the present study, we applied a positive linear ramp bias to the gate of the p-type MOS capacitors. With the gate bias larger than the flat band voltage of the capacitor, a depletion region forms in the substrate. Initially, the width of the depletion region increased with the increasing of the gate bias. When the magnitude of the gate bias equals the threshold voltage of the capacitor, the depletion width reaches an equilibrium maximum value Wm and forms an inversion layer[2]. Since the voltage drop across the silicon depletion region is a function of the depletion width and the oxide is a good insulator, further increases in gate bias, after formation SSE Vol. 22, No. 4--C
385
of the inversion layer, will result in an increasing electric field in the gate insulator. The high oxide field causes current flow through the oxide, and if this leakage current is large enough, can result in the collapse of the inversion layer. The decrease of the surface electron concentration enhances the surface generation rate[2]. Without increasing the depletion width, the bulk of the depletion region can handle the oxide current up to (qN~Wml2"fb) per unit area[2] where N~ is the intrinsic carder concentration of silicon, Tb is the bulk generation time constant and q is the electron charge quantity. For illustration prupose, let us first consider the case where the surface generation rate is much smaller than the bulk generation rate in the entire I- V measurement range. For a given depletion region width, once the oxide leakage current reaches the generation rate limit of the bulk depletion region, any further increase of gate bias will be distributed across the insulator and depletion region in such a way that a steady oxide current can be maintained. In other words, the substrate will get part of the increased gate bias to widen the depletion region and the oxide receives the rest of the bias. With this widened depletion region, the bulk of the depletion layer can supply more oxide current than before. Additional increase of the gate bias will force the depletion region to widen further. Therefore, starting from the onset of the depletion region widening (with W,, as a reference), the oxide no longer receives the full amount of the increased gate bias. This will be reflected in the measured I-V curve and cause the curve to deviate from the shape extrapolated from the low gate bias data. At a given temperature and illumination, the gate bias, where this deviation appears, is determined by the doping level of the substrate, oxide thickness and Tb. The second limiting case we will consider is that the surface generation rate is much larger than the bulk generation rate and can supply the oxide current increase over the entire I - V measurement range. In this case, the width of the depletion region will not be increased (with W~ as a reference) due to the increase of the gate bias and the voltage drop in the silicon will be constant. Therefore, the measured I - V results will follow the low oxide
HAN-SIIENG LEE
386
current trend without deviation. The example of having increasing oxide current without increasing the substrate depletion width can be found in the measured results of Osburn and Weitzman[3] and Weinberg et al.[4]. The example of the other case, namely, with increasing depletion layer width to supply the leakage electrons through the bulk generation process can be found in Soiomon's results[5] where the measured I-V curves at high bias do not follow the same trend observed at lower voltages. At high gate bias the oxide current increases more slowly than observed in the low gate bias region. In the following, we will present three experimental results which show high, medium and low surface generation rates (as compared with the bulk generation rate) and its effect on the shape of the measured I-V curve. We correlate the measured I-V curves with the corresponding gate to substrate capacitance vs gate bias (C-V) results to find the relationship between the oxide current and the depletion width for the different surface generation rate conditions. The technique of correlating C-V and I-V results to study the substrate has been used by Hielscher and Preier[6] in their metal-silicon nitride-silicon samples, by Kar[7] in his thin oxide (46nm) tunnel MOS diodes and by MacIver[8] in his hybrid capacitors. In this study, we used thermally grown oxides 55 and 84 nm thick in MOS capacitors. EXPERIMENTAL RI~ULTS AND DISCUSSIONS
I ( 1o'lZA )
C Cox #440 i
-0.8
Dark [ P-type, ( 100 ), ( . . . . Light J 2 ohm-cm, 55 nm. Data points only.
0.6
X ] N-type, ( 100 ), 3 ohm
t 55 nm.
0.4
2
O.2
1
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---L._------10
Fig. 1. I-V
10
and C-V
20
30
40
O
50
GATEBIAS( VOLTS resultsof a p-type sample(No.440).Solid
curves were measured in the dark and the dashed curves were measured with sample exposed to room light. Several I-V data points (measured in the dark) for a n-type sample are also shown. ( IO'12A )
c/Cox 1 1490 Dark ~ P-type, ( 100 ) / Light) 2 ohm-cm, 55 nm.
0.8 Samples with <100> orientation, 3 ohm-era n-type and 2 ohm-cm p-type were used. The oxide of the MOS capacitors was thermally grown in dry oxygen ambient at -0.6 3 ll00°C together with 0.3% of HCI flowing and followed by a 15 min nitrogen gas anneal in the same tube. The oxide thicknesses used were 55 and 84nm. Aluminum "0.4, ............................. ,- 2 / dots of one micron thickness and 127 izm diameter were ~..o; E-beam evaporated on the oxide. After removing the ! L°'2 ) back oxide, one micron of aluminum was evaporated on the back side of the wafers. The wafers were then annealed in forming gas at 480°C for 30rain, diced, t, 0,0 l I t 0 -I0 0 10 20 30 40 5O mounted on TO-5 headers, bonded and capped. GATE BIAS ( VOLTS ) A Keithley model 26300 logarithmic picoammeter was used to measure the oxide current in the range of 10 - i s Fig. 2. I- V and C- V results of a p-type sample (No. 490). Solid A-10 - ' ° A. For the same oxide thickness, there was no curves were measured in the dark and the dashed curves were measured with sample exposed to room light. significant difference in the measured I-V curves for the n-type or p-type substrate samples provided the p-type n-type samples were measured in the dark. To make the substrate samples were exposed to room light (without figures clear, we only show several I - V data points for sample cap) during the measurement. These I-V curves the measured n-type samples. All the I-V results in this fit a Fowler-Nordheim plot with an effective mass ratio study were measured by the slow ramp method with a m*/mo=0.41 and a barrier height of 3.2eV. If the I-V measurement was done in the dark (with sample cap on), ramp rate of 6 mV/s. The C- V results were measured at I MHz using the same dc ramp rate for all samples. In substrate-dependent results occurred in some samples. In Fig. 1, both n-type and p-type samples had the same the following I-V measurements we used 10-'2 A scale instead of going through 10-'3 A-10 -'° range. Therefore, oxide thickness of 55 nm because the wafers were fabricated together. We did not see much difference between a better accuracy in data reading can be obtained and the the solid curve and the dashed curve. The capacitance substrate generation effect still can be domonstrated curve corresponding to the measured current ranges is clearly. In this scale, the oxide current was directly read still fiat. The substrate-independent result is similar to from the Keithley model 616 electrometer. t h e ' observation reported by Osburn and Weitzman[3] Figures 1-3 show the measured I-V and C-V results. The solid curves were measured in the dark (with and Weinberg et aL [4]. In Fig. 2 the samples also had a thickness of 55 nm, but the solid curves deviate from the cap on) and the dashed cruves were measured with samples exposed to the room light (with cap off). All dashed curves. We also noticed the two I-V curves
Effect of substrate generation current I ( lO"1 A )
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Fig. 3. I-V and C-V results of a p-type sample (No. 830). Solid curves were measured in the dark and the dashed curves were measured with sample exposed to room light. Several I-V data points(measuredin the dark)for a n-typesamplearealsoshown.
deviate form each other at the same gate voltage that signals the onset of deep depletion in the solid C-V curve. The dashed 1-V curve is the same as the dashed I-V curve in Fig. 1. In Fig. 3 the n-type and p-type samples had an oxide thickness of 84 nm. The oxide dark current of the p-type sample is much smaller than the F-N tunneling current observed in the n-type sample. The gradual increase of the measured oxide dark current (comparing it with the dashed curve) is similar to Solomon's findings[5]. When there is a deviation between the dark and light current measurements at a given oxide current, the corresponding voltage drop across the silicon depletion region (underneath the gate area) can be calculated from the measured C-V curves. The light assisted case showed the smaller voltage drop in the silicon. The dark result showed a larger voltage drop in the silicon due to the formation of a deep depletion region• We denote the voltage difference between the two calculated values by A Vw. At the same time, we measured the voltage difference, A I/i, from the two I - V curves at the same given oxide current level. Using the data given in Figs. 2 and 3, we plot the relationship between A V~ and A Vw in Fig. 4. It results in a straight line through the origin with unity slope. This means that if we plot oxide current vs oxide voltage by subtracting the silicon voltage drop from the applied gate bias, there will be no difference in the result even though one was measured in the dark and the other was measured in the light. After the I-V measurement, we remeasured the C-V curve. No apparent C-V shift was found and the stretch-out of the C-V curve was less than 1 V. Therefore, for the dark I-V results in Figs. 2 and 3, we can rule out electron trapping as being the cause for the several volts of deviation from the light assisted results. Using the data shown in Figs. 2 and 3, we calculated the measured dark oxide current vs depletion width of the substrate as shown in Fig. 5. In the deep depletion region, the depletion width W of the semiconductor is
0
0
I 5
I 10
I 15
I 20
I 25
I 30
V w ( VOLTS )
Fig. 4. The apparent voltagedifferenceAVt in the measured I- V curves of Figs. 2 and 3 vs the corresponding voltage drop different AVw in the silicon depletion region. I ( 10-I2A ) #490
o
o.o /
-
..o~V..o.o "°~'~
f" .°
OEPt£TION WIDTH ! 10.4 cm I
Fig. 5. Measuredoxide dark current vs the correspondingsilicon depletion width. calculated from the relation
where VB= applied gate bias, e, = permittivity of silicon, Cox = measured oxide capacitance, C = measured gateto-substrate capacitance at Vs, A = gate electrode area. The triangle data points are from Fig. 2. Initially, there is a straight line region and then the curve deviates from the line as the depletion width becomes greater. We believe the straight line portion is due to the depletion region bulk generation while the deviated portion (measured from the straight line) comes from surface generation under the gate. Our results show that the surface generation component is not a constant in this sample No. 490. The results in Fig. 3 yield the circle data points in Fig. 5 Unlike the triangle data, the surface generation component in sample No. 830 increases at the start and then becomes saturated (at W~0.7pm). We
388
HAN-SHENGLEE
also obtain a straight line for this sample at higher depletion widths. From the slopes of these two straight lines, we get a depletion region bulk generation time constant of ~ = 11.7 its for the triangle data points (sample No. 490) and • b = 10.9/~s for the circle data points (sample No. 830). Here the bulk generation time constant is calculated from the straight line portion of Fig. 5 using the equation [2]
dW =
A
(2)
where I = measured oxide current. To support the results presented in Fig. 5, we did the following experiment. Initially, we applied a negative voltage to the gate. We then switched the polarity of the bias and observed the capacitance change with respect to time. This is a common method used by many authors to determine the bulk generation component and the surface generation current component of the substrate current[9-15]. We used different gate bias values to get different "after-switching' initial C/Cox values. Assuming the bulk generation time constant rb = 11.7/ts for sample No. 490 and zb = 10.9~s for sample No. 830, we used initial slopes (just after the switching) to calculate the surface generation current components. The results are shown in Fig. 6 where the data connected by solid lines are the results from Fig. 5 and the data connected by dashed lines are the switching gate bias measurements. The agreement between these two curves is reasonably good. The surface generation contribution from the lateral extended gate region[16, 17] (where the extended gate region is the lateral spread of space charge region outside the projection of the gate) had little effect in our measured results because in our transient capacitance measurement, the samples were switched from the accumulation condition to the inversion regime. Just after the switching, the majority carders are pushed out with a time constant of e#~, where ~ is the conductivity of the sample, resulting immediately in a deep depletion region. Therefore, the
(IO-12A)
t
#490
511s
)-a--
~
o
0.4
t
I
Figure5 results.
.... Transientcapacitancemeasurement.
e . . . .
i~.12
e_
l
la ~- qNpoL,A,
(3)
Tb
where Npo = thermal equilibrium electron concentration in silicon, L, = electron diffusion length. With Npo -~4x 104cm -~, L, -- 100/zm, Tb ~--- 10/Ls and A = l . 3 x 10-4cm 2, we obtain Id= 10-15A, which is much smaller than our measurement scale 10-~2A. Therefore, we can neglect the diffusion component. SUMMARY We applied a slow positive voltage ramp to the gate of MOS capacitors to measure both I - V (oxide current vs gate voltage) and C-V (gate to substrate capacitance vs gate voltage) characteristics of these samples. For some samples, with the same fabrication processes, the oxide current vs applied gate bias characteristics exhibited "apparent differences when using n-type or p-type substrate material. From the measured C-V results, we can calculate the voltage drop in the silicon substrate. Since there is a depletion region in the p-type MOS sample, it has more voltage drop in the silicon than the n-type sample does. After subtracting the silicon voltage drop from the applied gate bias, we find that both n-type and p-type suhstrates give the same oxide current vs oxide voltage results. Among the three p-type MOS capacitors shown in the experiment, we find that the role of surface generation is to reduce the need for a deeper depletion region when the surface of the depletion region is also responsible for the substrate generation current. We also used transient capacitance measurements to check the conclusions drawn from our I-V results. We find the agreement between these two measured results to be reasonably good.
_
t830
o l
initial slope of the transient capacitance measurement depends on the generation rates of the bulk depletion region and the depleted silicon surface region. This situation is similar to that in the I- V measurement where we have deep depletion in the substrate. At this condition, we have depleted surfaces under the gate area and at the extended lateral gate region. The area ratio of the extended gate region to the gate electrode is smaller than 5 x 10-2 for sample No. 830 and is smaller than 2 x 10-2 for sample No. 490. Hence we can neglect surface generation from the lateral extended gate region in our transient capacitance measurement. In the previous discussion we did not consider the substrate diffusion current. Under our measurement conditions, the electron diffusion current which diffuses from the bulk of the silicon substrate to the depletion region can be estimated from the expression[2].
I
l
0.8 1.6 2.0 DEPLETIONWIOTH{10-4cm )
i
i
2.4
Fig. 6. Surface generation current component, Is, extracted from the I-V and C-V measurement (solid lines). The dashed lines were the results of transient capacitance measurement.
Acknowledgements--I would like to thank Dr. M. C. Steele for his management support and encouragement. The fruitful discussion with J. W. Hile and the process assistancefrom Ms. B. J. Nation are also appreciated. ~CF~ I. M, Lenzlingerand E. H. Snow, J. Appl. Phys. 40, 278 (1969). 2. A. S. Grove, Physics and Technology of Semiconductor Devices. Wiley, New York (1967).
Effect of substrate generation current 3. C. M. Osburn and E. J. Weitzman, J. Electrochem. Soc. 119, 6o3 0972). 4. z. A. Weinberg, W. C. Johnson and M. A. Lampert, J. Appl. Phys. 47, 248 (1976). 5. P. M. Solomon, Appl. Phys. Lett.30, 597 (1977). 6. F. H. Hielscher and H. M. Preier, Solid-St. Electron 12, 527 (1969). 7. S. Kar, Appl. Phys. Left.25, 587 (1974). 8. B. A. Maclver, IEEE Trans. Electron Dev. ED-Ig, 401 (1971). 9. M. Zerbst, Z. Angew Phys. 120), 30 (1966). I0. F. P. Heiman, IEEE Trans. Electron Dev. ED-14, 781 (1967).
389
S. R. Hofstein, IEEE Trans Electron Dev. ED-14, 785 (1967). J. Muller and B. Schiek, Solid-St. Electron. 13, 1319 (1970). C. T. Sah and H. S. Fu, Phys. Status Solidi (a) 11,297 (1972). C. T. Sah and H..S. Fu, Phys. Status Solidi (a) 14, 59 (1972). T. W. Collins and J. N. Churchill, IEEE Trans Electron Dev. ED-22, 90 (1975). 16. D. R. Sehroder and H. C. Nathanson, Solid-St. Electron. 13, 577 (1970). 17. D. R. Schroder and J. Guldberg, Solid-St. Electron. 14, 1285 (197D. 11. 12. 13. 14. 15.
0038-1101/79/0401-0385/$02.00/0
EFFECT OF SUBSTRATE GENERATION CURRENT ON OXIDE I - V MEASUREMENT ON p-TYPE MOS STRUCTURES HAN-SHENG LEE Electronics Department, General Motors Research Laboratories, Warren, MI 48090, U.S.A. (Received 31 August 1978; in revisedform 12 October 1978) Abstract--The values of the bulk generation current and surface generation current extracted from slow ramp I- V and C-V measurements of p-type substrate MOS capacitors are found to be consistent with the results from transient capacitance measurement. The shape of the I- V curve for high positivegate biases is found to depend on the formation of a deep depletion region in the p-type substrate.
INTRODUCTION
With positive bias applied to the metal of a MetalOxide-Semiconductor (MOS) structure, electrons injected from the silicon side into the oxide and then subsequently collected by the metal gate are responsible for the observed Fowler-Nordheim (F-N) tunneling current at high electric fields[l]. Since electrons are the majority carriers in n-type substrates, injection electrons can be supplied very fast. Also, because of the formation of an accumulation layer beneath the gate oxide, almost all of the applied gate bias drops across the oxide. When the substrate is p-type, with high positive bias applied to the metal gate, injected electrons must be supplied through generation processes in order to maintain a steady oxide current. These electrons can be generated through the surface generation centers or the bulk generation centers of the substrate. In measurements of oxide leakage current of MOS capacitors as a function of gate voltage (I-V curves, gate positively biased, sample in darkness), we find an apparent dependence of the I-V characteristics on substrate conductivity type. Leakage currents on n-type substrate samples follow the Fowler-Nordheim model. I - V curves from p-type substrate samples differ from the n-type case and among each other. We find that the surface generation current is correlated with this substrate-type dependence and sample-to-sample variability of the p-type samples and can account for the major differences in the I-V characteristics of the two types of capacitors. In the present study, we applied a positive linear ramp bias to the gate of the p-type MOS capacitors. With the gate bias larger than the flat band voltage of the capacitor, a depletion region forms in the substrate. Initially, the width of the depletion region increased with the increasing of the gate bias. When the magnitude of the gate bias equals the threshold voltage of the capacitor, the depletion width reaches an equilibrium maximum value Wm and forms an inversion layer[2]. Since the voltage drop across the silicon depletion region is a function of the depletion width and the oxide is a good insulator, further increases in gate bias, after formation SSE Vol. 22, No. 4--C
385
of the inversion layer, will result in an increasing electric field in the gate insulator. The high oxide field causes current flow through the oxide, and if this leakage current is large enough, can result in the collapse of the inversion layer. The decrease of the surface electron concentration enhances the surface generation rate[2]. Without increasing the depletion width, the bulk of the depletion region can handle the oxide current up to (qN~Wml2"fb) per unit area[2] where N~ is the intrinsic carder concentration of silicon, Tb is the bulk generation time constant and q is the electron charge quantity. For illustration prupose, let us first consider the case where the surface generation rate is much smaller than the bulk generation rate in the entire I- V measurement range. For a given depletion region width, once the oxide leakage current reaches the generation rate limit of the bulk depletion region, any further increase of gate bias will be distributed across the insulator and depletion region in such a way that a steady oxide current can be maintained. In other words, the substrate will get part of the increased gate bias to widen the depletion region and the oxide receives the rest of the bias. With this widened depletion region, the bulk of the depletion layer can supply more oxide current than before. Additional increase of the gate bias will force the depletion region to widen further. Therefore, starting from the onset of the depletion region widening (with W,, as a reference), the oxide no longer receives the full amount of the increased gate bias. This will be reflected in the measured I-V curve and cause the curve to deviate from the shape extrapolated from the low gate bias data. At a given temperature and illumination, the gate bias, where this deviation appears, is determined by the doping level of the substrate, oxide thickness and Tb. The second limiting case we will consider is that the surface generation rate is much larger than the bulk generation rate and can supply the oxide current increase over the entire I - V measurement range. In this case, the width of the depletion region will not be increased (with W~ as a reference) due to the increase of the gate bias and the voltage drop in the silicon will be constant. Therefore, the measured I - V results will follow the low oxide
HAN-SIIENG LEE
386
current trend without deviation. The example of having increasing oxide current without increasing the substrate depletion width can be found in the measured results of Osburn and Weitzman[3] and Weinberg et al.[4]. The example of the other case, namely, with increasing depletion layer width to supply the leakage electrons through the bulk generation process can be found in Soiomon's results[5] where the measured I-V curves at high bias do not follow the same trend observed at lower voltages. At high gate bias the oxide current increases more slowly than observed in the low gate bias region. In the following, we will present three experimental results which show high, medium and low surface generation rates (as compared with the bulk generation rate) and its effect on the shape of the measured I-V curve. We correlate the measured I-V curves with the corresponding gate to substrate capacitance vs gate bias (C-V) results to find the relationship between the oxide current and the depletion width for the different surface generation rate conditions. The technique of correlating C-V and I-V results to study the substrate has been used by Hielscher and Preier[6] in their metal-silicon nitride-silicon samples, by Kar[7] in his thin oxide (46nm) tunnel MOS diodes and by MacIver[8] in his hybrid capacitors. In this study, we used thermally grown oxides 55 and 84 nm thick in MOS capacitors. EXPERIMENTAL RI~ULTS AND DISCUSSIONS
I ( 1o'lZA )
C Cox #440 i
-0.8
Dark [ P-type, ( 100 ), ( . . . . Light J 2 ohm-cm, 55 nm. Data points only.
0.6
X ] N-type, ( 100 ), 3 ohm
t 55 nm.
0.4
2
O.2
1
~
---L._------10
Fig. 1. I-V
10
and C-V
20
30
40
O
50
GATEBIAS( VOLTS resultsof a p-type sample(No.440).Solid
curves were measured in the dark and the dashed curves were measured with sample exposed to room light. Several I-V data points (measured in the dark) for a n-type sample are also shown. ( IO'12A )
c/Cox 1 1490 Dark ~ P-type, ( 100 ) / Light) 2 ohm-cm, 55 nm.
0.8 Samples with <100> orientation, 3 ohm-era n-type and 2 ohm-cm p-type were used. The oxide of the MOS capacitors was thermally grown in dry oxygen ambient at -0.6 3 ll00°C together with 0.3% of HCI flowing and followed by a 15 min nitrogen gas anneal in the same tube. The oxide thicknesses used were 55 and 84nm. Aluminum "0.4, ............................. ,- 2 / dots of one micron thickness and 127 izm diameter were ~..o; E-beam evaporated on the oxide. After removing the ! L°'2 ) back oxide, one micron of aluminum was evaporated on the back side of the wafers. The wafers were then annealed in forming gas at 480°C for 30rain, diced, t, 0,0 l I t 0 -I0 0 10 20 30 40 5O mounted on TO-5 headers, bonded and capped. GATE BIAS ( VOLTS ) A Keithley model 26300 logarithmic picoammeter was used to measure the oxide current in the range of 10 - i s Fig. 2. I- V and C- V results of a p-type sample (No. 490). Solid A-10 - ' ° A. For the same oxide thickness, there was no curves were measured in the dark and the dashed curves were measured with sample exposed to room light. significant difference in the measured I-V curves for the n-type or p-type substrate samples provided the p-type n-type samples were measured in the dark. To make the substrate samples were exposed to room light (without figures clear, we only show several I - V data points for sample cap) during the measurement. These I-V curves the measured n-type samples. All the I-V results in this fit a Fowler-Nordheim plot with an effective mass ratio study were measured by the slow ramp method with a m*/mo=0.41 and a barrier height of 3.2eV. If the I-V measurement was done in the dark (with sample cap on), ramp rate of 6 mV/s. The C- V results were measured at I MHz using the same dc ramp rate for all samples. In substrate-dependent results occurred in some samples. In Fig. 1, both n-type and p-type samples had the same the following I-V measurements we used 10-'2 A scale instead of going through 10-'3 A-10 -'° range. Therefore, oxide thickness of 55 nm because the wafers were fabricated together. We did not see much difference between a better accuracy in data reading can be obtained and the the solid curve and the dashed curve. The capacitance substrate generation effect still can be domonstrated curve corresponding to the measured current ranges is clearly. In this scale, the oxide current was directly read still fiat. The substrate-independent result is similar to from the Keithley model 616 electrometer. t h e ' observation reported by Osburn and Weitzman[3] Figures 1-3 show the measured I-V and C-V results. The solid curves were measured in the dark (with and Weinberg et aL [4]. In Fig. 2 the samples also had a thickness of 55 nm, but the solid curves deviate from the cap on) and the dashed cruves were measured with samples exposed to the room light (with cap off). All dashed curves. We also noticed the two I-V curves
Effect of substrate generation current I ( lO"1 A )
Cox
387
30 ~ .AV I(VOLTS)
#830 Dark I. P-type, 1100 ),
1
5
. . . . LkJM l 2 ohm-crn,~pn
o
25
/ •
X {N't~e,/
[/Z ~---.b/
0.6
_....o,-.......
I,
i
I -10
t
0.0 i 0 5
3
;- ........ ,.
0.2
l 0
60
70
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,t I " 50
2o
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80
l(I
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o
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GAI'[ BIAS (VOLTS)
Fig. 3. I-V and C-V results of a p-type sample (No. 830). Solid curves were measured in the dark and the dashed curves were measured with sample exposed to room light. Several I-V data points(measuredin the dark)for a n-typesamplearealsoshown.
deviate form each other at the same gate voltage that signals the onset of deep depletion in the solid C-V curve. The dashed 1-V curve is the same as the dashed I-V curve in Fig. 1. In Fig. 3 the n-type and p-type samples had an oxide thickness of 84 nm. The oxide dark current of the p-type sample is much smaller than the F-N tunneling current observed in the n-type sample. The gradual increase of the measured oxide dark current (comparing it with the dashed curve) is similar to Solomon's findings[5]. When there is a deviation between the dark and light current measurements at a given oxide current, the corresponding voltage drop across the silicon depletion region (underneath the gate area) can be calculated from the measured C-V curves. The light assisted case showed the smaller voltage drop in the silicon. The dark result showed a larger voltage drop in the silicon due to the formation of a deep depletion region• We denote the voltage difference between the two calculated values by A Vw. At the same time, we measured the voltage difference, A I/i, from the two I - V curves at the same given oxide current level. Using the data given in Figs. 2 and 3, we plot the relationship between A V~ and A Vw in Fig. 4. It results in a straight line through the origin with unity slope. This means that if we plot oxide current vs oxide voltage by subtracting the silicon voltage drop from the applied gate bias, there will be no difference in the result even though one was measured in the dark and the other was measured in the light. After the I-V measurement, we remeasured the C-V curve. No apparent C-V shift was found and the stretch-out of the C-V curve was less than 1 V. Therefore, for the dark I-V results in Figs. 2 and 3, we can rule out electron trapping as being the cause for the several volts of deviation from the light assisted results. Using the data shown in Figs. 2 and 3, we calculated the measured dark oxide current vs depletion width of the substrate as shown in Fig. 5. In the deep depletion region, the depletion width W of the semiconductor is
0
0
I 5
I 10
I 15
I 20
I 25
I 30
V w ( VOLTS )
Fig. 4. The apparent voltagedifferenceAVt in the measured I- V curves of Figs. 2 and 3 vs the corresponding voltage drop different AVw in the silicon depletion region. I ( 10-I2A ) #490
o
o.o /
-
..o~V..o.o "°~'~
f" .°
OEPt£TION WIDTH ! 10.4 cm I
Fig. 5. Measuredoxide dark current vs the correspondingsilicon depletion width. calculated from the relation
where VB= applied gate bias, e, = permittivity of silicon, Cox = measured oxide capacitance, C = measured gateto-substrate capacitance at Vs, A = gate electrode area. The triangle data points are from Fig. 2. Initially, there is a straight line region and then the curve deviates from the line as the depletion width becomes greater. We believe the straight line portion is due to the depletion region bulk generation while the deviated portion (measured from the straight line) comes from surface generation under the gate. Our results show that the surface generation component is not a constant in this sample No. 490. The results in Fig. 3 yield the circle data points in Fig. 5 Unlike the triangle data, the surface generation component in sample No. 830 increases at the start and then becomes saturated (at W~0.7pm). We
388
HAN-SHENGLEE
also obtain a straight line for this sample at higher depletion widths. From the slopes of these two straight lines, we get a depletion region bulk generation time constant of ~ = 11.7 its for the triangle data points (sample No. 490) and • b = 10.9/~s for the circle data points (sample No. 830). Here the bulk generation time constant is calculated from the straight line portion of Fig. 5 using the equation [2]
dW =
A
(2)
where I = measured oxide current. To support the results presented in Fig. 5, we did the following experiment. Initially, we applied a negative voltage to the gate. We then switched the polarity of the bias and observed the capacitance change with respect to time. This is a common method used by many authors to determine the bulk generation component and the surface generation current component of the substrate current[9-15]. We used different gate bias values to get different "after-switching' initial C/Cox values. Assuming the bulk generation time constant rb = 11.7/ts for sample No. 490 and zb = 10.9~s for sample No. 830, we used initial slopes (just after the switching) to calculate the surface generation current components. The results are shown in Fig. 6 where the data connected by solid lines are the results from Fig. 5 and the data connected by dashed lines are the switching gate bias measurements. The agreement between these two curves is reasonably good. The surface generation contribution from the lateral extended gate region[16, 17] (where the extended gate region is the lateral spread of space charge region outside the projection of the gate) had little effect in our measured results because in our transient capacitance measurement, the samples were switched from the accumulation condition to the inversion regime. Just after the switching, the majority carders are pushed out with a time constant of e#~, where ~ is the conductivity of the sample, resulting immediately in a deep depletion region. Therefore, the
(IO-12A)
t
#490
511s
)-a--
~
o
0.4
t
I
Figure5 results.
.... Transientcapacitancemeasurement.
e . . . .
i~.12
e_
l
la ~- qNpoL,A,
(3)
Tb
where Npo = thermal equilibrium electron concentration in silicon, L, = electron diffusion length. With Npo -~4x 104cm -~, L, -- 100/zm, Tb ~--- 10/Ls and A = l . 3 x 10-4cm 2, we obtain Id= 10-15A, which is much smaller than our measurement scale 10-~2A. Therefore, we can neglect the diffusion component. SUMMARY We applied a slow positive voltage ramp to the gate of MOS capacitors to measure both I - V (oxide current vs gate voltage) and C-V (gate to substrate capacitance vs gate voltage) characteristics of these samples. For some samples, with the same fabrication processes, the oxide current vs applied gate bias characteristics exhibited "apparent differences when using n-type or p-type substrate material. From the measured C-V results, we can calculate the voltage drop in the silicon substrate. Since there is a depletion region in the p-type MOS sample, it has more voltage drop in the silicon than the n-type sample does. After subtracting the silicon voltage drop from the applied gate bias, we find that both n-type and p-type suhstrates give the same oxide current vs oxide voltage results. Among the three p-type MOS capacitors shown in the experiment, we find that the role of surface generation is to reduce the need for a deeper depletion region when the surface of the depletion region is also responsible for the substrate generation current. We also used transient capacitance measurements to check the conclusions drawn from our I-V results. We find the agreement between these two measured results to be reasonably good.
_
t830
o l
initial slope of the transient capacitance measurement depends on the generation rates of the bulk depletion region and the depleted silicon surface region. This situation is similar to that in the I- V measurement where we have deep depletion in the substrate. At this condition, we have depleted surfaces under the gate area and at the extended lateral gate region. The area ratio of the extended gate region to the gate electrode is smaller than 5 x 10-2 for sample No. 830 and is smaller than 2 x 10-2 for sample No. 490. Hence we can neglect surface generation from the lateral extended gate region in our transient capacitance measurement. In the previous discussion we did not consider the substrate diffusion current. Under our measurement conditions, the electron diffusion current which diffuses from the bulk of the silicon substrate to the depletion region can be estimated from the expression[2].
I
l
0.8 1.6 2.0 DEPLETIONWIOTH{10-4cm )
i
i
2.4
Fig. 6. Surface generation current component, Is, extracted from the I-V and C-V measurement (solid lines). The dashed lines were the results of transient capacitance measurement.
Acknowledgements--I would like to thank Dr. M. C. Steele for his management support and encouragement. The fruitful discussion with J. W. Hile and the process assistancefrom Ms. B. J. Nation are also appreciated. ~CF~ I. M, Lenzlingerand E. H. Snow, J. Appl. Phys. 40, 278 (1969). 2. A. S. Grove, Physics and Technology of Semiconductor Devices. Wiley, New York (1967).
Effect of substrate generation current 3. C. M. Osburn and E. J. Weitzman, J. Electrochem. Soc. 119, 6o3 0972). 4. z. A. Weinberg, W. C. Johnson and M. A. Lampert, J. Appl. Phys. 47, 248 (1976). 5. P. M. Solomon, Appl. Phys. Lett.30, 597 (1977). 6. F. H. Hielscher and H. M. Preier, Solid-St. Electron 12, 527 (1969). 7. S. Kar, Appl. Phys. Left.25, 587 (1974). 8. B. A. Maclver, IEEE Trans. Electron Dev. ED-Ig, 401 (1971). 9. M. Zerbst, Z. Angew Phys. 120), 30 (1966). I0. F. P. Heiman, IEEE Trans. Electron Dev. ED-14, 781 (1967).
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S. R. Hofstein, IEEE Trans Electron Dev. ED-14, 785 (1967). J. Muller and B. Schiek, Solid-St. Electron. 13, 1319 (1970). C. T. Sah and H. S. Fu, Phys. Status Solidi (a) 11,297 (1972). C. T. Sah and H..S. Fu, Phys. Status Solidi (a) 14, 59 (1972). T. W. Collins and J. N. Churchill, IEEE Trans Electron Dev. ED-22, 90 (1975). 16. D. R. Sehroder and H. C. Nathanson, Solid-St. Electron. 13, 577 (1970). 17. D. R. Schroder and J. Guldberg, Solid-St. Electron. 14, 1285 (197D. 11. 12. 13. 14. 15.