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Chip capacitors in hybrid microelectronics
Chapter 19
Chip capacitors in hybrid microelectronics TANTALUM CHIP
CAPACITORS
This type of capacitor is suitable for applications in hybrid circuitry, but until recently there have been limitations regarding their assem bly, sealing, storage and operating temperature ranges. With the introduction of the high temperature solid copper counter-electrode system, most of the problems have been eliminated, thus tantalum chips are compatible with thin films, die-bonded applications, and thick film hybrid construction. The solid tantalum capacitor has matured over the past ten years and during this time much research has been carried out by circuit designers on the failures in this type of capacitor. It has been found that it is very necessary to observe safe limits when the capacitor used in such applications as smoothing, triggering, coupling-decoupling RC timing networks, phase shift, low fre quency and long-time constants etc. To avoid the many pitfalls when using this type of capacitor, designers should take note of the following: Capacitance The DC capacitance of the solid tantalum capacitor is always much higher than the AC value owing to the marked dielectric absoφtion of the anodic oxide dielectric. 215
Compatibility and Testing of Electronic Components Reappearance of Voltage If a capacitor which has been polarised is short circuited, a discharge current continues to flow for more than one hour. If instead, the capacitor is discharging for only a short time and then left on open circuit, a voltage builds up between the electrodes, the residual voltage increases with rise in ambient temperature and the time of initial polarisation. The reappearance of voltage across the capaci tor when it is intended to be unpolarised could be troublesome in circuits such as those used in computers and triggering circuits unless the circuit is suitably designed to allow for this condition.
High Ambient Temperature When this type of capacitor has to be used in high ambient tempe ratures, it must be remembered that the leakage current increases ten-fold for a 50 °C rise. Because of this, it is often necessary to derate the working voltages. Series Resistance Often the impedance of a capacitor is of greater importance than its capacitance. A capacitor should be rejected if the following properties exceed stipulated limits : (1) the impedance, measured at 50 Hz if the capacitance is signi ficant, measured at 100 Hz if the series resistance is significant (2) loss factor measured at 50 Hz (3) leakage current Source Impedance Catastrophic failures of this type of capacitor can be reduced by the user if he provides an adequate series resistance in the circuitry, because these capacitors tend to self-heal under proper circuit conditions, but where a sudden inrush of current does occur the capacitor can be destroyed. Several complaints have been made 216
Chip Capacitors in Hybrid Microelectronics of open circuit, increase in DC leakage current and short circuits, the latter two are usually caused by dielectric fractures at thin spots in the dielectric. These thin spots are due to impurities or contamination both of which resist the initial oxide formation during anodisation. These impurities produce an oxide film that is effectively thinner than that of a clean pure tantalum powder. The thin areas which are probably deep in the porous anode rupture under voltage or temperature stress allowing a localised current inrush. In consequence the leakage current may increase or decrease or show no change from its initial value, but this action can also result in short circuit failure. During current inrush, heat is generated in the immediate area. This Uberates oxygen from the manganese dioxide M^Ogi- Fortunately, two reactions occur to heal the defect site. First the freed oxygen combines with the exposed metallic tantalum material to reform the dielectric film, secondly, the formally conductive at the hot spot is reduced to a lower manganese oxide of high resistivity. This combination can effect a healing of the defect site if the inrush current is limited. Scintallations are caused by impurities and it is well known that manufacturers 'burn in' capacitors in their production process in an attempt to eliminate gross defects. Derating of Working Voltage Care must be taken to ensure that the DC bias is not so reduced as to cause a reversal of polarity on a polarized capacitor. To pre vent such an occurrence the peak value of any AC component must not exceed the applied DC bias. Reversed Polarity Polar tantalum capacitors should not be operated continuously at a reversed voltage exceeding 1 V at between 20 °C and 85 °C or 0-65 V from 85 °C to 125 °C. Leakage Leakage denotes the amount of direct current (not charging) that will flow steadily through a capacitor. This is an important consi deration when the capacitor is used in coupling or other applications 15
217
Compatibility and Testing of Electronic Components where DC voltage is imposed. When a soHd tantalum capacitor is polarised for a period of five seconds, the leakage current is appreciable, but drops towards a steady value. This condition could be important during the warming up period in equipment where a standing voltage is required at switch on. Improvements There is a considerable inefficiency within the discrete package of the canned capacitor and an obvious improvement would be to utihse the processed and silver coated tantalum anode directly in hybrid circuit apphcations. The silvered coating serves as the negative connection to the capacitor element. The positive connec tion is made by means of a gold plated tab wire which has been welded to the anode riser. Similar versions of tantalum chip capa citors utilise finer grain powders to achieve yet a further increase in volumetric efficiency. Another type is designed to minimise cost whilst sacrificing some volumetric efficiency. The positive connection is completed via a solder coated crossbar welded to the tantalum riser which means the weld is well away from the riser so the welding operations can be performed on automatic equipment. This type of chip is primaily designed for hybrid circuit modules where the highest volume effici ency is not required, as in the commercial and entertainment eqipment, but rather the lowest possible cost, including not only the component cost, but assembly labour and packaging rehability costs. Reflow Solder Some types of terminations are designed to be assembled into the circuit by means of solder application. One of these is where the tantalum chip is reflow soldered, the soldering operation being carried out in a hot air oven. In this operation it is necessary to control temperature and time. Figure 19.1 illustrates the time and temperature parameters for this operation. Exceeding these can result in the degradation of the parametic performance of the chip capacitor, particularly with regard to dissipation factor and equi valent series resistance. This is due to the scavenging of the silver layer by dissolution in the molten solder. 218
Chip Capacitors in Hybrid Microelectronics
I902002KD 2 2 0 2 3 0 2 4 0 2 5 0 2 6 0 Temperature °C
Figure 19.1. Safe mounting time/temperature parameters for tantalum chip capacitors using a SN-62 solder.
Hand Soldering The placeing of tantalum chip capacitors can also be accompli shed by soldering with a small iron or reflow heat pulse, infrared, or by hot plate techniques. The solder used in these assemblies should contain some silver to minimise scavenging of the silver from the negative electrode. A composition such as Sn 62 % (36 % Pb— 2% Ag)is suitable. Non Solder For this method of attachment the chip is pre-assembled to a ceramic substrate after which it may be subjected to life testing, thermal shock and parameter drift screening prior to use. With the chip pre-assembled to the substrate, the dangers of damage during assembly into the ultimate package are minimised. The substrate is generally fixed to the package substrate by epoxy bonding and the electrical connections are made by interconnection wires to gold plated positive and negative tabs on the chip substrate, or the tabs themselves may be soldered to the hybrid substrate. High Temperature Tantalum Chip Capacitors The previously described chip capacitors have been successful in hybrid circuits using thick film technology along with encapsulated semiconductor devices where the assembly, storage, conformal 219
Compatibility and Testing of Electronic Components coating, and/or package sealing temperatures have been limited to approximately 150 °C and where the storage and operating temper ature ranges have been confined to 125 °C. Attempts to use these chips in hybrid circuits employing thin films or unprotected semi conductors have been unsuccessful because the use of solder with flux as a means of interconnection and attachment cannot be tolerated. In addition, attempts to use solder coated chips or just silver coated chips attached by epoxy bonding and interconnection by ultrasonic wire bonding has met with only marginal success. In these apphcations there is a requirement for bake-out of the package coupled with subsequent heremetic sealing. These opera tions involve temperatures ranging to 300 °C and occasionally operating temperature of 200 °C. Under these conditions there is a significant degradation of the tantalum chip electrode system, and a further problem due to contamination within the package after sealing from the byproducts of the breakdown of the silver cathode surface. Occasional difficulties are also encountered where the assembly temperature, even in thick hybrid circuits, exceeds the time-temperature relationship. In these cases decomposition and delamination of the silver counterelectrode occurs which leads to a significant increase in the equivalent resistance of the device. To obviate the above problems along with the possible contami nation which may occur from elements of the tantalum chip capa citor itself, a new counterelectrode has been designed. The silver/ solder coating has been completely replaced with thin homogene ous solid copper coating, and with this coating the chip capacitors are capable of sustained storage or assembly temperatures up to 250 °C and operating temperatures up to 200 °C. Tests carried out show that due to the lo\^' solubility of copper compared to silver in solder, there is no degradation of the copper electrode. In addi tion, since there is no silver paint present there can be no decomposi tion products to contaminate other portions of the hybrid circuits by the formation of gas pockets or delamination of the counter electrode from the anode. The copper may be pre-tinned with solder or other materials for re-flow solder applications or with gold plated tabs affixed directly to the copper surface for ultrasonic wire bonding.
220
Chip Capacitors in Hybrid Microelectronics Performance Data Figures 19.2, 19.3 and 19.4 show the parametric performance of both conventional and copper clad tantalum chip capacitors on a 1000 hours 125 °C full rated voltage life test. The capacitance, dissipation factor and DC leakage parametric stability are typical of those obtained with conventional types. The response of the tanta-Conventional Counterelectrode
|iOO '^Χ"""""" o
5
^
Improved-""^
^
95
O
lOO
200 300 400 500 600 700
8 0 0 9 0 0 lOOO
Test time h
Figure 19.2, 125°C life test performance, tantalum chip capacitor 2-6 μ¥ 20 V rating. The full line represents on improved counterelectrode.
Conventional Counterelectrode ^XImproved
Ο
lOO 2 0 0
300 400 500 600 Test tinne h
TOO 8 0 0 9 0 0
lOOO
Figure 19.3. 125°C life test, 26 μ¥, 20 Y.
o
ΙΟΟ 2 0 0
300
4 0 0 5 0 0 6 0 0 7 0 0 8 0 0 9 0 0 ΙΟΟΟ Test time h
Figure 19.4. 125°C life test, 2-6 μ¥ 20 V.
221
Compatibility and Testing of Electronic Components lum chip capacitors to extremes of humidity conditions is that the capacitance increases very rapidly on exposure to high ambient humidity. After 100 h of the wet condition the capacitors were baked-out at 125 °C and the typical capacitance drop due to the removal of absorbed moisture was observed. These changes in capacitance with humidity/bake-out cycle can be repeated many times with no apparent degredation of the capacitor element or electrical performance. Extended exposure to a very wet condition will eventually cause a degradation of the DC leakage parameter due to ionic contamination carried into the capacitor element by the moisture but the point becomes academic in a sealed package. In thick film hybrid applica tions where the package is not hermetically sealed, conformal coatings such as polyurathane or silicon varnieshes have been found effective in impeding the ingress of moisture. Figure 19.5 illustrates the impedance versus frequency perform ance of a 1 μΕ ceramic chip and a 1 μΡ tantalum chip. At both the low and high frequencies the performance is similar, but in the lO
I
I"
o Ceramic Chip
Ol
OOl lOK
lOOK
IM lOM Frequency Hz
lOOM
IG
Figure 19.5. Chip capacitor impedance versus frequency I uF 25 V.
lOOK
IM Frequency Hz
lOOM
Figure 19.6. Tantalum chip capacitor with improved counterelectrode.
222
Chip Capacitors in Hybrid Microelectronics region of 6 Mhz the ceramic displays a series resonance due to the inherent lower equivalent series resistance whilst the tantalum chip impedance appears resistive. In fast pulse circuits this highly damped impedance can be used to decrease or eliminate ringing, oscillations and resonances set up between the capacitor element and the inductance of the interconnections. Figure 19.6 shows the impedance versus frequency of the improved copper clad tantalum chip capacitor.
CERAMIC CHIP
CAPACITORS
Single layer chip capacitors, small versions of conventional single layer ceramic discs or plates, can be used but are limited in maximum value to 1 000 pF. In the highest values they are extremely fragile due to the dielectric thickness, the minimum practical thickness be ing between 0127 mm and 0-254 mm. Furthermore, it is often inconvenient to the user to have the terminations on opposite faces and special shapes of electrode have to be used to put both terminations on the same face, this reduces the maximum capaci tance available in a given chip size. Monolithic chip capacitors, consisting of up to twentyfive layers of dielectric, each as thin as 0-0254 mm extend the upper limit of capacitance by one hundred times. Terminations can be brought to one face without any significant reduction in capacitance and here is also an advantage in this type of construction at the lower values of capacitance, which could be achieved with only one layer of dielectric. In these cases, the chip is made robust enough to handle by adding dummy or insulating layers. Also material finishes can be made suitable for the user's bonding techniques, ensuring compati bility with semiconductor devices used on the same substrate. Construction This is effected by dispersing dielectric powder inorganic binders and solvents and then casting the shp so formed to yield a flexible film that can be printed with the necessary electrode shape using ink or paint made from a dispersion of a noble metal of high melting point. The necessary number of layers are stacked, cut into shape by punching and consolidated by pressing in a die. 223
Compatibility and Testing of Electronic Components Accurate location of the electrodes is necessary so that their edges can be exposed alternatively on opposite edges of the 'green' ceramic chip so formed. Firing burns out the organic materials and sinters the dielectric and electrode layers into a solid block. The electrodes are connected together and terminated as required, either before or after firing. Almost any ceramic formulation can be used depending on the temperature characteristics required. For general purposes, where a 20% variation over a 200 °C range can be permitted, capacitance of 5 000 pF/mm^ can be achieved for a rated voltage of 50 to 100 DC. Where the temperature range is restricted, allowing the use of the highest permittivity ceramics, and the working voltage is low, it is possible to achieve up to 50 000 pF/mm^. The range of monolithic capacitors offer the user a large number of capacitors in a wide range of materials. Six different compositons ranging from K-35, with 0% TC to K-8000 with the usual peaky shape of a TC curve associated with high permittivity material, and have three sizes shown in Table 19.1. The standard range have Table 19.1 R A N G E O F MONOLrraiC CAPACITORS
Approximate Mate TC rial (_60o to Κ + 140°C)
Size number (mm)
1
2
Nominal size (mm)
2ΐχ1ι
3iX3i
Tolerances available
3
Capacitance (in pF up to 8200 in μΡ above)
35 0%
±5%, :-I0% ±20%
15 to 100
110 to 430
470 to 1500
90
±5%, ±10% ±20%
36 to 240
270 to 1500
1600 to 3600
240 ±10%
±10%, ±20%
100 to 680
820 to 3900 4700 to 0 0 1
800 - 1 5 %
±10%, ±20%
330 to 2200
2700 to 0012 0015 t o 0 0 3 7
2400 —20%
±10%, ±20% 1000 to 6800
8000 —10°to + 70°C - 2 0 % + 80% —50%
224
8200 to 0039 0047 too-11
3300 to 0022 0-033 to 0 1
0 1 5 to 0-33
Chip Capacitors in Hybrid Microelectronics terminations brought to one side and made of sintered palladium, satisfying most of the different requirements of weldabihty and solderability. Silver terminations, besides being restricted to solder ing only, have technical limitations when operated at high tempera tures and high DC voltage stress, due to silver migration. This can cause fairly rapid deterioration of the insulation of high Κ ceramics. Aging All ceramic dielectrics in the barium titanate class (i.e. high permit tivity) have an inherent aging characteristic. This is approximately — 2% and —5% per logarithic decade hours respectively. These units should be within their stated selection tolerance at 1 000 h, that is: 4 h from 0-1 h after operation in a temperature of +120 °C the capacitance will return to its initial 0-1 h value and the aging cycle resume. These capacitors are suitable for bypass and coupling applications or for frequency discriminating circuits where low loss and high stability are not of major importance. The uses of ceramic capacitors of various permittivities are as follows: (1) Low K, for temperature compensating purposes where stan dard values of temperature coefficients are essential, they are also specifically suited for resonant circuit applications or other uses where low loss and high stability are essential. (2) Medium K, for general purposes, where standard values and tolerances for temperature coefficients are suitable. (3) High K, (2 400) for general purpose, where wide tolerances on temperature coefficients are acceptable. (4) High K, (8 000) for general purpose but with still wider tolerances on temperature coefficients and less stringent requirements on the stability of capacitance.
225
Chip capacitors in hybrid microelectronics TANTALUM CHIP
CAPACITORS
This type of capacitor is suitable for applications in hybrid circuitry, but until recently there have been limitations regarding their assem bly, sealing, storage and operating temperature ranges. With the introduction of the high temperature solid copper counter-electrode system, most of the problems have been eliminated, thus tantalum chips are compatible with thin films, die-bonded applications, and thick film hybrid construction. The solid tantalum capacitor has matured over the past ten years and during this time much research has been carried out by circuit designers on the failures in this type of capacitor. It has been found that it is very necessary to observe safe limits when the capacitor used in such applications as smoothing, triggering, coupling-decoupling RC timing networks, phase shift, low fre quency and long-time constants etc. To avoid the many pitfalls when using this type of capacitor, designers should take note of the following: Capacitance The DC capacitance of the solid tantalum capacitor is always much higher than the AC value owing to the marked dielectric absoφtion of the anodic oxide dielectric. 215
Compatibility and Testing of Electronic Components Reappearance of Voltage If a capacitor which has been polarised is short circuited, a discharge current continues to flow for more than one hour. If instead, the capacitor is discharging for only a short time and then left on open circuit, a voltage builds up between the electrodes, the residual voltage increases with rise in ambient temperature and the time of initial polarisation. The reappearance of voltage across the capaci tor when it is intended to be unpolarised could be troublesome in circuits such as those used in computers and triggering circuits unless the circuit is suitably designed to allow for this condition.
High Ambient Temperature When this type of capacitor has to be used in high ambient tempe ratures, it must be remembered that the leakage current increases ten-fold for a 50 °C rise. Because of this, it is often necessary to derate the working voltages. Series Resistance Often the impedance of a capacitor is of greater importance than its capacitance. A capacitor should be rejected if the following properties exceed stipulated limits : (1) the impedance, measured at 50 Hz if the capacitance is signi ficant, measured at 100 Hz if the series resistance is significant (2) loss factor measured at 50 Hz (3) leakage current Source Impedance Catastrophic failures of this type of capacitor can be reduced by the user if he provides an adequate series resistance in the circuitry, because these capacitors tend to self-heal under proper circuit conditions, but where a sudden inrush of current does occur the capacitor can be destroyed. Several complaints have been made 216
Chip Capacitors in Hybrid Microelectronics of open circuit, increase in DC leakage current and short circuits, the latter two are usually caused by dielectric fractures at thin spots in the dielectric. These thin spots are due to impurities or contamination both of which resist the initial oxide formation during anodisation. These impurities produce an oxide film that is effectively thinner than that of a clean pure tantalum powder. The thin areas which are probably deep in the porous anode rupture under voltage or temperature stress allowing a localised current inrush. In consequence the leakage current may increase or decrease or show no change from its initial value, but this action can also result in short circuit failure. During current inrush, heat is generated in the immediate area. This Uberates oxygen from the manganese dioxide M^Ogi- Fortunately, two reactions occur to heal the defect site. First the freed oxygen combines with the exposed metallic tantalum material to reform the dielectric film, secondly, the formally conductive at the hot spot is reduced to a lower manganese oxide of high resistivity. This combination can effect a healing of the defect site if the inrush current is limited. Scintallations are caused by impurities and it is well known that manufacturers 'burn in' capacitors in their production process in an attempt to eliminate gross defects. Derating of Working Voltage Care must be taken to ensure that the DC bias is not so reduced as to cause a reversal of polarity on a polarized capacitor. To pre vent such an occurrence the peak value of any AC component must not exceed the applied DC bias. Reversed Polarity Polar tantalum capacitors should not be operated continuously at a reversed voltage exceeding 1 V at between 20 °C and 85 °C or 0-65 V from 85 °C to 125 °C. Leakage Leakage denotes the amount of direct current (not charging) that will flow steadily through a capacitor. This is an important consi deration when the capacitor is used in coupling or other applications 15
217
Compatibility and Testing of Electronic Components where DC voltage is imposed. When a soHd tantalum capacitor is polarised for a period of five seconds, the leakage current is appreciable, but drops towards a steady value. This condition could be important during the warming up period in equipment where a standing voltage is required at switch on. Improvements There is a considerable inefficiency within the discrete package of the canned capacitor and an obvious improvement would be to utihse the processed and silver coated tantalum anode directly in hybrid circuit apphcations. The silvered coating serves as the negative connection to the capacitor element. The positive connec tion is made by means of a gold plated tab wire which has been welded to the anode riser. Similar versions of tantalum chip capa citors utilise finer grain powders to achieve yet a further increase in volumetric efficiency. Another type is designed to minimise cost whilst sacrificing some volumetric efficiency. The positive connection is completed via a solder coated crossbar welded to the tantalum riser which means the weld is well away from the riser so the welding operations can be performed on automatic equipment. This type of chip is primaily designed for hybrid circuit modules where the highest volume effici ency is not required, as in the commercial and entertainment eqipment, but rather the lowest possible cost, including not only the component cost, but assembly labour and packaging rehability costs. Reflow Solder Some types of terminations are designed to be assembled into the circuit by means of solder application. One of these is where the tantalum chip is reflow soldered, the soldering operation being carried out in a hot air oven. In this operation it is necessary to control temperature and time. Figure 19.1 illustrates the time and temperature parameters for this operation. Exceeding these can result in the degradation of the parametic performance of the chip capacitor, particularly with regard to dissipation factor and equi valent series resistance. This is due to the scavenging of the silver layer by dissolution in the molten solder. 218
Chip Capacitors in Hybrid Microelectronics
I902002KD 2 2 0 2 3 0 2 4 0 2 5 0 2 6 0 Temperature °C
Figure 19.1. Safe mounting time/temperature parameters for tantalum chip capacitors using a SN-62 solder.
Hand Soldering The placeing of tantalum chip capacitors can also be accompli shed by soldering with a small iron or reflow heat pulse, infrared, or by hot plate techniques. The solder used in these assemblies should contain some silver to minimise scavenging of the silver from the negative electrode. A composition such as Sn 62 % (36 % Pb— 2% Ag)is suitable. Non Solder For this method of attachment the chip is pre-assembled to a ceramic substrate after which it may be subjected to life testing, thermal shock and parameter drift screening prior to use. With the chip pre-assembled to the substrate, the dangers of damage during assembly into the ultimate package are minimised. The substrate is generally fixed to the package substrate by epoxy bonding and the electrical connections are made by interconnection wires to gold plated positive and negative tabs on the chip substrate, or the tabs themselves may be soldered to the hybrid substrate. High Temperature Tantalum Chip Capacitors The previously described chip capacitors have been successful in hybrid circuits using thick film technology along with encapsulated semiconductor devices where the assembly, storage, conformal 219
Compatibility and Testing of Electronic Components coating, and/or package sealing temperatures have been limited to approximately 150 °C and where the storage and operating temper ature ranges have been confined to 125 °C. Attempts to use these chips in hybrid circuits employing thin films or unprotected semi conductors have been unsuccessful because the use of solder with flux as a means of interconnection and attachment cannot be tolerated. In addition, attempts to use solder coated chips or just silver coated chips attached by epoxy bonding and interconnection by ultrasonic wire bonding has met with only marginal success. In these apphcations there is a requirement for bake-out of the package coupled with subsequent heremetic sealing. These opera tions involve temperatures ranging to 300 °C and occasionally operating temperature of 200 °C. Under these conditions there is a significant degradation of the tantalum chip electrode system, and a further problem due to contamination within the package after sealing from the byproducts of the breakdown of the silver cathode surface. Occasional difficulties are also encountered where the assembly temperature, even in thick hybrid circuits, exceeds the time-temperature relationship. In these cases decomposition and delamination of the silver counterelectrode occurs which leads to a significant increase in the equivalent resistance of the device. To obviate the above problems along with the possible contami nation which may occur from elements of the tantalum chip capa citor itself, a new counterelectrode has been designed. The silver/ solder coating has been completely replaced with thin homogene ous solid copper coating, and with this coating the chip capacitors are capable of sustained storage or assembly temperatures up to 250 °C and operating temperatures up to 200 °C. Tests carried out show that due to the lo\^' solubility of copper compared to silver in solder, there is no degradation of the copper electrode. In addi tion, since there is no silver paint present there can be no decomposi tion products to contaminate other portions of the hybrid circuits by the formation of gas pockets or delamination of the counter electrode from the anode. The copper may be pre-tinned with solder or other materials for re-flow solder applications or with gold plated tabs affixed directly to the copper surface for ultrasonic wire bonding.
220
Chip Capacitors in Hybrid Microelectronics Performance Data Figures 19.2, 19.3 and 19.4 show the parametric performance of both conventional and copper clad tantalum chip capacitors on a 1000 hours 125 °C full rated voltage life test. The capacitance, dissipation factor and DC leakage parametric stability are typical of those obtained with conventional types. The response of the tanta-Conventional Counterelectrode
|iOO '^Χ"""""" o
5
^
Improved-""^
^
95
O
lOO
200 300 400 500 600 700
8 0 0 9 0 0 lOOO
Test time h
Figure 19.2, 125°C life test performance, tantalum chip capacitor 2-6 μ¥ 20 V rating. The full line represents on improved counterelectrode.
Conventional Counterelectrode ^XImproved
Ο
lOO 2 0 0
300 400 500 600 Test tinne h
TOO 8 0 0 9 0 0
lOOO
Figure 19.3. 125°C life test, 26 μ¥, 20 Y.
o
ΙΟΟ 2 0 0
300
4 0 0 5 0 0 6 0 0 7 0 0 8 0 0 9 0 0 ΙΟΟΟ Test time h
Figure 19.4. 125°C life test, 2-6 μ¥ 20 V.
221
Compatibility and Testing of Electronic Components lum chip capacitors to extremes of humidity conditions is that the capacitance increases very rapidly on exposure to high ambient humidity. After 100 h of the wet condition the capacitors were baked-out at 125 °C and the typical capacitance drop due to the removal of absorbed moisture was observed. These changes in capacitance with humidity/bake-out cycle can be repeated many times with no apparent degredation of the capacitor element or electrical performance. Extended exposure to a very wet condition will eventually cause a degradation of the DC leakage parameter due to ionic contamination carried into the capacitor element by the moisture but the point becomes academic in a sealed package. In thick film hybrid applica tions where the package is not hermetically sealed, conformal coatings such as polyurathane or silicon varnieshes have been found effective in impeding the ingress of moisture. Figure 19.5 illustrates the impedance versus frequency perform ance of a 1 μΕ ceramic chip and a 1 μΡ tantalum chip. At both the low and high frequencies the performance is similar, but in the lO
I
I"
o Ceramic Chip
Ol
OOl lOK
lOOK
IM lOM Frequency Hz
lOOM
IG
Figure 19.5. Chip capacitor impedance versus frequency I uF 25 V.
lOOK
IM Frequency Hz
lOOM
Figure 19.6. Tantalum chip capacitor with improved counterelectrode.
222
Chip Capacitors in Hybrid Microelectronics region of 6 Mhz the ceramic displays a series resonance due to the inherent lower equivalent series resistance whilst the tantalum chip impedance appears resistive. In fast pulse circuits this highly damped impedance can be used to decrease or eliminate ringing, oscillations and resonances set up between the capacitor element and the inductance of the interconnections. Figure 19.6 shows the impedance versus frequency of the improved copper clad tantalum chip capacitor.
CERAMIC CHIP
CAPACITORS
Single layer chip capacitors, small versions of conventional single layer ceramic discs or plates, can be used but are limited in maximum value to 1 000 pF. In the highest values they are extremely fragile due to the dielectric thickness, the minimum practical thickness be ing between 0127 mm and 0-254 mm. Furthermore, it is often inconvenient to the user to have the terminations on opposite faces and special shapes of electrode have to be used to put both terminations on the same face, this reduces the maximum capaci tance available in a given chip size. Monolithic chip capacitors, consisting of up to twentyfive layers of dielectric, each as thin as 0-0254 mm extend the upper limit of capacitance by one hundred times. Terminations can be brought to one face without any significant reduction in capacitance and here is also an advantage in this type of construction at the lower values of capacitance, which could be achieved with only one layer of dielectric. In these cases, the chip is made robust enough to handle by adding dummy or insulating layers. Also material finishes can be made suitable for the user's bonding techniques, ensuring compati bility with semiconductor devices used on the same substrate. Construction This is effected by dispersing dielectric powder inorganic binders and solvents and then casting the shp so formed to yield a flexible film that can be printed with the necessary electrode shape using ink or paint made from a dispersion of a noble metal of high melting point. The necessary number of layers are stacked, cut into shape by punching and consolidated by pressing in a die. 223
Compatibility and Testing of Electronic Components Accurate location of the electrodes is necessary so that their edges can be exposed alternatively on opposite edges of the 'green' ceramic chip so formed. Firing burns out the organic materials and sinters the dielectric and electrode layers into a solid block. The electrodes are connected together and terminated as required, either before or after firing. Almost any ceramic formulation can be used depending on the temperature characteristics required. For general purposes, where a 20% variation over a 200 °C range can be permitted, capacitance of 5 000 pF/mm^ can be achieved for a rated voltage of 50 to 100 DC. Where the temperature range is restricted, allowing the use of the highest permittivity ceramics, and the working voltage is low, it is possible to achieve up to 50 000 pF/mm^. The range of monolithic capacitors offer the user a large number of capacitors in a wide range of materials. Six different compositons ranging from K-35, with 0% TC to K-8000 with the usual peaky shape of a TC curve associated with high permittivity material, and have three sizes shown in Table 19.1. The standard range have Table 19.1 R A N G E O F MONOLrraiC CAPACITORS
Approximate Mate TC rial (_60o to Κ + 140°C)
Size number (mm)
1
2
Nominal size (mm)
2ΐχ1ι
3iX3i
Tolerances available
3
Capacitance (in pF up to 8200 in μΡ above)
35 0%
±5%, :-I0% ±20%
15 to 100
110 to 430
470 to 1500
90
±5%, ±10% ±20%
36 to 240
270 to 1500
1600 to 3600
240 ±10%
±10%, ±20%
100 to 680
820 to 3900 4700 to 0 0 1
800 - 1 5 %
±10%, ±20%
330 to 2200
2700 to 0012 0015 t o 0 0 3 7
2400 —20%
±10%, ±20% 1000 to 6800
8000 —10°to + 70°C - 2 0 % + 80% —50%
224
8200 to 0039 0047 too-11
3300 to 0022 0-033 to 0 1
0 1 5 to 0-33
Chip Capacitors in Hybrid Microelectronics terminations brought to one side and made of sintered palladium, satisfying most of the different requirements of weldabihty and solderability. Silver terminations, besides being restricted to solder ing only, have technical limitations when operated at high tempera tures and high DC voltage stress, due to silver migration. This can cause fairly rapid deterioration of the insulation of high Κ ceramics. Aging All ceramic dielectrics in the barium titanate class (i.e. high permit tivity) have an inherent aging characteristic. This is approximately — 2% and —5% per logarithic decade hours respectively. These units should be within their stated selection tolerance at 1 000 h, that is: 4 h from 0-1 h after operation in a temperature of +120 °C the capacitance will return to its initial 0-1 h value and the aging cycle resume. These capacitors are suitable for bypass and coupling applications or for frequency discriminating circuits where low loss and high stability are not of major importance. The uses of ceramic capacitors of various permittivities are as follows: (1) Low K, for temperature compensating purposes where stan dard values of temperature coefficients are essential, they are also specifically suited for resonant circuit applications or other uses where low loss and high stability are essential. (2) Medium K, for general purposes, where standard values and tolerances for temperature coefficients are suitable. (3) High K, (2 400) for general purpose, where wide tolerances on temperature coefficients are acceptable. (4) High K, (8 000) for general purpose but with still wider tolerances on temperature coefficients and less stringent requirements on the stability of capacitance.
225