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CMOS NAND and NOR Schmitt circuits
MicroelectronicsJournal27 (1996) 757-765 Copyright O 1996 Elsevier Science Limited Printed in Great Britain. All rights reserved 0026-2692/96/$15.00 ELSEVIER
PII: S0026-2692(96)00009-2
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CMOS NAND and NOR Schmitt circuits Branko L. Doki6 Faculty of Electrical Engineering, University of Banja Luka, Trg Palih Boraca 2/11, 78000 Banja Lu/ea, Serbia
Original solutions of m-input NAND and NOR logic circuits with hysteresis :in the transfer characteristics are proposed. Multiple inputs are done similarly to standard NAND and NOR logic circuits. The logic circuits proposed in this paper consist of2m + 1 pairs of enhancement CMOS transistors. The hysteresisvoltage depends on supply voltage and transistor geometry. The proposed solutions always guarantee hysteresis,even with very large process variations. The noise immunity is typicallygreater than 50% of supply voltage. Analysis using simple device models together with computer simulations and experimental results is given. Copyright © 1996 Elsevier Science Ltd. 1. Introduction
n the conventional simple digital N O R and N A N D gates at any point in time the output Iis directly related to the input by some logic combination. Therefore, these circuits are k n o w n as combinational logic circuits. A characteristic of combinational circuits is the lack o f intentional connections between outputs and inputs. There is another class of circuits, k n o w n as sequential logic circuits, in which the outputs are also dependent on preceding values o f input data. A characteristic o f sequential circuits is that one or more output nodes are intentionally connected back to inputs to give positive feedback, i.e. regeneration. Therefore, these circuits are also k n o w n as regenerative circuits.
C o m m o n examples o f these circuits are the multivibrator circuits (the bistable circuits - latches and flip-flops, the monostable circuits and the astable circuits). Another family o f regenerative circuits, particularly useful in digital systems, is the Schmitt trigger [1-5]. A characteristic o f these circuits is that the voltage transfer characteristic has different input threshold for positive-going and negative-going voltage signals. Therefore, there is hysteresis in the transfer characteristic. Another important feature is that this circuit responds to a slowly changing input waveform with a fast transition at the output. If the output of the Schmitt trigger is directly related to the input by some logic combination, such a circuit is k n o w n as the Schmitt trigger logic circuit. C o m m o n examples of these circuits are the N A N D and N O R Schmitt triggers. Original solutions of m-input N A N D and N O R Schmitt triggers are described in this paper. They consist only o f enhancement transistors and can be implemented using conventional C M O S technology. T h e circuits are simple and demonstrate hysteresis even with very large process variations. This is an important feature in comparison with N A N D and N O R circuits described in [2].
757
%
Branko L. Doki#/NAND and NOR circuits
+V~
+VDo
1
TM
&
1
V,
Vi
V,
+V~
(a)
~"
(b)
I
"T
Ve
l'i '
o
-[
+V~
Tm
1"
Fig. 1. Schmitt trigger-inverter with three pairs of CMOS transistors.
2. Schmitt trigger-inverter The basic circuit is the Schmitt trigger-inverter [1] with three pairs of CMOS transistors (Fig. 1). Transistors Tn and Tp form the standard inverter I (Fig. lb). Transistors Tn0, T~ and Tp0, Tp are operating as the inverting NMOS and PMOS amplifier, respectively. They also introduce hysteresis by feeding back the output voltage to points 1 and 2. To describe the circuit, assume the threshold voltages of all NMOS and PMOS transistors are Vm and Vtp, respectively. Constants f of the transistors Tno and Tpo are fn0 and fp0, and constants f of the other NMOS and PMOS transistors are fn and flip, respectively, where -- JL/ng°X Wn
fin
2tox Ln
and
fp __ ]-/pgox Wp tox Lp
/~ is the mobility of the carders in the channel, gox the oxide dielectric constant, tox the oxide thickness, L the channel length and W the channel width. Now with Vi = 0 V, the two stacked p-channel transistors Tp and T'p will be on with negligible conducting drain current, since Tn and T" are off, and Vout = VDD. The transistor Tp0 is off',
758
and Tn0 is at the threshold of conduction and V1 -- VDD -- Vtn-When Vi rises to Vm T'n starts to turn on, but Tn is offbecause V1 > Vm. Now T'n and Tn0 are in the saturated region and form the inverting NMOS amplifier with a voltage gain of about - A (2). Namely, with equalization of the drain current of Tn0 and T'n V1 is given by V1 = VDD -- V m - An(Vi -
Vm)
(1)
where
An --
~f ~n / Wn/Ln V = VW.GnO
(2)
Thus, as Vi rises, V1 is falling. At Vi = V1 + Vtn, Tn turns on. Then Tp0 is off so that the series transistors T'p and Tp can be replaced by an equivalent one with constant f [6] fpe = f p / 2
(3)
When both the T n and equivalent PMOS transistors are in saturation, regenerative switching is about to take over and the output rapidly goes to 0V, turning off Tn0 and turning on Tp0. The input voltage at which these changes occur is the high threshold Vt+ of the Schmitt trigger. The
Microelectronics Journal, Vol. 27, No. 8
currents of the Tn and equivalent PMOS transistors are equal so t]hat fin(V + - V 1 -
Vtn) 2 = flpe(VDD q- Vtp - V + ) 2
(4)
so that V t _A p ( V D D + Ytp) + B2Ytn 1 + Ap + B2 where
where V1 is given by eq. (1) with Vi = V +. Combining eqs. (4) and (1), we obtain V+ = VDD+
Vtp--I-BI(VDD+AnVtn)
(5)
1 + B1 (1 + An) where (6)
V-g
Assume that the input voltage Vi decreases from VDD to 0V. For Vi = VDD Tp, T'p and T,o are off, Tn and T" are on, and Tpo is at the threshold of conduction. That is Vo = 0 and V2 = ]Vtv]. The transistor Tp turns on at Vi = VDD + Vtp. As Tp and Tpo are saturated, V2 increases linearly as V,. decreases, and is given by 172 = Ap (VDD + Vtp - Vi) - Vtp
(11)
(12)
Vg
Besides the supply voltage, the threshold voltages Vt+ and V t depend on the ratio of transistor fl constants. The optimal characteristics will be when transistors' Tn, Ttn, Tp and Tpi fl constants are equal. Then, V + and V t depend on the transistors' Tn0 and Tp0 geometry if the supply voltage is constant (Fig. 2). Figure 3 shows the average propagation delay time, obtained by computer simulation using the program SPICE as a function of the constants An = Ap and the capacitive load at VDD = 5 V. The simulation was made for parameters of the vt*, vt-lvl 8
(7)
where
(8) =
VflPO=
VWpo-"~pO
Vt-
With Vi = V2 + Vtp, Tp turns on. Then Tn0 is off so that Tn and T'n can be replaced by an equivalent transistor with constant fl [6] fine = fin~ 2
When the equivalent NMOS and Tp transistors are saturated, the regenerative process takes place and V0 rapidly goes to VDD, turning off Tp0 and turning on Tn0. Then the input voltage is equal to the low threshold voltage V~-. Thus, at Vi = V t we obtain f i n e ( V ; - --
Vtn)2 = tip(V2 +
Vt
(9)
Vq, -
V~-) 2
(10)
0 0.2
= 1.2
i 2,2
i 9.2
i 4.2 2 2 A n - Ap
Fig. 2. The threshold voltages Vt+ and V t as a function of the ratios (Wn/Ln)/(Wno/Lno) = (Wp/Lp)/(Wpo/Lpo) at VDD = 5 V and VDO = 10V given by SPICE.
759
Branko L. Doki6/NAND and NOR circuits
t d [ns}
of the circuit in Fig. 4 will be low only when all inputs are high, i.e. Z = X1X2 . . . . ,Xm SO that Z = X 1 X 2 . . . . ,Xm. Hence this is an m-input N A N D gate.
200
The output of the circuit in Fig. 5 will be ! I high only when all inputs are low (Tpl .... ,Tpm and PMOS transistors of the conventional N O R gate are connected in series and must be conducting), i.e. Z ~ . X 1 X 2 , . . . , X m or Z = X1 + X2 + , . . . , + Xm. Hence this is an minput N O R gate.
150
,oo 50
........o12 ...............................................
..................................................................................................................................................................................
CL'lpF
0.2
I
I
I
l
1.2
2.2
3.2
4.2 2
2
An - Ap
Fig. 3. Average propagation delay time as a function of (Wn/Ln)/(Wno/L,o) = ( W p / L p ) / ( W p o / L p o ) and capacitive load CL. 2 #m C M O S technological process. For An = Ap > 1 the propagation delay time almost does not depend on the Tn0 and Tp0 geometry. Therefore, by controlling the hysteresis through change An and Ap (Fig. 2), the propagation delay time is nearly held constant.
3. NAND and NOR circuit design Thus, the Schmitt trigger-inverter (Fig. 1) consists of one conventional C M O S inverter (Tn, Tp), one N M O S inverter (T'n, Tn0) and one PMOS I inverter (Tp, Tp0 ). The same principle is used for design of the new N A N D and N O R Schmitt circuits shown in Figs. 4 and 5 which are proposed in this paper. In this case conventional CMOS, N M O S and PMOS N A N D and N O R gates are used instead of the corresponding inverters. Since the transistors Tnl,...,Tnm t and the N M O S transistors of the conventional C M O S N A N D gates are connected in series, the output
760
Transistors Tn0 and Tp0 provide feedback to effect rapid change of the output voltage and the transfer characteristic has the shape of the hysteresis curve. Hence the circuits in Figs. 4 and 5 are m-input N A N D and N O R Schmitt circuits, respectively. 3.1 NAND circuit analysis 3.1.1 DC characteristics Parallel or series transistors can be replaced by one transistor such as the conventional N A N D and N O R circuits [6]. In this way, N A N D and N O R Schmitt circuits can be replaced by an equivalent Schmitt trigger-inverter (Fig. 7) by dc analysis. It will be shown by analysing an minput N A N D Schmitt circuit (Fig. 6).
Assume that n inputs are active, where 1 ~
(13) 2 The equivalent constant fl of series transistors depends on the number of transistors and position of the first active input [6]. Consequently,
Microelectronics Journal, Vol. 27, No. 8
+VDa
T
A
2
T~
1
v,
2 {~..r.-.
w
T~ !
; +Vaa
|-
Ill.;
iL5
IF- ~ TI~' Fig. 4. m-InputNANDSchmittcircuit. for the case of n a;ctive inputs the transistors T , b . . . , T n m and T nl,... ,T'nm can be replaced by the equivalent transistors Tne~ and The2, respectively, whose constants fl are given by fine1 =
fine2
m
fin m -- k + 1
(14)
Ane = , /-fln~2----A n ( m - k + 1)-1/2
Vfln0
Ble =
fl~l = B l [ n ( m - k + 1)]-1/2
V/3p0
(15)
(16)
where k marks the position of the first active input (for example, if k = 3 the inputs of the transistors Tnl, T'nl and Tn2, Tin2 are at VDD, and Tn3, T',3 are at Vi).
where An and B1 are given by eqs. (2) and (6), respectively.
Now, the ratios of Tne2 to Tn0, and Tn~l to Tpe are given by
From eq. (5), replacing An by Ane and B1 by Bie we obtain the high threshold voltage of the minputs N A N D Schmitt circuit
761
Branko L. Dokid/NAND and NOR circuits
+Vim
I
IF
Trm"
In =
i
TpI'
T~'
T~
1 2
v.
m
T Tu,
Fig. 5. m-Input N O R Schmitt circuit.
Vt+ = VDD + Vtp +
Bl[n(m - k +
1 + Bl[n(m - k +
1)1-1/2 [VDD + A n ( m
~n
762
1)-1/2 Vtn]
1)] -1/2 [1 +An(m - k + 1) -1/2]
To calculate V [ the circuit in Fig. 4 can be replaced by an equivalent one shown in Fig. 7b. Namely, T,0 is off. T n l , . . . ,Tnm, T nll , • .. , T n Im are on and can be replaced by an equivalent one Tne with the constant fl [6]
~ne --~ ~ m
- k +
(18)
(17)
is o n . Tpi and T p'i (i ---- 1 , . .. , n ) with active input can be replaced by equivalent transistors Tpel and Tpe2, respectively, with the constants fl Tp0
flpel • flpe2 ~---nflp
(19)
The fl ratios of Tve2 to Tvo, and The to Tpel, respectively, are given by:
Microelectronics Journal, Vol. 27, No. 8
Ape
]
=
Apn 1/2,
(20)
= B2(mn) -1/2
(21)
=
ll'J~ T~,•
1. ~.
=
.
B2e
_Vo
v,,
From eq. (11), replacing Ap by Ape and B2 by B2e, we obtain the low threshold voltage of the m-inputs N A N D Schmitt circuit
t.
Vt
X!
=
Apnl/2(VDD + Vtp) + B2(mn)-l/2Vm 1 -t- Apn 1/2 + B2(mn) -1/2
X.--
rTT
.+v=,
(22)
T~ I-- Tin"
where Ap and B2 are given by eqs. (8) and (12), respectively.
-h i i
Fig. 6. Complete scheme of the m-input N A N D Schmitt circuit.
The threshold voltages Vt+ and V t depend on supply voltage VDD, the ratio of the constants fin~tip, tin/tinO, i.e. ti-/tipO, number of inputs m, and number of actfve inputs n. Besides, Vt+ depends on the position of the first active input k.
+V~
+V~
V.
i
+VDo
ttt
:
111
Jr.
VI =
T~
(a) Fig. 7. Equivalent circuit of m-input N A N D or N O R circuit (a) at
Co)
Vo =
VDD, and (b) at V0 = 0V.
763
Branko L. Dokid/NAND and NOR circuits
Vm~=IOV
10
8 6
ii~ ii
i
ii
v, [Vl
X~; !:
4 iii X2 : [
3
4
.i
6
7 8
(a) 10
8 l~[mA] 46
ii
i ~] ~
ii
2
!
3 (b)
5
6
7 $
v, IV]
Fig. 8. Oscillograms of (a)voltage and (b) current transfercharacteristicof the two-input N A N D
3. 1.2 Measurements and computer simulation Measurements and computer simulation are made on a two-input N A N D Schmitt circuit. An experimental model was built using C M O S integrated circuits of type CD4007 (dual complementary pair plus inverter). Oscillograms of the voltage and current transfer characteristics of the two-input N A N D Schmitt circuit for various numbers and combinations of active inputs are shown in Fig. 8. Figure 8 confirms that V + depends and V t does not depend on the combination of active inputs. Namely, when first input X1 is active only ( n = l , k = l ) V + = 6.1V, and for the second input active only (n = 1, k = 2) V + = 6.7V. In both cases, V t = 3.8V. This was also confirmed by SPICE
764
Schmitt circuit.
simulation (Fig. 9). Simulation was made at VDD ----5 V with parameters o f the 2 # m C M O S process. 3.2 NOR circuit
As the N O R circuit is obtained from the N A N D one through the interchange of the pchannel and n-channel transistors and a power supply polarity change, the previous analysis can be applied analogously to this circuit. In this way we obtain
V~+=
VDD + Vtp + BI(mn)I/2(VDD + Annl/ZVtn)
1 + Bl(mn)l/2(1 +Annl/2) (23)
Microelectronics Journal, Vol. 27, No. 8
- A p ( m - k + I'-I/2(VDD + Vtp) + B2[n(m - k + 1)]t/2 Vtn
Vt
1 +Ap(m
-
-
k + 1) -1/2 + B 2 [ n ( m - k + 1)] 1/2
Vt*, Vt- [V]
4'5l 4
a.5
............................................................................................................................................................................
}i-2 .....................................
............................................................................
2.5"2 ~
..............................
1,5~ I
0.2
I
l
l
I
I
i
i
0.7
1.2
1.7
2.2
2,7
3.2
3.7
AS. Fig. 9. SPICE values of Vt+ and V~ for two-input NAND circuit versus (W,,/L,,)/'(W,,o/L,,o) = (Wp/Lp)/(Wpo/Lpo) for various numbers and combinations of active inputs at VDr) = 5 V and for optimum geometry ratio of NMOS and PMOS transistors [6], that is at fin~tip = 2. Therefore, the threshold voltages depend on exactly the same parameters as the thresholds o f the N A N D circuit except that in the N O R circuit V~- depends on the position o f the first active input k. 4. Conclusion The basic circuit for N A N D and N O R Schmitt circuit design is the 5;chmitt trigger-inverter with six M O S transistors. Multiple inputs are realized by adding series and parallel pairs o f M O S transistors per input (one N M O S pair and one
(24)
P M O S pair). As with the conventional C M O S gates the N A N D Schmitt circuit is obtained w h e n pairs o f N M O S transistors are in series and P M O S are parallel, and for the N O R Schmitt circuit it is the opposite. The total number o f transistors o f an m-input circuit is 2(2m + 1). The voltage hysteresis depends on supply voltage Vrm, threshold voltage and geometry o f transistors, as well as on the number o f inputs and number o f active inputs and combinations o f active inputs. The hysteresis increases with increasing geometry o f the transistors Tn0 and Tp0 in the feedback loop relative to the geometry o f the other transistors. W h e n the W / L ratio o f the transistors Tn0 and Tp0 is less than W / L o f the other transistors the average propagation delay time almost does not depend on the Tn0 and Tp0 geometry. It is worth noting that the described circuits always guarantee hysteresis, even with very large process variations. References [1] B.L. Doki~, CMOS Schmitt triggers,lEE Proc., 131(5) (Oct. 1984) 197-202. [2] B.L. Doki8 and Z.V. Bundalo, Regenerative logic circuits with CMOS transistors, Int. J. Electron., 58(6) (1985) 907-920. [3] Zhenhua Wang, CMOS adjustable Schmitt triggers, IEEE Trans. Instrum., 40(3) (June 1991) 601-605. [4] Daejeong Kim, Joongsik and Wonchan Kim, A new waveform reshaping circuit: an alternative approach to Schmitt trigger, IEEEJ. Solid-State Circuits, 28(2) (Feb. 1993) 162-164. [5] J. Exalto, HCMOS Schmitt-trigger applications, Electron. Components Applications, 7(3) (1985) 144-151. [6] B.L. Doki~, Influence of series and parallel transistors on DC characteristicsof CMOS logic circuits, Micro° electronicsJ., 13(2) (March/April 1982) 25-30.
765
PII: S0026-2692(96)00009-2
[ii~iiiiiiii
i!i!i!O!iiiil] iii!~ii~iiiiii! ~
CMOS NAND and NOR Schmitt circuits Branko L. Doki6 Faculty of Electrical Engineering, University of Banja Luka, Trg Palih Boraca 2/11, 78000 Banja Lu/ea, Serbia
Original solutions of m-input NAND and NOR logic circuits with hysteresis :in the transfer characteristics are proposed. Multiple inputs are done similarly to standard NAND and NOR logic circuits. The logic circuits proposed in this paper consist of2m + 1 pairs of enhancement CMOS transistors. The hysteresisvoltage depends on supply voltage and transistor geometry. The proposed solutions always guarantee hysteresis,even with very large process variations. The noise immunity is typicallygreater than 50% of supply voltage. Analysis using simple device models together with computer simulations and experimental results is given. Copyright © 1996 Elsevier Science Ltd. 1. Introduction
n the conventional simple digital N O R and N A N D gates at any point in time the output Iis directly related to the input by some logic combination. Therefore, these circuits are k n o w n as combinational logic circuits. A characteristic of combinational circuits is the lack o f intentional connections between outputs and inputs. There is another class of circuits, k n o w n as sequential logic circuits, in which the outputs are also dependent on preceding values o f input data. A characteristic o f sequential circuits is that one or more output nodes are intentionally connected back to inputs to give positive feedback, i.e. regeneration. Therefore, these circuits are also k n o w n as regenerative circuits.
C o m m o n examples o f these circuits are the multivibrator circuits (the bistable circuits - latches and flip-flops, the monostable circuits and the astable circuits). Another family o f regenerative circuits, particularly useful in digital systems, is the Schmitt trigger [1-5]. A characteristic o f these circuits is that the voltage transfer characteristic has different input threshold for positive-going and negative-going voltage signals. Therefore, there is hysteresis in the transfer characteristic. Another important feature is that this circuit responds to a slowly changing input waveform with a fast transition at the output. If the output of the Schmitt trigger is directly related to the input by some logic combination, such a circuit is k n o w n as the Schmitt trigger logic circuit. C o m m o n examples of these circuits are the N A N D and N O R Schmitt triggers. Original solutions of m-input N A N D and N O R Schmitt triggers are described in this paper. They consist only o f enhancement transistors and can be implemented using conventional C M O S technology. T h e circuits are simple and demonstrate hysteresis even with very large process variations. This is an important feature in comparison with N A N D and N O R circuits described in [2].
757
%
Branko L. Doki#/NAND and NOR circuits
+V~
+VDo
1
TM
&
1
V,
Vi
V,
+V~
(a)
~"
(b)
I
"T
Ve
l'i '
o
-[
+V~
Tm
1"
Fig. 1. Schmitt trigger-inverter with three pairs of CMOS transistors.
2. Schmitt trigger-inverter The basic circuit is the Schmitt trigger-inverter [1] with three pairs of CMOS transistors (Fig. 1). Transistors Tn and Tp form the standard inverter I (Fig. lb). Transistors Tn0, T~ and Tp0, Tp are operating as the inverting NMOS and PMOS amplifier, respectively. They also introduce hysteresis by feeding back the output voltage to points 1 and 2. To describe the circuit, assume the threshold voltages of all NMOS and PMOS transistors are Vm and Vtp, respectively. Constants f of the transistors Tno and Tpo are fn0 and fp0, and constants f of the other NMOS and PMOS transistors are fn and flip, respectively, where -- JL/ng°X Wn
fin
2tox Ln
and
fp __ ]-/pgox Wp tox Lp
/~ is the mobility of the carders in the channel, gox the oxide dielectric constant, tox the oxide thickness, L the channel length and W the channel width. Now with Vi = 0 V, the two stacked p-channel transistors Tp and T'p will be on with negligible conducting drain current, since Tn and T" are off, and Vout = VDD. The transistor Tp0 is off',
758
and Tn0 is at the threshold of conduction and V1 -- VDD -- Vtn-When Vi rises to Vm T'n starts to turn on, but Tn is offbecause V1 > Vm. Now T'n and Tn0 are in the saturated region and form the inverting NMOS amplifier with a voltage gain of about - A (2). Namely, with equalization of the drain current of Tn0 and T'n V1 is given by V1 = VDD -- V m - An(Vi -
Vm)
(1)
where
An --
~f ~n / Wn/Ln V = VW.GnO
(2)
Thus, as Vi rises, V1 is falling. At Vi = V1 + Vtn, Tn turns on. Then Tp0 is off so that the series transistors T'p and Tp can be replaced by an equivalent one with constant f [6] fpe = f p / 2
(3)
When both the T n and equivalent PMOS transistors are in saturation, regenerative switching is about to take over and the output rapidly goes to 0V, turning off Tn0 and turning on Tp0. The input voltage at which these changes occur is the high threshold Vt+ of the Schmitt trigger. The
Microelectronics Journal, Vol. 27, No. 8
currents of the Tn and equivalent PMOS transistors are equal so t]hat fin(V + - V 1 -
Vtn) 2 = flpe(VDD q- Vtp - V + ) 2
(4)
so that V t _A p ( V D D + Ytp) + B2Ytn 1 + Ap + B2 where
where V1 is given by eq. (1) with Vi = V +. Combining eqs. (4) and (1), we obtain V+ = VDD+
Vtp--I-BI(VDD+AnVtn)
(5)
1 + B1 (1 + An) where (6)
V-g
Assume that the input voltage Vi decreases from VDD to 0V. For Vi = VDD Tp, T'p and T,o are off, Tn and T" are on, and Tpo is at the threshold of conduction. That is Vo = 0 and V2 = ]Vtv]. The transistor Tp turns on at Vi = VDD + Vtp. As Tp and Tpo are saturated, V2 increases linearly as V,. decreases, and is given by 172 = Ap (VDD + Vtp - Vi) - Vtp
(11)
(12)
Vg
Besides the supply voltage, the threshold voltages Vt+ and V t depend on the ratio of transistor fl constants. The optimal characteristics will be when transistors' Tn, Ttn, Tp and Tpi fl constants are equal. Then, V + and V t depend on the transistors' Tn0 and Tp0 geometry if the supply voltage is constant (Fig. 2). Figure 3 shows the average propagation delay time, obtained by computer simulation using the program SPICE as a function of the constants An = Ap and the capacitive load at VDD = 5 V. The simulation was made for parameters of the vt*, vt-lvl 8
(7)
where
(8) =
VflPO=
VWpo-"~pO
Vt-
With Vi = V2 + Vtp, Tp turns on. Then Tn0 is off so that Tn and T'n can be replaced by an equivalent transistor with constant fl [6] fine = fin~ 2
When the equivalent NMOS and Tp transistors are saturated, the regenerative process takes place and V0 rapidly goes to VDD, turning off Tp0 and turning on Tn0. Then the input voltage is equal to the low threshold voltage V~-. Thus, at Vi = V t we obtain f i n e ( V ; - --
Vtn)2 = tip(V2 +
Vt
(9)
Vq, -
V~-) 2
(10)
0 0.2
= 1.2
i 2,2
i 9.2
i 4.2 2 2 A n - Ap
Fig. 2. The threshold voltages Vt+ and V t as a function of the ratios (Wn/Ln)/(Wno/Lno) = (Wp/Lp)/(Wpo/Lpo) at VDD = 5 V and VDO = 10V given by SPICE.
759
Branko L. Doki6/NAND and NOR circuits
t d [ns}
of the circuit in Fig. 4 will be low only when all inputs are high, i.e. Z = X1X2 . . . . ,Xm SO that Z = X 1 X 2 . . . . ,Xm. Hence this is an m-input N A N D gate.
200
The output of the circuit in Fig. 5 will be ! I high only when all inputs are low (Tpl .... ,Tpm and PMOS transistors of the conventional N O R gate are connected in series and must be conducting), i.e. Z ~ . X 1 X 2 , . . . , X m or Z = X1 + X2 + , . . . , + Xm. Hence this is an minput N O R gate.
150
,oo 50
........o12 ...............................................
..................................................................................................................................................................................
CL'lpF
0.2
I
I
I
l
1.2
2.2
3.2
4.2 2
2
An - Ap
Fig. 3. Average propagation delay time as a function of (Wn/Ln)/(Wno/L,o) = ( W p / L p ) / ( W p o / L p o ) and capacitive load CL. 2 #m C M O S technological process. For An = Ap > 1 the propagation delay time almost does not depend on the Tn0 and Tp0 geometry. Therefore, by controlling the hysteresis through change An and Ap (Fig. 2), the propagation delay time is nearly held constant.
3. NAND and NOR circuit design Thus, the Schmitt trigger-inverter (Fig. 1) consists of one conventional C M O S inverter (Tn, Tp), one N M O S inverter (T'n, Tn0) and one PMOS I inverter (Tp, Tp0 ). The same principle is used for design of the new N A N D and N O R Schmitt circuits shown in Figs. 4 and 5 which are proposed in this paper. In this case conventional CMOS, N M O S and PMOS N A N D and N O R gates are used instead of the corresponding inverters. Since the transistors Tnl,...,Tnm t and the N M O S transistors of the conventional C M O S N A N D gates are connected in series, the output
760
Transistors Tn0 and Tp0 provide feedback to effect rapid change of the output voltage and the transfer characteristic has the shape of the hysteresis curve. Hence the circuits in Figs. 4 and 5 are m-input N A N D and N O R Schmitt circuits, respectively. 3.1 NAND circuit analysis 3.1.1 DC characteristics Parallel or series transistors can be replaced by one transistor such as the conventional N A N D and N O R circuits [6]. In this way, N A N D and N O R Schmitt circuits can be replaced by an equivalent Schmitt trigger-inverter (Fig. 7) by dc analysis. It will be shown by analysing an minput N A N D Schmitt circuit (Fig. 6).
Assume that n inputs are active, where 1 ~
(13) 2 The equivalent constant fl of series transistors depends on the number of transistors and position of the first active input [6]. Consequently,
Microelectronics Journal, Vol. 27, No. 8
+VDa
T
A
2
T~
1
v,
2 {~..r.-.
w
T~ !
; +Vaa
|-
Ill.;
iL5
IF- ~ TI~' Fig. 4. m-InputNANDSchmittcircuit. for the case of n a;ctive inputs the transistors T , b . . . , T n m and T nl,... ,T'nm can be replaced by the equivalent transistors Tne~ and The2, respectively, whose constants fl are given by fine1 =
fine2
m
fin m -- k + 1
(14)
Ane = , /-fln~2----A n ( m - k + 1)-1/2
Vfln0
Ble =
fl~l = B l [ n ( m - k + 1)]-1/2
V/3p0
(15)
(16)
where k marks the position of the first active input (for example, if k = 3 the inputs of the transistors Tnl, T'nl and Tn2, Tin2 are at VDD, and Tn3, T',3 are at Vi).
where An and B1 are given by eqs. (2) and (6), respectively.
Now, the ratios of Tne2 to Tn0, and Tn~l to Tpe are given by
From eq. (5), replacing An by Ane and B1 by Bie we obtain the high threshold voltage of the minputs N A N D Schmitt circuit
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Branko L. Dokid/NAND and NOR circuits
+Vim
I
IF
Trm"
In =
i
TpI'
T~'
T~
1 2
v.
m
T Tu,
Fig. 5. m-Input N O R Schmitt circuit.
Vt+ = VDD + Vtp +
Bl[n(m - k +
1 + Bl[n(m - k +
1)1-1/2 [VDD + A n ( m
~n
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1)-1/2 Vtn]
1)] -1/2 [1 +An(m - k + 1) -1/2]
To calculate V [ the circuit in Fig. 4 can be replaced by an equivalent one shown in Fig. 7b. Namely, T,0 is off. T n l , . . . ,Tnm, T nll , • .. , T n Im are on and can be replaced by an equivalent one Tne with the constant fl [6]
~ne --~ ~ m
- k +
(18)
(17)
is o n . Tpi and T p'i (i ---- 1 , . .. , n ) with active input can be replaced by equivalent transistors Tpel and Tpe2, respectively, with the constants fl Tp0
flpel • flpe2 ~---nflp
(19)
The fl ratios of Tve2 to Tvo, and The to Tpel, respectively, are given by:
Microelectronics Journal, Vol. 27, No. 8
Ape
]
=
Apn 1/2,
(20)
= B2(mn) -1/2
(21)
=
ll'J~ T~,•
1. ~.
=
.
B2e
_Vo
v,,
From eq. (11), replacing Ap by Ape and B2 by B2e, we obtain the low threshold voltage of the m-inputs N A N D Schmitt circuit
t.
Vt
X!
=
Apnl/2(VDD + Vtp) + B2(mn)-l/2Vm 1 -t- Apn 1/2 + B2(mn) -1/2
X.--
rTT
.+v=,
(22)
T~ I-- Tin"
where Ap and B2 are given by eqs. (8) and (12), respectively.
-h i i
Fig. 6. Complete scheme of the m-input N A N D Schmitt circuit.
The threshold voltages Vt+ and V t depend on supply voltage VDD, the ratio of the constants fin~tip, tin/tinO, i.e. ti-/tipO, number of inputs m, and number of actfve inputs n. Besides, Vt+ depends on the position of the first active input k.
+V~
+V~
V.
i
+VDo
ttt
:
111
Jr.
VI =
T~
(a) Fig. 7. Equivalent circuit of m-input N A N D or N O R circuit (a) at
Co)
Vo =
VDD, and (b) at V0 = 0V.
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Branko L. Dokid/NAND and NOR circuits
Vm~=IOV
10
8 6
ii~ ii
i
ii
v, [Vl
X~; !:
4 iii X2 : [
3
4
.i
6
7 8
(a) 10
8 l~[mA] 46
ii
i ~] ~
ii
2
!
3 (b)
5
6
7 $
v, IV]
Fig. 8. Oscillograms of (a)voltage and (b) current transfercharacteristicof the two-input N A N D
3. 1.2 Measurements and computer simulation Measurements and computer simulation are made on a two-input N A N D Schmitt circuit. An experimental model was built using C M O S integrated circuits of type CD4007 (dual complementary pair plus inverter). Oscillograms of the voltage and current transfer characteristics of the two-input N A N D Schmitt circuit for various numbers and combinations of active inputs are shown in Fig. 8. Figure 8 confirms that V + depends and V t does not depend on the combination of active inputs. Namely, when first input X1 is active only ( n = l , k = l ) V + = 6.1V, and for the second input active only (n = 1, k = 2) V + = 6.7V. In both cases, V t = 3.8V. This was also confirmed by SPICE
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Schmitt circuit.
simulation (Fig. 9). Simulation was made at VDD ----5 V with parameters o f the 2 # m C M O S process. 3.2 NOR circuit
As the N O R circuit is obtained from the N A N D one through the interchange of the pchannel and n-channel transistors and a power supply polarity change, the previous analysis can be applied analogously to this circuit. In this way we obtain
V~+=
VDD + Vtp + BI(mn)I/2(VDD + Annl/ZVtn)
1 + Bl(mn)l/2(1 +Annl/2) (23)
Microelectronics Journal, Vol. 27, No. 8
- A p ( m - k + I'-I/2(VDD + Vtp) + B2[n(m - k + 1)]t/2 Vtn
Vt
1 +Ap(m
-
-
k + 1) -1/2 + B 2 [ n ( m - k + 1)] 1/2
Vt*, Vt- [V]
4'5l 4
a.5
............................................................................................................................................................................
}i-2 .....................................
............................................................................
2.5"2 ~
..............................
1,5~ I
0.2
I
l
l
I
I
i
i
0.7
1.2
1.7
2.2
2,7
3.2
3.7
AS. Fig. 9. SPICE values of Vt+ and V~ for two-input NAND circuit versus (W,,/L,,)/'(W,,o/L,,o) = (Wp/Lp)/(Wpo/Lpo) for various numbers and combinations of active inputs at VDr) = 5 V and for optimum geometry ratio of NMOS and PMOS transistors [6], that is at fin~tip = 2. Therefore, the threshold voltages depend on exactly the same parameters as the thresholds o f the N A N D circuit except that in the N O R circuit V~- depends on the position o f the first active input k. 4. Conclusion The basic circuit for N A N D and N O R Schmitt circuit design is the 5;chmitt trigger-inverter with six M O S transistors. Multiple inputs are realized by adding series and parallel pairs o f M O S transistors per input (one N M O S pair and one
(24)
P M O S pair). As with the conventional C M O S gates the N A N D Schmitt circuit is obtained w h e n pairs o f N M O S transistors are in series and P M O S are parallel, and for the N O R Schmitt circuit it is the opposite. The total number o f transistors o f an m-input circuit is 2(2m + 1). The voltage hysteresis depends on supply voltage Vrm, threshold voltage and geometry o f transistors, as well as on the number o f inputs and number o f active inputs and combinations o f active inputs. The hysteresis increases with increasing geometry o f the transistors Tn0 and Tp0 in the feedback loop relative to the geometry o f the other transistors. W h e n the W / L ratio o f the transistors Tn0 and Tp0 is less than W / L o f the other transistors the average propagation delay time almost does not depend on the Tn0 and Tp0 geometry. It is worth noting that the described circuits always guarantee hysteresis, even with very large process variations. References [1] B.L. Doki~, CMOS Schmitt triggers,lEE Proc., 131(5) (Oct. 1984) 197-202. [2] B.L. Doki8 and Z.V. Bundalo, Regenerative logic circuits with CMOS transistors, Int. J. Electron., 58(6) (1985) 907-920. [3] Zhenhua Wang, CMOS adjustable Schmitt triggers, IEEE Trans. Instrum., 40(3) (June 1991) 601-605. [4] Daejeong Kim, Joongsik and Wonchan Kim, A new waveform reshaping circuit: an alternative approach to Schmitt trigger, IEEEJ. Solid-State Circuits, 28(2) (Feb. 1993) 162-164. [5] J. Exalto, HCMOS Schmitt-trigger applications, Electron. Components Applications, 7(3) (1985) 144-151. [6] B.L. Doki~, Influence of series and parallel transistors on DC characteristicsof CMOS logic circuits, Micro° electronicsJ., 13(2) (March/April 1982) 25-30.
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