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Comparison on the effects of defects at Si(111) and Si(100) surface on electrical characteristics of MOS devices with HfOxNy gate dielectric
Microelectronic Engineering 80 (2005) 214–217 www.elsevier.com/locate/mee
Comparison on the effects of defects at Si(111) and Si(100) surface on electrical characteristics of MOS devices with HfOxNy gate dielectric Chin-Lung Cheng, Kuei-Shu Chang-Liao1, Tien-Ko Wang Department of Engineering and System Science, National Tsing Hua University, Hsinchu, Taiwan, R.O.C. 1 email: [email protected] Tel: 886-3-5742674
Abstract This work investigates and compares the effects of forming a denuded zone (DZ) at (111) and (100) Si surface on the electrical characteristic of MOS devices with HfOxNy high-k gate dielectric. Devices with DZ (low defect region) treatment at Si surface exhibit better electrical characteristics, such as reduced gate leakage current, defect generation rate, and interface trap density, as well as increased time to breakdown than those of without DZ treatment. This improvement can be attributed to the decrease of the defects at Si surface. In particular, by introducing DZ at the Si surface, the (111)-surface-oriented Si substrate has demonstrated more significant improvement on electrical properties than the (100) one. Keywords: defects; HfOxNy; interface; electrical; (111)-surface-oriented Si surface; (100)-surface-oriented Si surface
1. Introduction To solve the high-leakage-current problem of ultrathin gate oxide in metal-oxide semiconductor field-effect transistors (MOSFETs), dielectric materials with a high dielectric constant, a good thermal stability, and a low interface state density are required. In recent years, Hf-based gate dielectrics, which have high dielectric constants, good thermal stabilities, wide bandgaps and large band offsets, have received considerable attention [1]. However, it has been reported that high-k dielectric/silicon interfaces exist large amount of defect states which
result in poor electrical and reliability characteristics [2]. On the other hand, the nonplanar MOSFET devices, constructed on (111)-surface oriented substrates, are promising for very larger scale integrated applications [3]. Although it is known that the defects at the Si surface can be drastically reduced by denuded zone (DZ) formation [4], the comparison regarding the effects of DZ (low defect region), on the electric characteristics, at (111)- and (100)-surface-oriented substrate in MOS devices with HfOxNy high-k gate dielectric remains unclear. This work performs this comparison.
0167-9317/$ - see front matter Ó 2005 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2005.04.016
C.-L. Cheng et al. / Microelectronic Engineering 80 (2005) 214–217
2. Experiment
Firstly, the effects of high-temperature annealing (HTA) in H2 atmosphere on defects reduction were investigated. The amounts of defect characterized by SEM images are depicted in Fig. 1. The absorbance values at 1107 cm-1 analyzed by FTIR spectra are shown in Fig. 2. Both figures show fewer defects in DZ samples than in CN samples, demonstrating that the amount of the interstitial oxygen [Oi] and crystaloriginated particles (COP) defects in DZ samples are reduced through HTA in H2 ambient. Figure 3 shows that the MOS devices with DZ treatments have lower gate leakage current (Jg) and higher time-zero breakdown field (Ebd) as compared to those without DZ treatment. Moreover, the improvement for sample with (111) surface is more significsnt than that with (100) one. Figure 4 depicts that current densities remain constant at low temperature, while at higher
(b) CN100
(c) DZ111
(d) CN111
O
1.5 Absorbance
Si
Si
1.2
DZ111 CN111
0.9 0.6
1107 cm
DZ100 CN100
-1
0.3 1080 1100 1120 1140 -1 Wavenumber (cm )
Fig. 2 Fourier-transform infrared spectroscopy (FTIR) spectra of (111) and (100)-surface-oriented silicon substrate for DZ and CN at wave numbers ranging from 1080 to 1140 cm-1. DZ100 CN100 DZ111 95 CN111 CET~1.6 nm
(a)
99.5
70 40 10
1 'J =-67.4% 'J =-77.2 % g g 0.1 -6 -5 -4 -3 -2 10 10 2 10 10 10 Jg (A/cm ) at (Vg-Vfb)=-1.0 V
99.5 Cumulative Probability (%)
3. Results and discussion
(a) DZ100
Fig.1 Scanning electron microscope (SEM) images of silicon surface for the (a) DZ100, (b) CN100 , (c) DZ111, and (d) CN111 samples.
Cumulative Probability (%)
MOS capacitors with TaN/HfOxNy/Si structure were fabricated. To investigate the effects of the defects near the HfOxNy/Si interface, the wet cleaned (111)- and (100)-surface-oriented Si wafers were treated by furnace annealing at 1200 к in 100% H2 gas for 60 min (denoted as DZ samples: DZ111 and DZ100). The wet cleaning process used an NH4OH:H2O2:H2O mixture (APM) in a ratio of 1 : 4 : 20 (volume) at 75 °C and a HCl:H2O2:H2O mixture (HPM) in a ratio of 1 : 1 : 6 (volume) at 75 °C. Diluted HF (DHF) with HF and H2O in a ratio of 1 : 100 (volume) was used to remove native oxide. The cleaned untreated wafers were used as references (denoted as CN samples: CN111 and CN100). Next, a hafnium nitride (HfxNy, ~2 nm) film were deposited by reactive dc magnetron sputtering of a 99.9% pure Hf target in an Ar/N2 = 24/36 sccm ambient, at a power density of 4.7 W/cm2 and a pressure of 7.6 mTorr. Then, a rapid thermal annealing carried out at 850 oC in N2 gas for 60 s with a trace amount of residual oxygen in both chamber and native oxide of Si surface was performed to form HfOxNy (~4.5 nm). Later, the TaN- and Al-film were deposited as the gate electrode and back surface of wafer, respectively. Finally, a sintering was conducted in a N2/H2 ambient at 420 к for 30 min.
215
95
DZ100 CN100 DZ111 CN111
(b)
70 40 10 'Ebd=+26.8% 1 'E =+16.1% 0.1 bd 2 4 6 8 10 12 Ebd (MV/cm)
Fig. 3 Cumulative probability of (a) gate leakage current density Jg at (Vg-Vfb)=-1.0 V (b) time-zero breakdown field (Ebd) for TaN/HfOxNy/Si(111) and TaN/HfOxNy/Si(100) capacitors, tHfON: physical thickness of HfOxNy, 'Jg=[(DZCN)/CN] x 100%, Ebd=Vbd/tHfON.
C.-L. Cheng et al. / Microelectronic Engineering 80 (2005) 214–217
temperatures the current densities increase with increasing temperature. Based on Frenkel-Pool (FP) current equation, the FP emission current is correlated with temperature or activation energy. The figure suggests that field emission occurs at low temperature, while FP conduction mechanism occurs at high temperature. -1
1
3
10
-3
10
-5
1x10
-7
10
10
1
10
-1
10
-3
DZ100: -0.5 V DZ100: -1.0 V DZ100: -1.5 V CN100: -0.5 V CN100: -1.0 V CN100: -1.5 V
1
2
DZ111: -0.5 V DZ111: -1.0 V DZ111: -1.5 V CN111: -0.5 V CN111: -1.0 V CN111: -1.5 V
3 4 -1 5 1000/T (K )
6
10
-5
1x10 -7
10
Fig. 4 Plots of gate leakage current density (Jg) as a function of 1000/T ranging from 2.11 to 3.35 K-1 for (111)and (100)-surface-oriented Si substrate.
The straight-line fitting of [ln(Jg/Eeff)] in Fig. 5 suggests a FP emission mechanism at hightemperature and high electrical fields. From the data analysis involved in FP conduction in Fig. 4 and 5 (in the temperature 1000/T ranging from 2.11 to 2.51 K-1 and the electrical field at –0.52 MV/cm), the energy level of traps (ĭB) for samples with DZ treatment are found to be lower than those of without DZ ones. 1/2
ln (Jg/E)
-2 -3
-2 -1
-3
at 1000/T=2.36 K 0.66
0.69 0.72 0.75 1/2 1/2 (E) (MV/cm)
ln (Jg/E)
1/2
(E) (MV/cm) 0.57 0.60 0.63 0.66 0.69 1 0 DZ111 DZ100 CN111 CN100 0 -1 -1 Frenkel-Pool Current
4
2
DZ111 IB=0.50 eV CN111 IB=0.53 eV
TaN/HfOxNy/Si
-4 -5 0.78
Fig. 5 ln(Jg/E) versus (E)1/2 properties of capacitors for (111)- and (100)-surface-oriented Si substrate at 1000/T=2.36 K-1, E=(Vg-Vfb)/tHfON.
(Jg-J0)/J0at E=0.78 MV/cm
2
Jg (A/cm )
6
DZ100 1 I =0.50 eV 10 BCN100 -1 IB=0.52 eV
Jg (A/cm )
3
10
1000/T (K ) 5 4 3 2
To examine the degradation of reliability induced by the defects near the HfOxNy/Si interface, the stress-induced leakage current (SILC) [(Jg-J0)/J0] at electrical field E=-5.11 MV/cm as a function of injected charge is shown in Fig. 6. The results indicate that the lower defect amount for DZ sample results in a lower defect generation rate (Pg). By applying DZ treatment, more noticeable SILC reduction is observed for the (111) sample as compared with the (100) one. 10 Stress at E=-5.11 MV/cm 3 10 'Pg=-0.96 for (111) =-0.95 for (100)
2
10
2
1
10
Pg=0.85 cm /C: CN111 2
Pg=0.24 cm /C: CN100
0
10
-1
2
10
Pg=0.01 cm /C: DZ100 2
=0.03 cm /C: DZ111
-2
10
DZ111 CN111 DZ100 CN100
0
10
1
2
10 10 2 Qinj (C/cm )
3
10
Fig. 6 SILC [(Jg-J0)/J0] as a function of injected charge for (111)- and (100)-surface-oriented Si substrate. The defect generation rate (Pg) is extracted from the linear portion of the relationship between (Jg-J0)/J0 and Qinj, 'Pg=[(Pg of DZ)-(Pg of CN)]/(Pg of CN).
140 Stress at E= -3.56 MV/cm 120 DZ100 CN100 100 DZ111 80 CN111 60 40 20 0 -2 -1 0 1 2 10 10 10 102 10 Qinj (C/cm )
' Vfb (mV)
216
3
10
Fig.7 The charge trapping induced flatband voltage (Vfb) shift of capacitor for (111)- and (100)-surface-oriented Si substrate as a function of gate injection (Qinj) under constant voltage stress, 'Vfb=Vfb-Vfb0.
To further study the charge trapping properties, high-frequency (100 kHz) C-V curves of MOS devices following various stress times were analyzed as shown in Fig. 7. After stress, smaller flatband voltage shifts (ǻVfb) were observed in the DZ sample
C.-L. Cheng et al. / Microelectronic Engineering 80 (2005) 214–217
than in the CN sample due to its less charge trapping at HfOxNy/Si interface. Again, by using DZ treatment, the ǻVfb reduction for the (111) sample is more significant than that for the (100) one. The interface trap density (Dit) of MOS capacitors can be extracted from measured conductances as a function of frequency by biasing the Si surface in its depletion condition. Figure 8 reveals that the Dit for the DZ sample is lower than the CN one. -5
-6
10
-7
10
'Dit= -20 %
-8
10
-9
10
11
-2
-1
11
-2
-1
Dit=4.66 x 10 cm e V : CN100 2
4
10
10 -1 Z (s )
10 10
-7
10
-8
10
6
10
-5
-6
Dit=3.73 x 10 cm e V : DZ100
-10
10
10 -2
Dit=(2.5/qA)x(Gp/Z)max(a) DZ100 CN100
Gp/ZA (Sxsxcm )
-2
Gp/ZA (Sxsxcm )
10
Dit=(2.5/qA)x(Gp/Z)max(b) DZ111 CN111 'Dit= -35 %
12
-2
-1
11
-2
-1
Dit=1.03 x 10 cm e V : CN111 -9
Dit=6.67 x 10 cm e V : DZ111
10
2
10
4 -1
Z (s )
10
6
Fig. 8 The conductance is measured as a function of frequency and plotted as Gp/ZA versus Z by biasing the Si surface in depletion condition. Interface trap density (Dit) of MOS capacitors is extracted from conductance method for (a) (100)- and (b) (111)-surface-oriented Si substrate, 'Dit=(DZ-CN)/CN, area=1x10-4 cm2. 6
Time to Breakdown Tbd ( S )
10 Stress at 5 10 E=-5.33 MV/cm 10
3 2
10
1
-4
10 2 Area (cm )
4. Conclusions Better electrical properties for samples with denuded zone treatment, including reduced defect generation rate and interface trap density as well as increased time to breakdown, can be achieved by reduction of the [Oi] and the COP defects at the HfOxNy/Si interfaces. In particular, by introducing a denuded zone at the Si surface, the (111) Si substrate has demonstrated more significant improvement on electrical properties as compared to the (100) one.
The authors would like to thank the National Science Council of the Republic of China, for financially supporting this research under Contract No. NSC 93-2215E-007-014. The technical support from National Nano Device Laboratories of the R.O.C. is also acknowledged.
10
10 -5 10
layer applied at a high electric field, which causes immediate breakdown of dielectric bulk after interface degradation. As shown in Figs. 3 to 9, the improvement on electrical properties including Jg, Ebd, Pg, ǻVfb, Tbd, and Dit by forming a DZ at the Si surface is more remarkable in (111)-surface-oriented Si substrates than in (100) ones. The better improvement for the (111) sample can be attributed to the highe amount of dangling bonds minimized by the reaction with H atoms at the HfOxNy/Si(111) interface. This indicates that high-temperature annealing in hydrogen atmosphere is a promising process for the fabrication of MOS devices with (111)-surface-oriented Si substrate and high-k gate dielectric.
Acknowledgements
DZ100 CN100 DZ111 CN111
4
217
-3
10
Fig. 9 Time to breakdown (Tbd) of capacitors with various gate areas subjected to constant voltage stress for (111)and (100)-surface-oriented Si substrate.
The relatively lower Tbd for the CN sample shown in Fig. 9 can be caused by its large amount of defects at the HfOxNy/Si interface which result in a weakly localized percolation path between the gate electrode and the substrate. Therefore, the breakdown of the dielectric bulk is mostly dominated by the interfacial
References [1] G. D. Wilk, R. M. Wallace, and J. M. Anthony, J. Appl. Phys. Vo. 89 (2001) 5243-5275. [2] S. Mudanai, F. Li, S. B. Samavedam, P. J. Tobin, C. S. Kang, R. Nieh, J. C. Lee, L. F. Register, and S. K. Banerjee, IEEE Electron Device Lett., Vol. 23 (2002) 728-730. [3] J. H. Lee, J. P. Kim, J. H. Lee, Y. Kim, H. Jung, N. Lee, H. Kang, K. Suh, M. Jeong, K. Hyun, H. Baik, Y. S. Chung, X. Liu, S. Ramanathan, T. Seidel, J. Winkler, A. Londergan, H. Y. Kim, J. M. Ha, and N. K. Lee, in IEDM Tech. Dig. (2002) 221-224. [4] D. Graf, U. Lambert, M. Brohl, A. Ehlert, R. Wahlich, and P. Wagner, Mater. Sci. Engineering B, Vol. 36 (1996) 50-54.
Comparison on the effects of defects at Si(111) and Si(100) surface on electrical characteristics of MOS devices with HfOxNy gate dielectric Chin-Lung Cheng, Kuei-Shu Chang-Liao1, Tien-Ko Wang Department of Engineering and System Science, National Tsing Hua University, Hsinchu, Taiwan, R.O.C. 1 email: [email protected] Tel: 886-3-5742674
Abstract This work investigates and compares the effects of forming a denuded zone (DZ) at (111) and (100) Si surface on the electrical characteristic of MOS devices with HfOxNy high-k gate dielectric. Devices with DZ (low defect region) treatment at Si surface exhibit better electrical characteristics, such as reduced gate leakage current, defect generation rate, and interface trap density, as well as increased time to breakdown than those of without DZ treatment. This improvement can be attributed to the decrease of the defects at Si surface. In particular, by introducing DZ at the Si surface, the (111)-surface-oriented Si substrate has demonstrated more significant improvement on electrical properties than the (100) one. Keywords: defects; HfOxNy; interface; electrical; (111)-surface-oriented Si surface; (100)-surface-oriented Si surface
1. Introduction To solve the high-leakage-current problem of ultrathin gate oxide in metal-oxide semiconductor field-effect transistors (MOSFETs), dielectric materials with a high dielectric constant, a good thermal stability, and a low interface state density are required. In recent years, Hf-based gate dielectrics, which have high dielectric constants, good thermal stabilities, wide bandgaps and large band offsets, have received considerable attention [1]. However, it has been reported that high-k dielectric/silicon interfaces exist large amount of defect states which
result in poor electrical and reliability characteristics [2]. On the other hand, the nonplanar MOSFET devices, constructed on (111)-surface oriented substrates, are promising for very larger scale integrated applications [3]. Although it is known that the defects at the Si surface can be drastically reduced by denuded zone (DZ) formation [4], the comparison regarding the effects of DZ (low defect region), on the electric characteristics, at (111)- and (100)-surface-oriented substrate in MOS devices with HfOxNy high-k gate dielectric remains unclear. This work performs this comparison.
0167-9317/$ - see front matter Ó 2005 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2005.04.016
C.-L. Cheng et al. / Microelectronic Engineering 80 (2005) 214–217
2. Experiment
Firstly, the effects of high-temperature annealing (HTA) in H2 atmosphere on defects reduction were investigated. The amounts of defect characterized by SEM images are depicted in Fig. 1. The absorbance values at 1107 cm-1 analyzed by FTIR spectra are shown in Fig. 2. Both figures show fewer defects in DZ samples than in CN samples, demonstrating that the amount of the interstitial oxygen [Oi] and crystaloriginated particles (COP) defects in DZ samples are reduced through HTA in H2 ambient. Figure 3 shows that the MOS devices with DZ treatments have lower gate leakage current (Jg) and higher time-zero breakdown field (Ebd) as compared to those without DZ treatment. Moreover, the improvement for sample with (111) surface is more significsnt than that with (100) one. Figure 4 depicts that current densities remain constant at low temperature, while at higher
(b) CN100
(c) DZ111
(d) CN111
O
1.5 Absorbance
Si
Si
1.2
DZ111 CN111
0.9 0.6
1107 cm
DZ100 CN100
-1
0.3 1080 1100 1120 1140 -1 Wavenumber (cm )
Fig. 2 Fourier-transform infrared spectroscopy (FTIR) spectra of (111) and (100)-surface-oriented silicon substrate for DZ and CN at wave numbers ranging from 1080 to 1140 cm-1. DZ100 CN100 DZ111 95 CN111 CET~1.6 nm
(a)
99.5
70 40 10
1 'J =-67.4% 'J =-77.2 % g g 0.1 -6 -5 -4 -3 -2 10 10 2 10 10 10 Jg (A/cm ) at (Vg-Vfb)=-1.0 V
99.5 Cumulative Probability (%)
3. Results and discussion
(a) DZ100
Fig.1 Scanning electron microscope (SEM) images of silicon surface for the (a) DZ100, (b) CN100 , (c) DZ111, and (d) CN111 samples.
Cumulative Probability (%)
MOS capacitors with TaN/HfOxNy/Si structure were fabricated. To investigate the effects of the defects near the HfOxNy/Si interface, the wet cleaned (111)- and (100)-surface-oriented Si wafers were treated by furnace annealing at 1200 к in 100% H2 gas for 60 min (denoted as DZ samples: DZ111 and DZ100). The wet cleaning process used an NH4OH:H2O2:H2O mixture (APM) in a ratio of 1 : 4 : 20 (volume) at 75 °C and a HCl:H2O2:H2O mixture (HPM) in a ratio of 1 : 1 : 6 (volume) at 75 °C. Diluted HF (DHF) with HF and H2O in a ratio of 1 : 100 (volume) was used to remove native oxide. The cleaned untreated wafers were used as references (denoted as CN samples: CN111 and CN100). Next, a hafnium nitride (HfxNy, ~2 nm) film were deposited by reactive dc magnetron sputtering of a 99.9% pure Hf target in an Ar/N2 = 24/36 sccm ambient, at a power density of 4.7 W/cm2 and a pressure of 7.6 mTorr. Then, a rapid thermal annealing carried out at 850 oC in N2 gas for 60 s with a trace amount of residual oxygen in both chamber and native oxide of Si surface was performed to form HfOxNy (~4.5 nm). Later, the TaN- and Al-film were deposited as the gate electrode and back surface of wafer, respectively. Finally, a sintering was conducted in a N2/H2 ambient at 420 к for 30 min.
215
95
DZ100 CN100 DZ111 CN111
(b)
70 40 10 'Ebd=+26.8% 1 'E =+16.1% 0.1 bd 2 4 6 8 10 12 Ebd (MV/cm)
Fig. 3 Cumulative probability of (a) gate leakage current density Jg at (Vg-Vfb)=-1.0 V (b) time-zero breakdown field (Ebd) for TaN/HfOxNy/Si(111) and TaN/HfOxNy/Si(100) capacitors, tHfON: physical thickness of HfOxNy, 'Jg=[(DZCN)/CN] x 100%, Ebd=Vbd/tHfON.
C.-L. Cheng et al. / Microelectronic Engineering 80 (2005) 214–217
temperatures the current densities increase with increasing temperature. Based on Frenkel-Pool (FP) current equation, the FP emission current is correlated with temperature or activation energy. The figure suggests that field emission occurs at low temperature, while FP conduction mechanism occurs at high temperature. -1
1
3
10
-3
10
-5
1x10
-7
10
10
1
10
-1
10
-3
DZ100: -0.5 V DZ100: -1.0 V DZ100: -1.5 V CN100: -0.5 V CN100: -1.0 V CN100: -1.5 V
1
2
DZ111: -0.5 V DZ111: -1.0 V DZ111: -1.5 V CN111: -0.5 V CN111: -1.0 V CN111: -1.5 V
3 4 -1 5 1000/T (K )
6
10
-5
1x10 -7
10
Fig. 4 Plots of gate leakage current density (Jg) as a function of 1000/T ranging from 2.11 to 3.35 K-1 for (111)and (100)-surface-oriented Si substrate.
The straight-line fitting of [ln(Jg/Eeff)] in Fig. 5 suggests a FP emission mechanism at hightemperature and high electrical fields. From the data analysis involved in FP conduction in Fig. 4 and 5 (in the temperature 1000/T ranging from 2.11 to 2.51 K-1 and the electrical field at –0.52 MV/cm), the energy level of traps (ĭB) for samples with DZ treatment are found to be lower than those of without DZ ones. 1/2
ln (Jg/E)
-2 -3
-2 -1
-3
at 1000/T=2.36 K 0.66
0.69 0.72 0.75 1/2 1/2 (E) (MV/cm)
ln (Jg/E)
1/2
(E) (MV/cm) 0.57 0.60 0.63 0.66 0.69 1 0 DZ111 DZ100 CN111 CN100 0 -1 -1 Frenkel-Pool Current
4
2
DZ111 IB=0.50 eV CN111 IB=0.53 eV
TaN/HfOxNy/Si
-4 -5 0.78
Fig. 5 ln(Jg/E) versus (E)1/2 properties of capacitors for (111)- and (100)-surface-oriented Si substrate at 1000/T=2.36 K-1, E=(Vg-Vfb)/tHfON.
(Jg-J0)/J0at E=0.78 MV/cm
2
Jg (A/cm )
6
DZ100 1 I =0.50 eV 10 BCN100 -1 IB=0.52 eV
Jg (A/cm )
3
10
1000/T (K ) 5 4 3 2
To examine the degradation of reliability induced by the defects near the HfOxNy/Si interface, the stress-induced leakage current (SILC) [(Jg-J0)/J0] at electrical field E=-5.11 MV/cm as a function of injected charge is shown in Fig. 6. The results indicate that the lower defect amount for DZ sample results in a lower defect generation rate (Pg). By applying DZ treatment, more noticeable SILC reduction is observed for the (111) sample as compared with the (100) one. 10 Stress at E=-5.11 MV/cm 3 10 'Pg=-0.96 for (111) =-0.95 for (100)
2
10
2
1
10
Pg=0.85 cm /C: CN111 2
Pg=0.24 cm /C: CN100
0
10
-1
2
10
Pg=0.01 cm /C: DZ100 2
=0.03 cm /C: DZ111
-2
10
DZ111 CN111 DZ100 CN100
0
10
1
2
10 10 2 Qinj (C/cm )
3
10
Fig. 6 SILC [(Jg-J0)/J0] as a function of injected charge for (111)- and (100)-surface-oriented Si substrate. The defect generation rate (Pg) is extracted from the linear portion of the relationship between (Jg-J0)/J0 and Qinj, 'Pg=[(Pg of DZ)-(Pg of CN)]/(Pg of CN).
140 Stress at E= -3.56 MV/cm 120 DZ100 CN100 100 DZ111 80 CN111 60 40 20 0 -2 -1 0 1 2 10 10 10 102 10 Qinj (C/cm )
' Vfb (mV)
216
3
10
Fig.7 The charge trapping induced flatband voltage (Vfb) shift of capacitor for (111)- and (100)-surface-oriented Si substrate as a function of gate injection (Qinj) under constant voltage stress, 'Vfb=Vfb-Vfb0.
To further study the charge trapping properties, high-frequency (100 kHz) C-V curves of MOS devices following various stress times were analyzed as shown in Fig. 7. After stress, smaller flatband voltage shifts (ǻVfb) were observed in the DZ sample
C.-L. Cheng et al. / Microelectronic Engineering 80 (2005) 214–217
than in the CN sample due to its less charge trapping at HfOxNy/Si interface. Again, by using DZ treatment, the ǻVfb reduction for the (111) sample is more significant than that for the (100) one. The interface trap density (Dit) of MOS capacitors can be extracted from measured conductances as a function of frequency by biasing the Si surface in its depletion condition. Figure 8 reveals that the Dit for the DZ sample is lower than the CN one. -5
-6
10
-7
10
'Dit= -20 %
-8
10
-9
10
11
-2
-1
11
-2
-1
Dit=4.66 x 10 cm e V : CN100 2
4
10
10 -1 Z (s )
10 10
-7
10
-8
10
6
10
-5
-6
Dit=3.73 x 10 cm e V : DZ100
-10
10
10 -2
Dit=(2.5/qA)x(Gp/Z)max(a) DZ100 CN100
Gp/ZA (Sxsxcm )
-2
Gp/ZA (Sxsxcm )
10
Dit=(2.5/qA)x(Gp/Z)max(b) DZ111 CN111 'Dit= -35 %
12
-2
-1
11
-2
-1
Dit=1.03 x 10 cm e V : CN111 -9
Dit=6.67 x 10 cm e V : DZ111
10
2
10
4 -1
Z (s )
10
6
Fig. 8 The conductance is measured as a function of frequency and plotted as Gp/ZA versus Z by biasing the Si surface in depletion condition. Interface trap density (Dit) of MOS capacitors is extracted from conductance method for (a) (100)- and (b) (111)-surface-oriented Si substrate, 'Dit=(DZ-CN)/CN, area=1x10-4 cm2. 6
Time to Breakdown Tbd ( S )
10 Stress at 5 10 E=-5.33 MV/cm 10
3 2
10
1
-4
10 2 Area (cm )
4. Conclusions Better electrical properties for samples with denuded zone treatment, including reduced defect generation rate and interface trap density as well as increased time to breakdown, can be achieved by reduction of the [Oi] and the COP defects at the HfOxNy/Si interfaces. In particular, by introducing a denuded zone at the Si surface, the (111) Si substrate has demonstrated more significant improvement on electrical properties as compared to the (100) one.
The authors would like to thank the National Science Council of the Republic of China, for financially supporting this research under Contract No. NSC 93-2215E-007-014. The technical support from National Nano Device Laboratories of the R.O.C. is also acknowledged.
10
10 -5 10
layer applied at a high electric field, which causes immediate breakdown of dielectric bulk after interface degradation. As shown in Figs. 3 to 9, the improvement on electrical properties including Jg, Ebd, Pg, ǻVfb, Tbd, and Dit by forming a DZ at the Si surface is more remarkable in (111)-surface-oriented Si substrates than in (100) ones. The better improvement for the (111) sample can be attributed to the highe amount of dangling bonds minimized by the reaction with H atoms at the HfOxNy/Si(111) interface. This indicates that high-temperature annealing in hydrogen atmosphere is a promising process for the fabrication of MOS devices with (111)-surface-oriented Si substrate and high-k gate dielectric.
Acknowledgements
DZ100 CN100 DZ111 CN111
4
217
-3
10
Fig. 9 Time to breakdown (Tbd) of capacitors with various gate areas subjected to constant voltage stress for (111)and (100)-surface-oriented Si substrate.
The relatively lower Tbd for the CN sample shown in Fig. 9 can be caused by its large amount of defects at the HfOxNy/Si interface which result in a weakly localized percolation path between the gate electrode and the substrate. Therefore, the breakdown of the dielectric bulk is mostly dominated by the interfacial
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