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Electrical characteristics of Ge MOS device on Si substrate with thermal SiON as gate dielectric
Microelectronic Engineering 87 (2010) 2423–2428
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Electrical characteristics of Ge MOS device on Si substrate with thermal SiON as gate dielectric Yung-Hsien Wu *, Min-Lin Wu, Jia-Rong Wu, Yuan-Sheng Lin Department of Engineering and System Science, National Tsing-Hua University, 300 Hsinchu, Taiwan
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Article history: Received 1 April 2009 Received in revised form 31 March 2010 Accepted 20 April 2010 Available online 28 April 2010 Keywords: Ge MOS devices Thermal SiON Gate dielectric Interface trap density Conduction mechanism
a b s t r a c t Metal–oxide-semiconductor (MOS) devices, using a Si substrate and a thermal SiON film as the gate dielectric on a Ge layer, have been physically and electrically characterized. The small frequency dispersion and negligible hysteresis demonstrate very few oxide traps. The efficiency of Ge surface passivation is evidenced by the acceptable interface trap density of 7.08 1011 cm 2 eV 1 close to midgap, which is critical for the enhancement of the carrier mobility in MOSFET devices. On the other hand, for the thermal SiON film, a higher permittivity of 4.86 can be achieved by NH3 nitridation and a subsequent N2O treatment of an as-grown SiO2 film without compromising its leakage current. The conduction mechanism is confirmed to be Fowler–Nordheim (F–N) tunneling with extracted electron barrier height of 2.71 eV. Combining with these promising properties, the SiON film shows a great potential to further boost the performance of Ge MOSFETs. Most importantly, without using a Ge substrate, the SiON film on a Ge layer can be formed by the process fully compatible with incumbent ultra-large-scale integration (ULSI) technology, and hence, providing an economic way of fabricating high-performance Ge MOSFETs. Ó 2010 Elsevier B.V. All rights reserved.
1. Introduction Despite great advancement in high permittivity (high-j) gate dielectrics, metal gates and strain engineering, the effort to pursue devices with higher performance never slows down. Due to the superior carrier mobility against Si, germanium (Ge) has received much attention and been regarded as a potential channel material to accommodate the ever-stringent scaling requirement for future technology nodes. One of the major challenges in achieving high-performance Ge MOS devices is to maintain a good interface property between gate dielectric and Ge channel. In spite of the water-soluble property, a thermally grown GeO2 film has shown to possess good passivation for a Ge substrate [1]. However, extreme care should be exercised to prevent the formation of volatile GeO by the reaction between GeO2 and Ge substrate at temperature higher than 400 °C since this reaction would leave a huge amount of interface defects and traps [2,3], and causes the degradation of the electrical properties [4]. To effectively restrict the desorption of a GeO2 film at higher processing temperature, many research groups have explored the possibility of incorporating nitrogen or other elements into GeO2 to form GeON [5–10], GeZrO [11], GeZrSiO [12], or GeOS [13], which were reported to have good electrical characteristics. On the other hand, many non-GeOx based passivation methods such as surface SiH4 [14] or PH3 treatment * Corresponding author. Tel.: +886 3 5162248; fax: +886 3 5720724. E-mail address: [email protected] (Y.-H. Wu). 0167-9317/$ - see front matter Ó 2010 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2010.04.018
[15], and AlN [15,16] or Hf3N4 [17] deposition have been proposed to enhance interfacial quality. Using a Si cap with SiO2 film for Ge surface passivation is another way to realize good interfacial characteristics [18,19]. However, it requires rigorous control of the Si cap thickness to maintain desirable device performance [20]. In this work, without a Si cap, a thermal SiON film directly grown on a Ge layer was evaluated. In comparison with our previous work [21], aside from reducing the effective oxide thickness by means of thinning down the physical oxide thickness and enhancing the nitridation, this work also focuses on the analysis of interfacial property and conducting mechanism of the SiON film. Based on the negligible hysteresis, excellent frequency dispersion and interface trap density of 7.08 1011 cm 2eV 1 obtained from the SiON film; it shows the capability to be employed as a promising passivation method for Ge MOSFETs fabrication. Most importantly, the thermal SiON film on a Ge layer can be implemented on a Si substrate, which is not only less expensive but also compatible with existent ULSI technology.
2. Experiment After ex-situ HF vapor treatment to maintain a native-oxidefree surface of active areas on a (1 0 0)-oriented p-type Si substrate, an epitaxial Si0.3Ge0.7 layer was selectively formed in the active areas by amorphous Ge deposition and a subsequent thermal annealing [22]. Thereafter, a single crystalline Ge layer can be
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formed through oxidation of the Si0.3Ge0.7 layer at 900 °C followed by a forming gas annealing at 700 °C. Then, a thermal SiO2 film with 14.6 nm was concurrently grown on a 12-nm-thick Ge layer and served as the gate dielectric of Ge MOS capacitors. Detailed process conditions and mechanisms on implementing this film structure can be found in our previous work [21]. To further enhance permittivity of the SiO2 film, additional thermal nitridation in NH3 ambient and a subsequent N2O treatment was performed at 850 °C to form a desirable nitrided oxide [23]. The physical thickness of the nitrided oxide and as-grown SiO2 film was nearly the same after characterization by ellipsometer and TEM (Transmission Electron Microscopy). Finally, aluminum was evaporated and patterned as the gate electrode. X-ray photoelectron spectroscopy (XPS) analysis was performed to investigate bond structure of the oxide film. In order to mitigate the surface charging effect on the insulating film, a charge neutralizer (low-energy electron gun) was employed for charge compensation in the XPS measurement [24,25]. A sequence of Ar+ ion sputtering cycles (sputtering rate of 2.1 nm/min) interleaved with XPS measurement was utilized to obtain bond structure near the oxide surface and interface. Atomic force microscopy (AFM) was used to characterize the surface roughness of the Ge film. The eligibility for passivation was electrically evaluated by frequency dispersion, interface trap density (Dit) characteristics and gate leakage measurement. Note that to extract the interface trap density, Ge n-MOSFETs were also fabricated with the source/drain formed by phosphorous implantation and activation annealing at 600 °C for full conductance measurement [26]. 3. Results and discussion Fig. 1 manifests the cross-sectional TEM image for the sample with nitrided oxide. Besides confirming the physical thickness of 14.6 nm, smooth interface between the nitrided oxide and single crystalline Ge layer can be also observed which is beneficial for maintaining low interface traps and achieving high carrier mobility for MOS devices. Fig. 2 shows the Si 2p and Ge 3d spectra for the nitrided oxide from the XPS measurement. By comparing with the Si 2p spectrum of the thermal SiO2 film which has a signal at 103.6 eV, the strong Si 2p signal for the nitrided oxide at lower binding energy of 102.9 eV indicates that a large amount of nitrogen was incorporated in the oxide bulk rather than the interface to
Fig. 1. Cross-sectional TEM image for the sample with nitrided oxide.
Fig. 2. XPS Si 2p spectrum for the nitrided oxide. The inset shows Ge 3d spectra for the nitrided oxide.
form a silicon oxynitride (SiON) film. This is similar to the results published in the literature [27]. On the other hand, the weak and broad Ge 3d signal at 33 eV near the oxide interface together with the nearly flat signal close to the oxide surface prove that the amount of GeO content in the nitrided oxide is negligible. In contrast to the signal near the oxide surface, the stronger signal at 33 eV near the interface can be ascribed to the fact that Ge atoms are largely repelled to the oxide interface during Si0.3Ge0.7 oxidation, and that GeO content in the oxide can be continually decreased during the reduction process through the forming gas annealing [21,28]. This result is consistent with the SIMS analysis in our previous work [21] and confirms that a thermal gate dielectric mainly composed of SiON can be directly formed on a Ge layer, which would have greater capability to improve the electrical characteristics as compared to the commonly used GeOx-based dielectrics. Frequency dispersion of capacitance–voltage (C–V) characteristics is essential to assess the interfacial quality of a dielectric. The C–V frequency dispersion measured between 1 MHz and 1 kHz at 300 K for the capacitor with SiON film is shown in Fig. 3, and it displays less than 196 mV frequency dispersion in the depletion regime and no kinks near the inversion regime. It is worth noting that for many researches regarding the C–V characteristics of Ge MOS capacitors, inversion can be usually
Fig. 3. Capacitance–voltage frequency dispersion characteristics for the capacitor with SiON film. The inset is the comparison of hysteresis measured by ±5 V sweep at different frequencies for the capacitor with SiON film.
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observed at low measurement frequency (0.1–10 kHz) [6,26,29], which is quite different from that in this work. The formation of inversion layer can be attributed to the much shorter minority carrier response time and higher minority carrier generation–recombination rate for smaller-bandgap Ge as relative to Si counterpart [29]. The high defect density in a low quality Ge material is also known to facilitate the minority carrier generation–recombination rate. To better understand this phenomenon, it is worth noting the two possible mechanisms for minority carrier generation. One of which is that minority carriers are generated in the Ge bulk and then diffuse to the Ge/dielectric interface, while the other mechanism involves minority carrier generation in the depletion layer through bulk and interface traps. For the Ge device used in this work (12 nm Ge layer on Si substrate), the bulk material is primarily made of Si substrate, which lowers the possibility of minority carrier generation by the former mechanism. On the other hand, the good Ge crystallinity with limited bulk and interface traps of this device would suppress the minority carrier generation via the latter mechanism. These inferences may explain the C–V characteristics shown in Fig. 3. In fact, similar C–V characteristics for Ge MOS capacitors have been reported in Ref. [30,31], which attributes this phenomenon to the desirable interfacial property. The frequency-independent capacitance in the accumulation regime indicates that it is proper to extract the intrinsic oxide capacitance without including the series resistance effect [32]. The excellent hysteresis performance is also obtained at different frequencies ranging from 1 kHz to 1 MHz as evidenced in the inset of Fig. 3. Presented in Fig. 4 is the bi-directional C–V hysteresis characteristics for the capacitors with SiON and as-grown SiO2 film measured at 1 kHz with ±5 V voltage sweep. The negligible hysteresis for the SiON film suggests that the electron traps introduced during NH3 nitridation can be effectively alleviated by N2O treatment, which is very important for gate dielectric reliability. The extracted permittivity of the as-grown SiO2 film is about 3.92. This value is much different from that of a GeO2 film (j7) [33,34] and close to the conventional thermal SiO2 film (j3.9) on Si, which implies the negligible Ge content in the oxide and is consistent with the XPS results shown in Fig. 2. The higher capacitance in the accumulation regime for the nitrided oxide is ascribed to the incorporation of a large amount of nitrogen. The effective oxide thickness of the SiON film is extracted to be 11.7 nm with a permittivity of 4.86, which is nearly a 23.9% enhancement as compared with the asgrown SiO2 film. The relatively larger permittivity enhancement as compared to our previous work is due to the longer NH3 nitridation time, and the nitrogen concentration is about 11.8 at.% by XPS analysis. For Ge MOSFETs, a good interface trap density has been regarded as the effective means to improve the inferior
mobility enhancement in n-MOSFET over its p-MOSFET counterpart as compared with Si control sample [5,6]. Because of the low bandgap of Ge, the weak inversion response and strong inversion response due to minority carrier would dominate the conductance at 300 K and therefore makes the conventional conductance method, which assumes depletion, no longer correct for extracting the Dit value of Ge MOS capacitors [26]. To circumvent this issue, full conductance method is used to extract Dit in which a MOSFET or a gated diode with the bulk and source/drain shortened is employed for conductance measurement [26]. Fig. 5 displays the full conductance measurement for the n-MOSFET with SiON film as the gate dielectric at 300 K. Note that Gp is the parallel equivalent conductance after subtracting the reactance associated with Cox while x is the angular frequency. It is worth mentioning that this full conductance measurement was conducted at 300 K and the energy range at which the Fermi level could move (ET–EV) for the applied gate voltages (0.05–0.30 V) is about 0.24–0.34 eV, where it is near the midgap of Ge. Note that ET and EV, respectively denote the interface trap energy and valence band energy. The energy range for the applied gate voltages was extracted from the surface potential variation which can be measured by the following scheme: The surface potential is first considered for a given value of the capacitance from the theoretical capacitance vs. surface potential plot. In order to construct a voltage vs. surface potential plot, the gate bias on the measured C–V curve for the same value of the experimental capacitance is then taken repetitively [40]. The GP/x vs. frequency shown in Fig. 5 is much similar to that reported in Ref. [26] with measurement temperature of 300 K. Since Dit value is proportional to the peak value of GP/x, the similarity in the GP/x peaks for different gate voltage implies that a similar Dit in the measured energy range could also be found, which is consistent with the result shown in Ref. [5]. Dit extraction over the entire Ge bandgap can only be obtained with measurement temperature down to 80 K [26] and it will be discussed elsewhere. The Dit value extracted from full conductance measurement for the SiON and as-grown SiO2 film are 7.08 1011 and 5.33 1011 cm 2eV 1, respectively which is close to Ge midgap. This Dit value is superior to other approaches disclosed in the literature for Ge surface passivation and it is evidenced by the comparison of Dit value with various passivation approaches shown in Table 1. The Dit value for the SiON film lies in an acceptable range, and thus, verifies the passivation capability of this process. Note that the desirable Dit is mainly attributed to the thermally grown nature of the gate dielectric and the completely repelled Ge atoms from the oxide through which the epitaxial Ge layer is formed during the forming gas annealing. This is very much different from those forming the gate dielectric on a
Fig. 4. Capacitance–voltage hysteresis characteristics for the capacitor with SiON and as-grown SiO2 film.
Fig. 5. Full conductance measurement at 300 K of the n-MOSFET with SiON film as the gate dielectric.
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Table 1 Comparison of Dit among various Ge surface passivation approaches. *Bold type in the first column indicates the passivation layer. **Process in second column does not include subsequent annealing steps. Gate stack on Ge SiON/Al SiOx/HfSiO/WN SiOx/Al2O3/Pt GeOxNy/W GexNy/HfO2/W Hf3N4/GdScO3/WN AIN/Al2O3/WN GeOS/HfO2/W HfO2/Al La2O3/Pt
Process for surface passivation Thermal oxidation Atomic layer deposition Molecular beam epitaxy Thermal oxidation Remote plasma Atomic layer deposition Atomic layer deposition Immersion in liquid Thermal evaporation Electron beam evaporation
Dit extraction methods Conductance Conductance Conductance High/low frequency High/low frequency Conductance Conductance Conductance Conductance Conductance
Fig. 6. (a) Sub-threshold characteristics of the Ge n-MOSFET biased at drain voltage of 50 mV and 1 V. (b) Output characteristics of the SiON-gated Ge n-MOSFET.
Ge layer by deposition [15–17]. In fact, from the sub-threshold characteristics of the Ge n-MOSFET with a channel length of 20 lm shown in Fig. 6(a), a sub-threshold slope of 145 mV/dec is shown and from that, the sub-threshold slope of this level can be mainly associated with the acceptable Dit between the SiON film and Ge channel, which is consistent with the aforementioned Dit value and our previous work [41,42]. In addition, the smooth interface between the SiON film and Ge layer characterized by TEM shown in Fig. 1 may partly account for the acceptable Dit value. It is worth noting that the Dit value does not significantly degrade after the long nitridation time, and this desirable characteristic is due to the N2O treatment of which atomic oxygen could be generated and acts as the role for the partial removal of nitrogen in the bulk and interfacial parts of the oxide [43]. Fig. 6(b) displays the output characteristics of the SiON-gated Ge n-MOSFET. On the other hand, the smooth interface is also evidenced by the AFM scan
Dit near midgap (cm 11
7.08 10 1.0 1013 8.0 1012 1.0 1012 8.0 1012 1.0–3.0 1012 2.0 1012 2.4 1012 5.1 1012 1.0–2.0 1012
2
eV
1
)
Reference This work [37] [36] [6] [35] [17] [16] [13] [38] [39]
for the Ge surface by striping the SiON film in 1:100 (49% HF:H2O) dilute HF solution at 25 °C. The etching rate of the SiON film is about 2.3 nm/min which is comparable with that of a thermal SiO2 film on Si, and suggests a similar quality between them. The result of AFM scan is shown in Fig. 7, which reveals a small absolute roughness value (Rrms) of 0.62 nm. It compares favorably to the epitaxial Ge film formed by Ge deposition followed by hydrogen annealing in which the surface roughness is about 2.94 nm [44]. The smaller roughness value is a prerequisite to form a sharp and atomically smooth interface between the SiON film and Ge layer, which is quite beneficial to the improvement of the oxide reliability and carrier mobility. Besides C–V characteristics and AFM analysis, leakage current performance and dielectric conduction mechanism were also investigated. Fig. 8(a) shows the leakage current of the Ge MOS capacitor with SiON and as-grown SiO2 film. The asymmetric leakage current characteristic found in accumulation and inversion regime is similar to that of the GeON-gated MOS capacitor [7] and it is ascribed to the different carrier supply under different gate voltage polarity. As compared to the capacitor with as-grown SiO2 film, no leakage current degradation is observed for that with SiON film. This result can be attributed to the fact that the hydrogen related species such as –H and –OH bond, causing traps during the NH3 nitridation, are being effectively reduced by annealing out the hydrogen during the N2O treatment [45,46]. For the SiON film, the combination of an acceptable Dit value and an enhanced permittivity without compromising the leakage current shows that it is very desirable to be employed as the gate dielectric, as well as the interfacial layer for the integration of high-j gate dielectrics. Fig. 8(b) shows the ln (J/E2) vs. (1/E) relationship for the SiON-gated capacitor where J is the current density and E is the electric field. The measured characteristic of the SiON film fits Fowler–Nordheim (F–N) plot very well with an electron
Fig. 7. Topographical AFM image (5 5 lm) of the Ge surface.
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ther expected. Moreover, this thermal SiON film could also be scaled down by fine tuning the growth condition and/or etching back process [50] to become an interfacial layer for high-j integration in order to achieve a gate stack with eligible quality for nextgeneration advanced Ge MOS devices. On the other hand, from a process technology perspective, the intriguing point of this process lies in the fact that it can be realized by ULSI technology-compatible tools which renders this process more economic than others. 4. Conclusion By using a Si substrate, MOS devices with a SiON film as the gate dielectric formed on a Ge layer have been characterized. The SiON film is found to have negligible amount of Ge and very few oxide traps, which are evidenced by the small frequency dispersion and hysteresis performance. The Dit value of 7.08 1011 cm 2eV 1 close to Ge midgap is found to be acceptable, and proves that this dielectric is capable of effectively passivating a Ge surface, hence, is very useful toward boosting the carrier mobility for MOSFET devices. In addition, the SiON film reveals a higher permittivity value of 4.86 with respect to the as-grown SiO2 film without sacrificing the leakage current. The conduction mechanism through the SiON film has been confirmed to be F–N tunneling with extracted electron barrier height of 2.71 eV. Most importantly, it should be emphasized that the SiON film on a Ge layer can be formed on a Si substrate by existing ULSI technology without using any Ge substrate, which offers an economic way of fabricating high-performance Ge MOSFETs. Acknowledgment This work was supported by the National Science Council of Taiwan under Contract NSC 95-2221-E-007-252-MY2. Fig. 8. (a) Leakage current of the Ge MOS capacitor with SiON and as-grown SiO2 film as the gate dielectric. (b) Linear correlation between ln (J/E2) and (1/E) for the SiON-gated capacitor shows that F–N tunneling is the conduction mechanism.
barrier height of 2.71 eV. The dielectric mainly composed of SiON and the lack of traps in the dielectric may be responsible for F–N conduction mechanism. Due to the smaller electron affinity of Ge than Si, the barrier height between the SiON film and Ge layer is close to the theoretical value [47], which explains the superior leakage current performance against the GeON-gated MOS capacitor [7]. In fact, the conduction band offset of 2.71 eV is much larger than that reported in a GeO2/Ge heterostructure which corresponds to a conduction band offset in the range of 0.6–1.04 eV [48,49]. The larger conduction band offset is beneficial in suppressing gate leakage current, which confirms the amount of GeO in the SiON film to be negligible. As compared to prior arts for Ge surface passivation, the major advancement of the thermal SiON passivation disclosed in this work is the improvement in the Dit value, which is favorable to high-speed operation. By combining with the atomically smooth interface with Ge surface, employment of this thermal SiON film as the passivation layer implies a greater potential to achieve higher carrier mobility due to lessened scattering. Additionally, the thermal SiON possessing F–N conduction mechanism coupled with high conduction band offset with respect to Ge also suggests good dielectric quality and improved leakage current from which a better dielectric integrity and reliability can be anticipated. In fact, based on these promising characteristics, this passivation approach has been successfully integrated to accomplish high-speed Ge p-MOSFETs [42] and high-performance Ge-based silicon–oxide–nitride–oxide–silicon (SONOS) type nonvolatile memories [50], and more versatile applications can be fur-
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Electrical characteristics of Ge MOS device on Si substrate with thermal SiON as gate dielectric Yung-Hsien Wu *, Min-Lin Wu, Jia-Rong Wu, Yuan-Sheng Lin Department of Engineering and System Science, National Tsing-Hua University, 300 Hsinchu, Taiwan
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Article history: Received 1 April 2009 Received in revised form 31 March 2010 Accepted 20 April 2010 Available online 28 April 2010 Keywords: Ge MOS devices Thermal SiON Gate dielectric Interface trap density Conduction mechanism
a b s t r a c t Metal–oxide-semiconductor (MOS) devices, using a Si substrate and a thermal SiON film as the gate dielectric on a Ge layer, have been physically and electrically characterized. The small frequency dispersion and negligible hysteresis demonstrate very few oxide traps. The efficiency of Ge surface passivation is evidenced by the acceptable interface trap density of 7.08 1011 cm 2 eV 1 close to midgap, which is critical for the enhancement of the carrier mobility in MOSFET devices. On the other hand, for the thermal SiON film, a higher permittivity of 4.86 can be achieved by NH3 nitridation and a subsequent N2O treatment of an as-grown SiO2 film without compromising its leakage current. The conduction mechanism is confirmed to be Fowler–Nordheim (F–N) tunneling with extracted electron barrier height of 2.71 eV. Combining with these promising properties, the SiON film shows a great potential to further boost the performance of Ge MOSFETs. Most importantly, without using a Ge substrate, the SiON film on a Ge layer can be formed by the process fully compatible with incumbent ultra-large-scale integration (ULSI) technology, and hence, providing an economic way of fabricating high-performance Ge MOSFETs. Ó 2010 Elsevier B.V. All rights reserved.
1. Introduction Despite great advancement in high permittivity (high-j) gate dielectrics, metal gates and strain engineering, the effort to pursue devices with higher performance never slows down. Due to the superior carrier mobility against Si, germanium (Ge) has received much attention and been regarded as a potential channel material to accommodate the ever-stringent scaling requirement for future technology nodes. One of the major challenges in achieving high-performance Ge MOS devices is to maintain a good interface property between gate dielectric and Ge channel. In spite of the water-soluble property, a thermally grown GeO2 film has shown to possess good passivation for a Ge substrate [1]. However, extreme care should be exercised to prevent the formation of volatile GeO by the reaction between GeO2 and Ge substrate at temperature higher than 400 °C since this reaction would leave a huge amount of interface defects and traps [2,3], and causes the degradation of the electrical properties [4]. To effectively restrict the desorption of a GeO2 film at higher processing temperature, many research groups have explored the possibility of incorporating nitrogen or other elements into GeO2 to form GeON [5–10], GeZrO [11], GeZrSiO [12], or GeOS [13], which were reported to have good electrical characteristics. On the other hand, many non-GeOx based passivation methods such as surface SiH4 [14] or PH3 treatment * Corresponding author. Tel.: +886 3 5162248; fax: +886 3 5720724. E-mail address: [email protected] (Y.-H. Wu). 0167-9317/$ - see front matter Ó 2010 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2010.04.018
[15], and AlN [15,16] or Hf3N4 [17] deposition have been proposed to enhance interfacial quality. Using a Si cap with SiO2 film for Ge surface passivation is another way to realize good interfacial characteristics [18,19]. However, it requires rigorous control of the Si cap thickness to maintain desirable device performance [20]. In this work, without a Si cap, a thermal SiON film directly grown on a Ge layer was evaluated. In comparison with our previous work [21], aside from reducing the effective oxide thickness by means of thinning down the physical oxide thickness and enhancing the nitridation, this work also focuses on the analysis of interfacial property and conducting mechanism of the SiON film. Based on the negligible hysteresis, excellent frequency dispersion and interface trap density of 7.08 1011 cm 2eV 1 obtained from the SiON film; it shows the capability to be employed as a promising passivation method for Ge MOSFETs fabrication. Most importantly, the thermal SiON film on a Ge layer can be implemented on a Si substrate, which is not only less expensive but also compatible with existent ULSI technology.
2. Experiment After ex-situ HF vapor treatment to maintain a native-oxidefree surface of active areas on a (1 0 0)-oriented p-type Si substrate, an epitaxial Si0.3Ge0.7 layer was selectively formed in the active areas by amorphous Ge deposition and a subsequent thermal annealing [22]. Thereafter, a single crystalline Ge layer can be
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formed through oxidation of the Si0.3Ge0.7 layer at 900 °C followed by a forming gas annealing at 700 °C. Then, a thermal SiO2 film with 14.6 nm was concurrently grown on a 12-nm-thick Ge layer and served as the gate dielectric of Ge MOS capacitors. Detailed process conditions and mechanisms on implementing this film structure can be found in our previous work [21]. To further enhance permittivity of the SiO2 film, additional thermal nitridation in NH3 ambient and a subsequent N2O treatment was performed at 850 °C to form a desirable nitrided oxide [23]. The physical thickness of the nitrided oxide and as-grown SiO2 film was nearly the same after characterization by ellipsometer and TEM (Transmission Electron Microscopy). Finally, aluminum was evaporated and patterned as the gate electrode. X-ray photoelectron spectroscopy (XPS) analysis was performed to investigate bond structure of the oxide film. In order to mitigate the surface charging effect on the insulating film, a charge neutralizer (low-energy electron gun) was employed for charge compensation in the XPS measurement [24,25]. A sequence of Ar+ ion sputtering cycles (sputtering rate of 2.1 nm/min) interleaved with XPS measurement was utilized to obtain bond structure near the oxide surface and interface. Atomic force microscopy (AFM) was used to characterize the surface roughness of the Ge film. The eligibility for passivation was electrically evaluated by frequency dispersion, interface trap density (Dit) characteristics and gate leakage measurement. Note that to extract the interface trap density, Ge n-MOSFETs were also fabricated with the source/drain formed by phosphorous implantation and activation annealing at 600 °C for full conductance measurement [26]. 3. Results and discussion Fig. 1 manifests the cross-sectional TEM image for the sample with nitrided oxide. Besides confirming the physical thickness of 14.6 nm, smooth interface between the nitrided oxide and single crystalline Ge layer can be also observed which is beneficial for maintaining low interface traps and achieving high carrier mobility for MOS devices. Fig. 2 shows the Si 2p and Ge 3d spectra for the nitrided oxide from the XPS measurement. By comparing with the Si 2p spectrum of the thermal SiO2 film which has a signal at 103.6 eV, the strong Si 2p signal for the nitrided oxide at lower binding energy of 102.9 eV indicates that a large amount of nitrogen was incorporated in the oxide bulk rather than the interface to
Fig. 1. Cross-sectional TEM image for the sample with nitrided oxide.
Fig. 2. XPS Si 2p spectrum for the nitrided oxide. The inset shows Ge 3d spectra for the nitrided oxide.
form a silicon oxynitride (SiON) film. This is similar to the results published in the literature [27]. On the other hand, the weak and broad Ge 3d signal at 33 eV near the oxide interface together with the nearly flat signal close to the oxide surface prove that the amount of GeO content in the nitrided oxide is negligible. In contrast to the signal near the oxide surface, the stronger signal at 33 eV near the interface can be ascribed to the fact that Ge atoms are largely repelled to the oxide interface during Si0.3Ge0.7 oxidation, and that GeO content in the oxide can be continually decreased during the reduction process through the forming gas annealing [21,28]. This result is consistent with the SIMS analysis in our previous work [21] and confirms that a thermal gate dielectric mainly composed of SiON can be directly formed on a Ge layer, which would have greater capability to improve the electrical characteristics as compared to the commonly used GeOx-based dielectrics. Frequency dispersion of capacitance–voltage (C–V) characteristics is essential to assess the interfacial quality of a dielectric. The C–V frequency dispersion measured between 1 MHz and 1 kHz at 300 K for the capacitor with SiON film is shown in Fig. 3, and it displays less than 196 mV frequency dispersion in the depletion regime and no kinks near the inversion regime. It is worth noting that for many researches regarding the C–V characteristics of Ge MOS capacitors, inversion can be usually
Fig. 3. Capacitance–voltage frequency dispersion characteristics for the capacitor with SiON film. The inset is the comparison of hysteresis measured by ±5 V sweep at different frequencies for the capacitor with SiON film.
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observed at low measurement frequency (0.1–10 kHz) [6,26,29], which is quite different from that in this work. The formation of inversion layer can be attributed to the much shorter minority carrier response time and higher minority carrier generation–recombination rate for smaller-bandgap Ge as relative to Si counterpart [29]. The high defect density in a low quality Ge material is also known to facilitate the minority carrier generation–recombination rate. To better understand this phenomenon, it is worth noting the two possible mechanisms for minority carrier generation. One of which is that minority carriers are generated in the Ge bulk and then diffuse to the Ge/dielectric interface, while the other mechanism involves minority carrier generation in the depletion layer through bulk and interface traps. For the Ge device used in this work (12 nm Ge layer on Si substrate), the bulk material is primarily made of Si substrate, which lowers the possibility of minority carrier generation by the former mechanism. On the other hand, the good Ge crystallinity with limited bulk and interface traps of this device would suppress the minority carrier generation via the latter mechanism. These inferences may explain the C–V characteristics shown in Fig. 3. In fact, similar C–V characteristics for Ge MOS capacitors have been reported in Ref. [30,31], which attributes this phenomenon to the desirable interfacial property. The frequency-independent capacitance in the accumulation regime indicates that it is proper to extract the intrinsic oxide capacitance without including the series resistance effect [32]. The excellent hysteresis performance is also obtained at different frequencies ranging from 1 kHz to 1 MHz as evidenced in the inset of Fig. 3. Presented in Fig. 4 is the bi-directional C–V hysteresis characteristics for the capacitors with SiON and as-grown SiO2 film measured at 1 kHz with ±5 V voltage sweep. The negligible hysteresis for the SiON film suggests that the electron traps introduced during NH3 nitridation can be effectively alleviated by N2O treatment, which is very important for gate dielectric reliability. The extracted permittivity of the as-grown SiO2 film is about 3.92. This value is much different from that of a GeO2 film (j7) [33,34] and close to the conventional thermal SiO2 film (j3.9) on Si, which implies the negligible Ge content in the oxide and is consistent with the XPS results shown in Fig. 2. The higher capacitance in the accumulation regime for the nitrided oxide is ascribed to the incorporation of a large amount of nitrogen. The effective oxide thickness of the SiON film is extracted to be 11.7 nm with a permittivity of 4.86, which is nearly a 23.9% enhancement as compared with the asgrown SiO2 film. The relatively larger permittivity enhancement as compared to our previous work is due to the longer NH3 nitridation time, and the nitrogen concentration is about 11.8 at.% by XPS analysis. For Ge MOSFETs, a good interface trap density has been regarded as the effective means to improve the inferior
mobility enhancement in n-MOSFET over its p-MOSFET counterpart as compared with Si control sample [5,6]. Because of the low bandgap of Ge, the weak inversion response and strong inversion response due to minority carrier would dominate the conductance at 300 K and therefore makes the conventional conductance method, which assumes depletion, no longer correct for extracting the Dit value of Ge MOS capacitors [26]. To circumvent this issue, full conductance method is used to extract Dit in which a MOSFET or a gated diode with the bulk and source/drain shortened is employed for conductance measurement [26]. Fig. 5 displays the full conductance measurement for the n-MOSFET with SiON film as the gate dielectric at 300 K. Note that Gp is the parallel equivalent conductance after subtracting the reactance associated with Cox while x is the angular frequency. It is worth mentioning that this full conductance measurement was conducted at 300 K and the energy range at which the Fermi level could move (ET–EV) for the applied gate voltages (0.05–0.30 V) is about 0.24–0.34 eV, where it is near the midgap of Ge. Note that ET and EV, respectively denote the interface trap energy and valence band energy. The energy range for the applied gate voltages was extracted from the surface potential variation which can be measured by the following scheme: The surface potential is first considered for a given value of the capacitance from the theoretical capacitance vs. surface potential plot. In order to construct a voltage vs. surface potential plot, the gate bias on the measured C–V curve for the same value of the experimental capacitance is then taken repetitively [40]. The GP/x vs. frequency shown in Fig. 5 is much similar to that reported in Ref. [26] with measurement temperature of 300 K. Since Dit value is proportional to the peak value of GP/x, the similarity in the GP/x peaks for different gate voltage implies that a similar Dit in the measured energy range could also be found, which is consistent with the result shown in Ref. [5]. Dit extraction over the entire Ge bandgap can only be obtained with measurement temperature down to 80 K [26] and it will be discussed elsewhere. The Dit value extracted from full conductance measurement for the SiON and as-grown SiO2 film are 7.08 1011 and 5.33 1011 cm 2eV 1, respectively which is close to Ge midgap. This Dit value is superior to other approaches disclosed in the literature for Ge surface passivation and it is evidenced by the comparison of Dit value with various passivation approaches shown in Table 1. The Dit value for the SiON film lies in an acceptable range, and thus, verifies the passivation capability of this process. Note that the desirable Dit is mainly attributed to the thermally grown nature of the gate dielectric and the completely repelled Ge atoms from the oxide through which the epitaxial Ge layer is formed during the forming gas annealing. This is very much different from those forming the gate dielectric on a
Fig. 4. Capacitance–voltage hysteresis characteristics for the capacitor with SiON and as-grown SiO2 film.
Fig. 5. Full conductance measurement at 300 K of the n-MOSFET with SiON film as the gate dielectric.
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Table 1 Comparison of Dit among various Ge surface passivation approaches. *Bold type in the first column indicates the passivation layer. **Process in second column does not include subsequent annealing steps. Gate stack on Ge SiON/Al SiOx/HfSiO/WN SiOx/Al2O3/Pt GeOxNy/W GexNy/HfO2/W Hf3N4/GdScO3/WN AIN/Al2O3/WN GeOS/HfO2/W HfO2/Al La2O3/Pt
Process for surface passivation Thermal oxidation Atomic layer deposition Molecular beam epitaxy Thermal oxidation Remote plasma Atomic layer deposition Atomic layer deposition Immersion in liquid Thermal evaporation Electron beam evaporation
Dit extraction methods Conductance Conductance Conductance High/low frequency High/low frequency Conductance Conductance Conductance Conductance Conductance
Fig. 6. (a) Sub-threshold characteristics of the Ge n-MOSFET biased at drain voltage of 50 mV and 1 V. (b) Output characteristics of the SiON-gated Ge n-MOSFET.
Ge layer by deposition [15–17]. In fact, from the sub-threshold characteristics of the Ge n-MOSFET with a channel length of 20 lm shown in Fig. 6(a), a sub-threshold slope of 145 mV/dec is shown and from that, the sub-threshold slope of this level can be mainly associated with the acceptable Dit between the SiON film and Ge channel, which is consistent with the aforementioned Dit value and our previous work [41,42]. In addition, the smooth interface between the SiON film and Ge layer characterized by TEM shown in Fig. 1 may partly account for the acceptable Dit value. It is worth noting that the Dit value does not significantly degrade after the long nitridation time, and this desirable characteristic is due to the N2O treatment of which atomic oxygen could be generated and acts as the role for the partial removal of nitrogen in the bulk and interfacial parts of the oxide [43]. Fig. 6(b) displays the output characteristics of the SiON-gated Ge n-MOSFET. On the other hand, the smooth interface is also evidenced by the AFM scan
Dit near midgap (cm 11
7.08 10 1.0 1013 8.0 1012 1.0 1012 8.0 1012 1.0–3.0 1012 2.0 1012 2.4 1012 5.1 1012 1.0–2.0 1012
2
eV
1
)
Reference This work [37] [36] [6] [35] [17] [16] [13] [38] [39]
for the Ge surface by striping the SiON film in 1:100 (49% HF:H2O) dilute HF solution at 25 °C. The etching rate of the SiON film is about 2.3 nm/min which is comparable with that of a thermal SiO2 film on Si, and suggests a similar quality between them. The result of AFM scan is shown in Fig. 7, which reveals a small absolute roughness value (Rrms) of 0.62 nm. It compares favorably to the epitaxial Ge film formed by Ge deposition followed by hydrogen annealing in which the surface roughness is about 2.94 nm [44]. The smaller roughness value is a prerequisite to form a sharp and atomically smooth interface between the SiON film and Ge layer, which is quite beneficial to the improvement of the oxide reliability and carrier mobility. Besides C–V characteristics and AFM analysis, leakage current performance and dielectric conduction mechanism were also investigated. Fig. 8(a) shows the leakage current of the Ge MOS capacitor with SiON and as-grown SiO2 film. The asymmetric leakage current characteristic found in accumulation and inversion regime is similar to that of the GeON-gated MOS capacitor [7] and it is ascribed to the different carrier supply under different gate voltage polarity. As compared to the capacitor with as-grown SiO2 film, no leakage current degradation is observed for that with SiON film. This result can be attributed to the fact that the hydrogen related species such as –H and –OH bond, causing traps during the NH3 nitridation, are being effectively reduced by annealing out the hydrogen during the N2O treatment [45,46]. For the SiON film, the combination of an acceptable Dit value and an enhanced permittivity without compromising the leakage current shows that it is very desirable to be employed as the gate dielectric, as well as the interfacial layer for the integration of high-j gate dielectrics. Fig. 8(b) shows the ln (J/E2) vs. (1/E) relationship for the SiON-gated capacitor where J is the current density and E is the electric field. The measured characteristic of the SiON film fits Fowler–Nordheim (F–N) plot very well with an electron
Fig. 7. Topographical AFM image (5 5 lm) of the Ge surface.
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ther expected. Moreover, this thermal SiON film could also be scaled down by fine tuning the growth condition and/or etching back process [50] to become an interfacial layer for high-j integration in order to achieve a gate stack with eligible quality for nextgeneration advanced Ge MOS devices. On the other hand, from a process technology perspective, the intriguing point of this process lies in the fact that it can be realized by ULSI technology-compatible tools which renders this process more economic than others. 4. Conclusion By using a Si substrate, MOS devices with a SiON film as the gate dielectric formed on a Ge layer have been characterized. The SiON film is found to have negligible amount of Ge and very few oxide traps, which are evidenced by the small frequency dispersion and hysteresis performance. The Dit value of 7.08 1011 cm 2eV 1 close to Ge midgap is found to be acceptable, and proves that this dielectric is capable of effectively passivating a Ge surface, hence, is very useful toward boosting the carrier mobility for MOSFET devices. In addition, the SiON film reveals a higher permittivity value of 4.86 with respect to the as-grown SiO2 film without sacrificing the leakage current. The conduction mechanism through the SiON film has been confirmed to be F–N tunneling with extracted electron barrier height of 2.71 eV. Most importantly, it should be emphasized that the SiON film on a Ge layer can be formed on a Si substrate by existing ULSI technology without using any Ge substrate, which offers an economic way of fabricating high-performance Ge MOSFETs. Acknowledgment This work was supported by the National Science Council of Taiwan under Contract NSC 95-2221-E-007-252-MY2. Fig. 8. (a) Leakage current of the Ge MOS capacitor with SiON and as-grown SiO2 film as the gate dielectric. (b) Linear correlation between ln (J/E2) and (1/E) for the SiON-gated capacitor shows that F–N tunneling is the conduction mechanism.
barrier height of 2.71 eV. The dielectric mainly composed of SiON and the lack of traps in the dielectric may be responsible for F–N conduction mechanism. Due to the smaller electron affinity of Ge than Si, the barrier height between the SiON film and Ge layer is close to the theoretical value [47], which explains the superior leakage current performance against the GeON-gated MOS capacitor [7]. In fact, the conduction band offset of 2.71 eV is much larger than that reported in a GeO2/Ge heterostructure which corresponds to a conduction band offset in the range of 0.6–1.04 eV [48,49]. The larger conduction band offset is beneficial in suppressing gate leakage current, which confirms the amount of GeO in the SiON film to be negligible. As compared to prior arts for Ge surface passivation, the major advancement of the thermal SiON passivation disclosed in this work is the improvement in the Dit value, which is favorable to high-speed operation. By combining with the atomically smooth interface with Ge surface, employment of this thermal SiON film as the passivation layer implies a greater potential to achieve higher carrier mobility due to lessened scattering. Additionally, the thermal SiON possessing F–N conduction mechanism coupled with high conduction band offset with respect to Ge also suggests good dielectric quality and improved leakage current from which a better dielectric integrity and reliability can be anticipated. In fact, based on these promising characteristics, this passivation approach has been successfully integrated to accomplish high-speed Ge p-MOSFETs [42] and high-performance Ge-based silicon–oxide–nitride–oxide–silicon (SONOS) type nonvolatile memories [50], and more versatile applications can be fur-
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