Correlation of thermal annealing effect, crystallinity and electrical characteristics in c-axis crystallized InGaZnO thin-film transistors

Journal of Alloys and Compounds xxx (2015) xxx–xxx

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Correlation of thermal annealing effect, crystallinity and electrical characteristics in c-axis crystallized InGaZnO thin-film transistors Hsiao-Hsuan Hsu a, Shiang-Shiou Yen a, Yu-Chien Chiu a, Ping Chiou a, Chun-Yen Chang a, Chun-Hu Cheng b,⇑, Yu-Chien Lai c, Chih-Pang Chang c, Hsueh-Hsing Lu c, Ching-Sang Chuang c, Yu-Hsin Lin c a b c

Department of Electronics Engineering, National Chiao Tung University, Hsinchu 30010, Taiwan, ROC Department of Mechatronic Engineering, National Taiwan Normal University, Taipei 10610, Taiwan, ROC OLED Platform Technology Dept., AU Optronics Corporation, Taiwan, ROC

a r t i c l e

i n f o

Article history: Available online xxxx Keywords: InGaZnO Compound Crystal Thin film transistor

a b s t r a c t A low off-state current of 1.6  10 14 A/lm and a small subthreshold gate swing of 152 mV/decade were achieved in a novel thin film transistor using a c-axis crystallized InGaZnO semiconductor that could be obtained at a low substrate temperature range of 150 °C. From experimental results, we found that the lowered off-state current is mainly attributed to the formation of rich Ga–O bonds to reduce oxygen vacancies, and the c-axis crystallized structure of IGZO to increase the potential barrier on the source side due to the increase of local trap states at the grain boundary. Ó 2015 Elsevier B.V. All rights reserved.

1. Introduction The InGaZnO (IGZO) compound in amorphous state can reach a high mobility, which has been proposed for thin film transistor application [1–12]. As well known, the metal–oxide IGZO semiconductor was deposited by physical vapor deposition (PVD) such as sputtering. Although the sputtering system had the advantages of low cost, fast throughput and high process integration, the high drive voltage, high off-state current and unfavorable gate swing were the challenges for practical applications. Recently, a c-axisaligned IGZO channel has been implemented in thin film transistor (TFT) process. The c-axis-aligned IGZO TFT featured a low off-state current and large on–off ratio [13] that showed the potential for developing new applications including active matrix liquid crystal display (AMLCD) or active matrix organic light emitted diode (AMOLED). To understand the effect of c-axis orientation on IGZO semiconductor, we investigated the film crystallization based on different substrate temperature and post annealing treatment. The TFT characteristics with different c-axis-oriented IGZO channels were also measured for a performance comparison. In this work, the c-axis crystallized phase (<5 nm nano-crystal IGZO) could be observed

⇑ Corresponding author. Tel.: +886 2 77343514. E-mail address: [email protected] (C.-H. Cheng).

at a low substrate temperature of 150 °C. Even through the grain size of c-axis IGZO crystal gradually increased with annealing temperatures, the TFT devices had no apparent degradation on transfer characteristics. It can be ascribed to the c-axis crystallized orientation in IGZO channel, favoring an out-of-plane alignment and enhancing barrier height on the source side, especially for applying a negative gate bias to turn off. 2. Experiments The IGZO films were deposited by DC sputter system using an InGaZnO target with a composition ratio of In:Ga:Zn:O = 1:1:1:4. To observe the crystallized phases of IGZO compound, the different post-deposition annealing (PDA) conditions of 500 °C, 600 °C, and 700 °C were applied. The crystallinity of IGZO films were analyzed by X-ray diffraction (XRD). The structure and orientation of crystallized IGZO (c-IGZO) films were characterized by transmission electron microscopy (TEM). To confirm the influence of crystallized IGZO structure on TFT devices, the c-IGZO channels under different PDA conditions were also fabricated. The bottom-gated TFT process flow was described as follows. First, an n+ Si wafer with low resistivity was used as a bottom gate. Subsequently, a 50-nm-thick Al2O3 gate dielectric was deposited by e-gun evaporation system and followed by a dielectric annealing at 400 °C for 15 min. After gate dielectric patterning, a 90-nm-thick IGZO channel was deposited by sputtering with substrate temperature 150 °C and 200 °C in argon/oxygen mixed ambient. Because the in-situ annealing temperature was limited by sputter system, the substrate temperature only could be operated under <200 °C. To increase the crystallinity, the different post-annealing temperatures of 500 °C, 600 °C, and 700 °C were subsequently performed. To understand the effect of substrate temperature on film crystallization, the IGZO film with substrate temperatures of 150 °C and 200 °C were first analyzed. After depositing the gate stacks,

http://dx.doi.org/10.1016/j.jallcom.2014.12.207 0925-8388/Ó 2015 Elsevier B.V. All rights reserved.

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(a)

Al Contact (300nm)

IGZO (87 nm) Al2O3 (50 nm) n+ Si

(b) 1600

(c)

-5

10

Substrate temperature 1400

Intensity (a.u.)

1200 1000 800 600

o

@ 200 C

400

o

Drain Current, ID (A)

-6

(0 0 16)

10

-7

10

-8

10

-9

10

w/o sub. temp.

@ 150 C As-deposited

200 0

VD =1V

20

40

60

80

2θ (degree)

o

150 C (sub. temp.) -10

o

10

-0.5

200 C (sub. temp.) 0.0

0.5

1.0

1.5

2.0

2.5

Gate Voltage, VG (V)

Fig. 1. (a) Cross-sectional TEM image of IGZO/Al2O3 IGZO TFT. (b) XRD spectra of IGZO samples with substrate temperatures of 150 °C and 200 °C. (c) ID–VG characteristics of IGZO/Al2O3 TFT devices.

300-nm-thick Al metals was evaporated to form the source and drain contact electrodes. The channel size was then defined as 530 lm  30 lm. The crosssectional structure of IGZO TFT devices is shown in Fig. 1(a). Finally, the electrical property such as output and transfer characteristics were measured in these c-IGZO TFT devices incorporated with Al2O3 gate dielectrics.

3. Results and discussion The grain crystallization peaks of IGZO samples with two substrate temperatures can be observed in XRD spectra of Fig. 1(b). The (0 0 1 6) peak located at 33° corresponds to a crystal orientation of c-axis, which imply that the crystallinity of IGZO is much sensitive to substrate temperature, even processed at very low temperature range from 150 °C to 200 °C. Furthermore, the sharp (0 0 1 6) peak with higher intensity observed at higher substrate temperature of 200 °C indicates that the substrate temperature determines the nucleation behavior of c-axis crystallization. Nevertheless, a low substrate temperature is also preferred during the deposition of IGZO channel layer. The lower substrate temperature can control initial nucleation distribution and subsequent grain size, which is beneficial for the interface

quality between gate dielectric and IGZO channel during a thin film transistor process. Fig. 1(c) shows the ID–VG characteristics of IGZO TFT with and without a substrate temperature of 150 °C. The on- and off-state current (Ion/Ioff) ratio is significant improved from 3 to >4 order. The negative shift in the threshold voltage is due to the reduction of channel resistance. However, the reduced Ioff of 10 13 A/lm may be correlated to low-temperature crystallization. The lowered Ioff and enhanced Ion demonstrate the driving current is not only improved by a c-axis crystallized IGZO, but also the off-state current can be lowered simultaneously. To further investigate the c-axis crystallization of IGZO, the c-IGZO with a PDA of 500 °C was examined by TEM, selected area electron diffraction (SAED), and fast Fourier transforms (FFT). From top-view and cross-sectional TEM images, the micro-crystals of <5 nm is clearly observed in Fig. 2(a) and (b). The quasi-crystal like phase with short-range order structure is also confirmed by FFT pattern. The quasi-ordered (short-range order) structure mixed with c-axis micro crystals shows less grain-boundary issues, associated with the electrical nonuniformity and surface roughness.

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(a)

(b) IGZO

Al2O3

(c) Fig. 2. (a) Top-view TEM image (include FFT) and (b) cross-sectional TEM image of IGZO film with a thermal budget of 500 °C PDA. (c) TEM image of IGZO/Al2O3 interface.

The smooth interface between c-IGZO and Al2O3 gate dielectric can be observed in cross-sectional TEM of Fig. 2(c). The Al2O3 dielectric with large bandgap of 8.8 eV and good thermal stability [14] can be help for keeping a stable interface that is critical for gate leakage and subthreshold current. With increasing the temperature up to 700 °C, the grain size increases from 5 nm to 10 nm as shown in the top-view TEM images of Fig. 3(a). The SAED pattern with discontinuous diffraction

spots reveals a nano-crystallized phase in amorphous matrix. Combining In addition, based on AFM analysis as seen in 3(b), the root-mean-square (Rms) roughness gradually increases from 0.591 nm (at 150 °C) to 0.816 (at 700 °C). Such distinct Rms variation for partly nano-crystallized IGZO is also linked to channel leakage due to defect trap generation. Therefore, the IGZO surface roughness and grain boundary effect need to be considered during channel activation process. To further confirm the influence of grain

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(a) 0.9

Rms (nm)

0.8

0.7

0.6

0.5 100

200

300

400

500

600

700

o

Temperature ( C)

(b) Fig. 3. (a) Top-view TEM images and TEM-SAD pattern of IGZO film with a thermal budget of 700 °C PDA. (b) AFM Rms values of c-IGZO samples with different PDA temperatures.

size on TFT characteristics, we also fabricate the IGZO/Al2O3 TFT devices with different PDA temperatures. Fig. 4(a)–(c) shows the XPS spectra (Ga 2p, In 3d and Zn 2p) of c-IGZO films annealed at 500 °C and 700 °C. Apparently, the intensities of Ga–O and In–O changed with raising the PDA temperature from 500 °C to 700 °C. The increase of Ga–O bonds can explain that the oxygen atom compensate oxygen vacancies acting as donors to contribute free carrier in IGZO channel. Besides, the bonding structure of annealed IGZO films that may affect the channel stability maintains unchanged because of only slight binding energy shift among metal–oxide bonds. According to the results of IGZO crystallinity and metal–oxide bonding, we confirm that the degree of c-axis crystalline also company with the decrease of oxygen vacancies in IGZO channel generating leakage paths in the off state. In Fig. 5(a), the output (ID–VD) characteristic shows a saturated ID current of 5 lA at a small VG of 3 V. The small drive voltage can lower power consumption and save the switching energy during TFT device operation. Fig. 5(b) shows the transfer (ID–VG) characteristic. For c-IGZO TFT with 500 °C PDA, the extracted sub-threshold swing (SS) is about 173 mV/decade. The large SS is associated with interface state, which may not be avoided under a high annealing temperature. However, the very small threshold voltage of close to zero ( 0.01 V) is much impressive

to a metal–oxide IGZO TFT device. Compared to IGZO devices using a low substrate temperature of 150 °C (see Fig. 1), the Ioff is further improved by an order of magnitude from 1  10 13 A/lm to 2.5  10 14 A/lm. It is suggested that off-state current may be related to c-axis aligned crystallization, which have been reported [13]. From C–V (dielectric constant of Al2O3 7.6) and I–V curves of Al2O3 MIM capacitor (see inset of Fig. 5(b)), the gate leakage can be as low as 10 16 A/lm2. This confirms that the gate leakage path can be neglected under channel inversion. An apparently improved tendency on leakage current and SS is verified again at a higher PDA temperature of 700 °C. This is because the c-axis crystallized structure has many crystal grains that may increase the potential barrier on the source side due to the increase of local trap states at the grain boundary. Besides, the slightly reduced In–O bonds during annealing reflect a VT roll-off. Thus, the c-axis crystallized channel structure with rich Ga–O bonds leads to a lower off state current, even at a more negative gate voltage. Notably, the smaller SS of 152 mV/decade and lower Ioff of 1.6  10 14 A/lm are simultaneously observed at 700 °C PDA case, which provides the direct evidence in support of this work. Table 1 shows the devices characteristics of c-IGZO TFTs with various PDA temperatures. The annealed c-IGZO TFTs showed the highest lFE of 1.33 cm2/Vs at 500 °C PDA, but the lowest Ioff of

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75M

44M

500C 700C

38M

Ga 2p3/2

Intensity (a.u.)

Intensity (a.u.)

69M

500C 700C

63M

56M

50M

31M

In 3d5/2

In 3d3/2

25M

19M

13M

1110

1115

1120

1125

6M 440

1130

445

450

Binding Energy (eV)

Binding Energy (eV)

(a)

(b)

455

500C 700C

Intensity (a.u.)

50M

Zn 2p

3/2

44M

38M

31M 1015

1020

1025

1030

1035

1040

Binding Energy (eV)

(c) Fig. 4. (a) Ga–O, (b) In–O and (c) Zn–O spectra of IGZO film annealed at 500 °C and 700 °C.

6.0 10

3.0

1.5

VD = 1 V

700oC PDA -10

-8

10

2

10

Capacitance Density (fF/μm )

4.5

500oC PDA 600oC PDA

2

Drain Current, ID (A/ μm)

Drain Current, ID (μA)

VG = 0-3 V

-9

Current Density (A/ μm )

VG = 3 V

-11

10

-12

10

-13

10

-10

10

-12

10

-14

10

Al/Al2O3/TaN MIM

50 40 30

dielectric constant~ 7.6

20 10

Measured @100 kHz 0

-3

-2

-16

10

-4

-14

60

-3

-2

10

0.0 0

1

2

Drain Voltage, VD (V)

(a)

3

-1

0

1

-1 0 1 Voltage (V)

-1 0 1 2 Voltage (V)

2

Gate Voltage, VG (V)

(b)

Fig. 5. (a) ID–VD (measured at 700 °C) and (b) ID–VG characteristics of IGZO/Al2O3 TFT devices.

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2

3

3

3

4

4

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Table 1 Comparison of c-IGZO TFTs with different annealed temperatures. Temp.

VT (V)

500 °C 600 °C 700 °C

0.01 0.5 0.8

SS (mV/ dec)

On/off ratio

Ioff (A/lm)

Mobility (cm2/ Vs)

173 175 152

1.1  105 6.2  104 1.7  105

2.5  10 14 3.7  10 14 1.610 14

1.33 0.34 0.53

1.6  10 14 A/lm at 700 °C PDA. As improvement of subthreshold current become significant with increasing PDA temperature, the SS is reduced to 152 mV/dec. After high temperature 700 °C PDA, the on/off ratio still remain higher than five of magnitude (1.7  105) under a maximum overdrive voltage (VG–VT) of <4 V.

c-axis crystallized structure at 700 °C PDA contributes an improved off-state current, suggested that the potential barrier near source side is raised by the carrier trapping effect of grain boundary. References [1] [2] [3] [4] [5] [6] [7] [8] [9]

4. Conclusion In our work, the c-axis crystallized IGZO crystal was revealed under a low thermal budget of 150 °C. The low substrate temperature can be a key factor for c-axis oriented crystallization during film nucleation process. The TFT performance using c-axis aligned IGZO film may not be degraded with increasing temperature dependence of grain size. Additionally, a low off-state current of 1.6  10 14 A/lm has been confirmed in IGZO TFT devices with a thermal budget of 700 °C. The increased Ga–O bonds and

[10] [11] [12] [13]

[14]

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