Electrical Power and Energy Systems 117 (2020) 105638
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Electrical Power and Energy Systems journal homepage: www.elsevier.com/locate/ijepes
Dynamic space vector based discontinuous PWM for three-level inverters a
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Jiang Zeng , Zhihua Li , Lin Yang , Zhonglong Huang , Junchi Huang , Yiying Huang , ⁎ Bo Yangb, , Tao Yua a b
School of Electric Power, South China University of Technology, 510640 Guangzhou, People’s Republic of China Faculty of Electric Power Engineering, Kunming University of Science and Technology, 650500 Kunming, People’s Republic of China
A R T I C LE I N FO
A B S T R A C T
Keywords: Three-level inverter Dynamic space vector Discontinuous PWM Neutral point potential fluctuations
Three-level diode clamped inverters have been widely used in high-voltage and high-power applications, which can effectively increase the voltage/current limit of power electronic devices. This paper proposes a dynamic space vector based discontinuous PWM (DSV-DPWM) to enhance the robustness to neutral point potential fluctuations (NPPF). The proposed method generates a dynamic space vector (DSV) by detecting the voltages across upper capacitor and lower capacitor of inverter in the real-time, which then accurately synthesizes the vector reference. In particular, gh-coordinate and parity sector conversion approach are adopted to reduce the complexity of DSV-DPWM. Moreover, switching vector sequence that has opposite effect on neutral point potential is employed to eliminate neutral point potential offset (NPPO). DSV-DPWM performance is thoroughly analyzed based on error current vector. Both PSCAD/EMTDC simulation and digital signal processor (DSP) based hardware experiment using TMS320F28335 chip have been undertaken, which verify the advantages of DSVDPWM against traditional space vector based discontinuous PWM (TSV-DPWM).
1. Introduction Renewable energy [1] has been rapidly deployed in the globe for the sake of environment protection during the past decade. Typical applications include wind, solar, biomass, etc. A crucial part of renewable energy generation system is inverter, which converts DC current into AC current, such that the generated power could be integrated into the main power grid [2–7]. Generally speaking, inverters could be classified into two-level, three-level, and multilevel type. The control of two-level inverter is simple, but the output waveform distortion rate and switching tube stress are large. In contrast, the modulation mode of three-level inverter is flexible, which owns prominent advantages of large output capacity, small waveform distortion rate, low switching tube stress and small electromagnetic interference [8]. On the other hand, the control of multilevel inverter is very complicated. Hence, three-level inverters have gained an enormous attention. On one hand, the increase of inverter level can make the modulation mode more flexible. On the other hand, switching losses resulted from the increase of power devices cannot be ignored [9,10]. Normally, a satisfactory output waveform can be guaranteed by appropriate modulation. Meanwhile, the switching losses can be considerably reduced. The inverter control system usually adopts sine-wave pulse width
⁎
modulation (SPWM) or space vector pulse width modulation (SVPWM). In practice, SVPWM has been widely used due to the merits of wide linear modulation region, low output waveform distortion rate, and simple digitalization. It can be further divided into continuous SVPWM (CSVPWM) and discontinuous SVPWM (DSVPWM) [11]. Each phase switch can keep 60 degrees inactive in half cycle by DSVPWM, while the switch frequency could be reduced by 1/3 compared with CSVPWM. As a consequence, DSVPWM has more advantages in a certain modulation region [12–14] in the consideration of switching losses and output waveform harmonics. However, unbalanced neutral point potential, which often causes output waveform distortion, will be emerged in diode clamping type (NPC) based three-level inverters. Under such condition, the switching tube has to suffer inconsistent voltage that would shorten its operation life [15–19]. CSVPWM can achieve neutral point potential balance by adjusting the action time of redundant small vectors. However, the balance effect is determined by power factor and modulation degree, in which there exists an unbalanced modulation region [20]. Neutral point potential balance in the fully modulated region was achieved via virtual space vector modulation [21], which however also increases the switching losses. In practice, DSVPWM has severer neutral point potential fluctuations (NPPF) against SVPWM due to the fact that no redundant vector is available for adjustment [22–26].
Corresponding author. E-mail address:
[email protected] (B. Yang).
https://doi.org/10.1016/j.ijepes.2019.105638 Received 5 March 2019; Received in revised form 19 August 2019; Accepted 16 October 2019 0142-0615/ © 2019 Elsevier Ltd. All rights reserved.
Electrical Power and Energy Systems 117 (2020) 105638
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To handle this difficulty caused by neutral point potential offset (NPPO) [27–30], many studies have been undertaken. Literature [22] achieved neutral point potential control by dynamically adjusting positive/negative half-cycle discontinuous pulse width of output voltage. Moreover, Based on hysteresis loop, reference [23] divided the vector sequences of each triangular region into positive and negative ones, which have opposite effects on the neutral point potential. In particular, the neutral point potential is limited to a fixed ring width by dynamically switching the sequence of positive and negative vectors. Nevertheless, the aforementioned approaches only control the neutral point potential in power frequency cycle while NPPF is still quite significant. In order to solve the above issue, this paper attempts to develop a dynamic space vector based DPWM (DSV-DPWM). At first, DSV-DPWM generates a dynamic space vector (DSV) by detecting the capacitor voltage of inverters in the real-time, which then accurately synthesizes the vector reference. Then, gh-coordinate and parity sector conversion method are adopted to reduce its complexity. Moreover, switching vector sequence with opposite effect on neutral point potential is employed to eliminate its offset. This strategy can effectively enhance the robustness to NPPF, together with a noticeable reduction of output waveform distortion and switching losses.
Fig. 2. Space vector diagram of three level inverter.
⎧Udc1 = ⎨Udc2 = ⎩
2. Three-level inverter and neutral point potential
(1 + k ) Udc 2 (1 − k ) Udc 2
(1)
2.2.1. Change of small vectors The coordinates of positive small vector POO in abc-coordinate can be written by
2.1. Three-level diode clamped inverter modelling Fig. 1 shows the structure of a typical three-level inverter. Here, C1 and C2 represent the DC bus capacitors. Each bridge arm contains four power switch tubes, denoted as Sx1, Sx2, Sx3, and Sx4 (x = a, b, c), respectively. It also includes three output states, e.g., P (the conduction of Sx1 and Sx2), O (the conduction of Sx2 and Sx3), and N (the conduction of Sx3 and Sx4), respectively. The three-level inverter has 27 space vectors in total, e.g., 3 zero vectors, 12 small vectors, 6 medium vectors, and 6 large vectors. It is divided into 6 sectors, S1-S6, while each sector is divided into 6 small regions. Taking an example of S1 of Fig. 2, PPN is large vector, PON is medium vector, PPO, POO, OON, ONN is small vector, PPP, NNN, OOO is zero vector. In the case of neutral point potential balance, the positive and negative small vectors do not coincide such as PPO and OON, POO and ONN, and all the vector vertices are surrounded by equilateral triangles.
VPOO\_abc = (Udc, Udc2, Udc2)
2.2. Effect of neutral point potential imbalance on fundamental vector
2.2.2. Change of medium vectors The coordinates of PON in abc-coordinate can be written as
(2)
After NPPO occurs, it becomes
V ′POO\_abc = (Udc,
(1 − k ) Udc (1 − k ) Udc ) , 2 2
(3)
Transform it into αβ-coordinate, yields
′ VPOO_α β = (
(1 + k ) Udc , 0) = (1 + k ) VPOO 3
(4)
Similarly, the change of negative small vector ONN can be obtained by
′ VONN_α β = (
(1 − k ) Udc , 0) = (1 − k ) VONN 3
(5)
It can be seen that, when NPPO occurs, the direction of small vector remains unchanged but the magnitude changes.
Space vector of inverter will be changed when NPPO occurs, which then affects the synthesis of vector reference. Here, Udc is the DC-link capacitor voltage and Udc1, Udc2 are used to represent the voltage across capacitor C1 and C2, respectively. To describe the imbalance degree of neutral point potential, an offset factor k (-1 < k < 1) is introduced, thus Udc1 and Udc2 can be expressed as
VPOO\_abc = (Udc, Udc2, 0)
(6)
After NPPO occurs, it obtains
V ′PON\_abc = (Udc,
(1 − k ) Udc , 0) 2
(7)
Transform it into αβ-coordinate, gives
′ VPON_α β = (
(3 + k ) Udc , 6
3 (1 - k ) Udc ) 6
(8)
Obviously, both the direction and magnitude of medium vector change after NPPO occurs. 2.2.3. Change of large and zero vectors The large and zero vectors do not contain Udc1 and Udc2 in their coordinates, so they do not change after NPPO occurs. Fig. 3 illustrates the space voltage vector (SVV) diagram considering NPPF. Taking an example of S1. The dotted red line represents the position of each vector before NPPF. It shows that the positive and negative small vectors will be separated, such as PPO and OON, POO
Fig. 1. Structure of a three-level inverter. 2
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⎧Vref cos(θ) = Vrefα V cos(θ) = Vrefg ⎨ ⎩ ref ⎧Vref sin (θ) = Vrefβ ° ⎨ ⎩Vref cos(60 - θ) = Vrefh
(10)
Eliminate variables Vref and θ, yields
⎡ Vrefg ⎤ = ⎡ 1 ⎢ ⎣Vrefh ⎥ ⎦ ⎣1/2
0 ⎤ ⎡Vrefα ⎤ V ⎦ 3 /2 ⎦ ⎢ ⎣ refβ ⎥
(11)
Therefore
1 H=⎡ ⎣1/2
0 ⎤ 3 /2 ⎦
(12)
The coordinate transformation matrix R1 can rotate a vector counterclockwisely by 120° via a rotation factor ej120°, while the coordinate transformation matrix R2 can rotate a vector counterclockwise by 240° via a rotation factor ej120°, the specific derivation as follows:
Fig. 3. SVV diagram considering NPPF.
and ONN do not coincide while the magnitude and phase angle of the medium vector also change. Such as PON becomes PON’ Here, if the sector determination and vector action time are calculated by conventional fixed SVV, the synthetic error of vector reference will be emerged, which results in a distortion of output voltage and current waveform.
Vα _R1 + jVβ _R1 = (Vα + jVβ ) e j120
°
=Vα × (cos(120°) + j sin 120°) + jVβ (cos(120°) + j sin 120°) 1
=− 2 × Vα −
3 2
× Vβ + j (
Vα _R2 + jVβ _R2 = (Vα + jVβ ) e j240
3 2
× Vα −
1 2
× Vβ )
°
=Vα × (cos(240°) + j sin 240°) + jVβ (cos(240°) + j sin 240°) 1
=− 2 × Vα +
3. Dynamic space vector based discontinuous modulation
3 2
× Vβ + j (−
3 2
× Vα −
1 2
× Vβ ) (13)
The space vector modulation usually includes sector determination, calculation of output vector action time, vector sequences arrangement (VSA), etc. [31]. This section aims to analyze the implementation of dynamic space vector based on discontinuous modulation algorithm under NPPF.
Therefore
⎡− 1 − R1 = ⎢ 2 ⎢ 3 − ⎣ 2
⎡− ⎤ ⎥, R2 = ⎢ ⎢− ⎥ ⎣ ⎦
1 2 3 2
3 2
−
⎤ ⎥
1⎥ 2⎦
(14)
Moreover, Table 1 shows the converting of odd sector into the first sector. From the coordinate transformation, the even sector is converted into the second sector, which has the same expression of odd sector.
3.1. Vector reference sector conversion Fig. 3 shows that the region surrounded by space vector is no longer a standard equilateral triangle under NPPF. Thus, traditional simplification are inadequate, i.e., 60° coordinate system [32], virtual coordinate system modulation [21]. However, it can be found that the odd sector and even sector still have symmetry, thus the modulation can be simplified through vector reference sector conversion. Based on gh-coordinate(gh coordinate system is a 60° coordinate system, that is, the g-axis coincides with the α-axis in the αβ coordinate system, and a counterclockwise rotation of 60° as the h-axis), odd sector can be transformed into the first sector and even sector can be transformed to the second sector in the space vector diagram by Eq. (9), which simplifies the time calculation of output vector and determines the sequence of basic space vector action.
⎡ Vg ⎤ = H ⎡Vα ⎤ = HR ⎡Vrefα ⎤ = HRH−1 ⎡ Vrefg ⎤ V ⎢ ⎢ ⎢ ⎢ ⎥ ⎣ Vβ ⎦ ⎣Vh ⎥ ⎦ ⎣ refβ ⎥ ⎦ ⎦ ⎣Vrefh ⎥
3 2 1 2
3.2. Arrangement of space vector sequence The discontinuous modulation of three-level inverter can be divided into four types (DPWM0 ~ DPWM3) according to inactive areas of switching tube. In some cases, the switching losses play the major part of power device losses. In order to minimize the switching losses, the phase switching tube can be inactivated when approaching the peak and valley of each phase current [23,33,34] (called large current no switch). In general, distribution power grid operates at the unit power factor, in which DPWM1 type can be adopted to achieve large current no switch. Take the first sector (S1) of Fig. 2 as an example, the suitable vector sequences for each region are provided in Table 2. Since the power grid usually operates at high modulation ratio, the
(9)
Table 1 Odd sector conversion process.
In Eq. (9), Vrefg and Vrefh represent the projection of basic space vector in gh-coordinate. Vrefα and Vrefβ represent the projection of basic space vector in αβ-coordinate. Vg and Vh denote the projection in ghcoordinates after basic space vector is converted into the first/second sector. Vα and Vβ denote the projection in αβ-coordinates after basic space vector is converted into the first/second sector. H is the transformation matrix from αβ-coordinate to gh-coordinate. The specific derivation are given as follows: Denote coordinate (Vrefα, Vrefβ) as the reference voltage vector Vref∠θ in the αβ coordinate system, while coordinate (Vrefg, Vrefh) is the reference voltage vector Vref∠θ in the gh coordinate system, gives
Sector number
The expression after converting to the first sector
The expression after converting to the first sector
1 3 5
Vg = Vrefg Vg = Vrefh Vg = -Vrefg-Vrefh
Vh = Vrefh Vh = -Vrefg-Vrefh Vh = Vrefg
Sector number
The expression after converting to the second sector Vg = Vrefg Vg = Vrefh Vg = -Vrefg-Vrefh
The expression after converting to the second sector
2 4 6
3
Vh = Vrefh Vh = -Vrefg-Vrefh Vh = Vrefg
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Table 2 VSA of the first sector.
Table 4 Action time of odd sector vector.
Region number
Vector sequence
Time
Region 1
Region 2
1 2 3 4 5 6
POO-PON-PNN-PON-POO PPN-PON-OON-PON-PPN PPO-POO-PON-POO-PPO PON-OON-ONN-OON-PON PPP-PPO-POO-PPO-PPP OON-ONN-NNN-ONN-OON
t1 t2 t3
Ts(Vg + Vh-2)/(k-1) - TsVh/(k-1) Ts-t1-t2
Ts (Vg + Vh-1)/(k + 1) TsVg/(k + 1) Ts-t1-t2
Time
Region 3
Region 4
t1 t2 t3
Ts(Vh + k-1)/(k-1) Ts-t1-t3 Ts(k-Vg + 1)/(k + 1)
TsVg/(k + 1) Ts-t1-t3 - TsVh/(k-1)
Table 3 Default VSA of the first sector. Region number
Vector sequence
1 2 3 4
POO-PON-PNN-PON-POO PPN-PON-OON-PON-PPN POO-PON-OON-PON-POO POO-OOO-OON-OOO-POO
Table 5 Action time of even sector vector.
operation time of region 3, 4, 5 and 6 is relatively short. In order to simplify the modulation, the original region 3 and 4, as well as 5 and 6 are merged into new region 3 and region 4, respectively. Here, they have flexible vector sequences, which can be used to adjust neutral point potential. In addition, region 1 and region 2 can realize large current no switch. Thus NPPO is prevented while the switching losses can be reduced significantly. From Table 3, region 3 and region 4 adopt switching sequence with self-balancing function of neutral point potential by default. According to VSA, space vector partition considering NPPF is illustrated by Fig. 4.
Region 1
Region 2
t1 t2 t3
Ts(Vh-2)/(k-1) - Ts(Vg + Vh)/(k-1) Ts-t1-t2
Ts(Vg + Vh + k-1)/(k + 1) - TsVg/(k + 1) Ts-t1-t2
Time
Region 3
Region 4
t1 t2 t3
Ts(Vg + Vh + k-1)/(k-1) Ts-t1-t3 Ts(Vg + k + 1)/(k + 1)
- TsVg/(k + 1) Ts-t1-t3 - Ts(Vg + Vh)/(k-1)
Clearly, the sector conversion method based on gh-coordinate can still obtain the action time of each dynamic space vector in each region through simple calculation. Hence, the complexity of DSV-DPWM is similar to that of traditional simplified algorithm. Furthermore, DSVDPWM can accurately synthesize the voltage reference vector.
3.3. Calculation of space vector action time
3.4. Neutral point potential offset elimination based on vector sequence switching
It can be seen from Fig. 4 that the coordinate of each output vector are related to the offset factor k in gh-coordinate, which has a very concise form. According to Volt-second balance [35], the action time of basic space vector when the vector reference is located in four regions can be obtained as
⎧Vrefg1 t1 + Vrefg2 t2 + Vrefg3 t3 = Vrefg Ts V t + Vrefh2 t2 + Vrefh3 t3 = Vrefh Ts ⎨ refh1 1 ⎩t1 + t2 + t3 = Ts
Time
Switching hysteresis control of vector sequence is used to eliminate NPPO caused by system parameter uncertainties and other factors. As described in Section 3.2, the neutral point potential is controlled in region 3 and region 4. In particular, the switching vector sequences of region 3 and region 4 under the unit power factor can be divided into three types: positive bias (mode 0), self-balance (mode 1), and negative bias (mode 2) to the neutral point potential, respectively. The vector sequences of region 3 are given in Table 6 and Fig. 4. Through the hysteresis control of neutral point potential, self-balancing sequence of mode 1 is adopted under the balanced state. When the neutral point potential crosses negative hysteresis boundary, it will switch to mode 0 to increase the neutral point potential in Fig. 4b. In contrast, when the neutral point potential crosses positive hysteresis boundary, it will switch to mode 2 to decrease the neutral point potential in Fig. 4a. Note that mode 1 is adopted by default in the balanced state, while the magnitude of common mode voltage of inverter can be effectively reduced [36–38].
(15)
In Eq. (15), Vrefg and Vrefh represent the projection of voltage reference vector in gh-coordinate system. (Vrefg1, Vrefh1), (Vrefg2, Vrefh2), and (Vrefg3, Vrefh3) represent three basic space vectors for synthesis. In addition, t1, t2, and t3 denote the action time of three basic space vectors, Ts is switching period respectively. When the vector reference locates between each region in odd sector and even sector, the action time of basic space vector is summarized in Tables 4 and 5, respectively.
Table 6 Vector sequences of region 3.
Fig. 4. Space vector partition diagram of Sector 1 considering NPPF. (a) Udc1 > Udc2, (b) Udc1 < Udc2. 4
Sector
Mode 0
Mode 1
Mode 2
1 2 3 4 5 6
PON-OON-ONN OPN-OON-NON NPO-NOO-NON NOP-NOO-NNO ONP-ONO-NNO PNO-ONO-ONN
POO-PON-OON OPO-OPN-OON OPO-NPO-NOO OOP-NOP-NOO OOP-ONP-ONO POO-PNO-ONO
PPO-POO-PON PPO-OPO-OPN OPP-OPO-NPO OPP-OOP-NOP POP-OOP-ONP POP-POO-PNO
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starting point of the error current vector Δi1 is at point O according to Eq. (19), and the terminal moves from point O to point A along the direction of the error voltage vector ΔV1. (c) In the range [t1/2, t1/2 + t2/2], voltage vector V2 acts, while the terminal moves from point A to point B along the direction of the error voltage vector ΔV2. In the range [t1/2, t1/2 + t2/2 + t3/2], voltage vector V3 acts, and the terminal moves from point B to point O along the direction of the error voltage vector ΔV3.
4. Error current analysis of DSV-DPWM Total harmonic distortion rate (ITHD) of output current or weighted total harmonic distortion rate (VTHD) of output voltage [30] are usually used to evaluate the output waveform quality of inverters. Their calculation will be very complicated considering NPPF due to Fourier decomposition. As a result, output waveform quality evaluation method based on current error vector is employed to analyze the output waveform quality improvement of DSV-DPWM. In AC output side of inverter shown by Fig. 1, the actual vector equation of inverter and vector reference by ignoring resistance are obtained as follows:
Note that the second half of the cycle can be analyzed in the same way. Therefore, the error current vector trajectory can be obtained as shown in Fig. 5b when DSV-DPWM is adopted. Within a switching period Ts, the root-mean-square (RMS) of current error ΔI is defined as
di
⎧V = Lg dt + e ⎨Vref = Lg diref + e dt ⎩
(16)
where V and i are the actual voltage vector and current vector of inverter, Vref and iref are the voltage reference vector and current reference vector, e is the grid voltage vector and Lg is the AC filter inductance. The voltage error vector ΔV and current error vector Δi are defined as
⎧ ΔV = V − Vref ⎨ ⎩ Δi = i − i ref
(17)
⎨V = ( 1 − k , 3 2 ⎩
(18)
Integrate both sides, gives
1 Δi j = Lg
∫ ΔVj dt
Ts
|Δi|2 dt
(20)
⎧V1 = (1 + k , 0), V2 = ( 3 +2 k ,
d Δi j dt
∫0
Because the current error vector trajectory is half-circle symmetric, one can just integrate the first three segments of current error ΔI in Eq. (20) to obtain the RMS of current error. Particularly, in sector 1, the action time of voltage vector can be obtained from Tables 4 and 5. In order to simplify the expression, the basic voltage vector is adjusted on the complex plane (α,β) with Udc/3 as the reference value, Vpα, Vpβ represent the unit value of the reference voltage vector Vref in αβ-coordinate gives
When the fundamental space vector Vj of inverter is applied, the error vector trajectory ΔVj becomes
ΔVj = Vj − Vref = Lg
1 Ts
ΔI =
3 2
3 2
(1 − k ))
(1 − k )), Vref = (Vpα , Vpβ )
(21)
In range [0, t1/2], voltage vector V1 acts and current error vector Δi1 varies along OA, which initial value is (0, 0), yields (19)
1 Ts
ΔI1 =
When Vref is located at region 3 shown in Fig. 3a, the voltage error vector ΔV1(POO) acts at first, one can obtain the voltage error vector ΔV1 because of the voltage error vector ΔV1 = V1-Vref. Then, the voltage error vector ΔV2(PON) acts, one can obtain the voltage error vector ΔV2 because of the voltage error vector ΔV2 = V2-Vref. Finally, the voltage error vector ΔV3(POO) acts, one can obtain the voltage error vector ΔV3 because of the voltage error vector ΔV3 = V3-Vref. Therefore, the error voltage vector trajectory can be illustrated by Fig. 5a. According to the modulation strategy in Table 3, the action order of voltage vectors in region 3 is as follows: POO-PON-OON-PON-POO. The time of action is t1/2, t2/2, (t3/2, t3/2), t2/2, and t1/2, respectively. Due to the symmetry of its modulation strategy, only the error current vector trajectory in the first half of the cycle is analyzed as follows:
∫0
t1 2
[(1 + k − Vpα )2 + Vp2β ] t 2dt
(22)
In range [t1/2, t1/2 + t2/2], voltage vector V2 acts, while current error vector Δi2 varies along AB, which initial value is
t t (iα 0, iβ 0) = ((1 + k − Vpα ) 1 , −Vpβ 1 ) 2 2
(23)
and
ΔI2= 1 Ts
t1+ t 2 2
∫t1 2
(
⎡ iα0 + ⎢ ⎣
(
3+k 2
))
− Vpα t
2
(
+ iβ 0 +
(
3 2
))
2
(1 − k ) − Vpβ t ⎤ dt ⎥ ⎦ (24)
In range [t1/2, t1/2 + t2/2 + t3/2], voltage vector V3 acts, while current error vector Δi3 varies along BO. In order to simplify the calculation, the inverse integral is used, which initial value is (0,0), obtains
(a) At the beginning of the sampling, the error current vector is 0, while the start and end points of the trajectory are at the origin O. (b) In the range [0, t1/2], voltage vector V1(POO) acts, while the
ΔI3 =
1 Ts
∫0
t3 2
[(
1−k 3 (1 − k ) − Vpβ )2] t 2dt − Vpα )2 + ( 2 2
(25)
The RMS of current error ΔI can be obtained by
ΔI =
2Udc (ΔI1 + ΔI2 + ΔI3) 3Lg
(26)
Based on the above analysis, the current error variation rule can be obtained on the entire space vector plane. Fig. 6a shows a three-dimensional distribution diagram of RMS of current error based on DSV-DPWM in the neutral point potential balance scenario. One can find that RMS of current error in sector 1 presents a multi-peak distribution. Besides, a closer distance to the interval vertex results in a smaller current error. Fig. 6b shows the current error ratio (CER) distribution of DSV-DPWM and TSV-DPWM which don't
Fig. 5. Error vector trajectory. (a) Voltage error vector, (b) Current error vector. 5
Electrical Power and Energy Systems 117 (2020) 105638
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Fig. 6. Three-dimensional diagram of different strategies. (a) Current error distribution of DSV-DPWM under balanced scenario, (b) CER of DSV-DPWM and TSV-DPWM under 30% NPPF.
take into account the change of vectors under NPPF under a 30% NPPO. It can be seen that the ratio of current error is less than 1 in large range. Besides, DSV-DPWM can reduce current error and track the reference more accurately than TSV-DPWM.
5. Case studies Case studies are carried out through PSCAD/EMTDC. The system parameters are given as follows: upper and lower capacitance of inverter: C1 = C2 = 150 μF, LCL filter parameters of inverter are: L1 = 0.74 mH, Cg = 55 μF, L2 = 55 μH, DC voltage equals to 640 V, and the switching frequency is 20 kHz. Fig. 7a shows the voltage and current from literature [16] of DSVPWM when the load is 12 Ω. Obviously, it can suppress NPPF within a given hysteresis loop width. The output current quality is considerably improved, e.g., harmonics distortion rate reduced from 4.8% to 1.9% with the decrease of NPPF. However, the non-operation interval of switching tube reduces significantly with the decrease of hysteresis loop width after 0.04 s and the growth of switching frequency, which results in relatively high switching losses (see Figs. 8 and 9). Fig. 7b and c compare the robustness of TSV-DPWM and DSVDPWM to NPPF, in which the magnitude of NPPF reaches around 60 V. Fig. 7b demonstrates the output current of TSV-DPWM causes large distortions with a 4.3% current THD. In contrast, the current of DSVDPWM is not affected by NPPF, while the current THD is merely 1.6%, as shown in Fig. 7c. The space voltage vector depicted in Fig. 7d further shows that DSVDPWM can maintain a smooth circular vector trajectory under large DC voltage fluctuations. In contrast, it is not a standard circle by TSVDPWM. The following specifically analyzes the formation of the voltage space vector loop in Fig. 7d. Define three voltage space vectors denoted by Ua(t), Ub(t), Uc(t). Their direction is always on the axis of each phase that is spatially different by 120°, which magnitude changes sinusoidally with 120° phase difference each other. Let Um be the phase voltage peak value,
Fig. 7. Voltage and current of DSVPWM. (a) DSVPWM based on vector switching, (b) TSV-DPWM, (c) DSV-DPWM, (d) Voltage of DSVPWM.
Fig. 8. The synthesise of the general vector V.
6
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Fig. 9. The diagram of inverter bridge arm output voltage vector.
Fig. 10. Harmonics distortion of output current under different load conditions. (a) TSV-DPWM, (b) DSV-DPWM.
Fig. 11. Phase voltage and current waveform. (a) TSV-DPWM under light load condition, (b) DSV-DPWM under light load condition, (c) TSV-DPWM under heavy load condition, (d) DSV-DPWM under heavy load condition.
Table 7 System parameters of hardware experiment.
V (t ) = Ua (t ) + Ub (t ) e j2π /3 + Uc (t ) e j 4π /3 =
System parameters DC capacitance/μF
C1/μF C2/μF
150 150
LCL filter
L1/mH Cg/μF L2/μH
0.74 55 55
DC voltage/V Switching frequency/kHz Load
(28)
Here, the vector V(t) can be used to represent Ua(t), Ub(t), Uc(t), and the projection of vector V(t) on the three-phase axes of A, B, and C is equal to the instantaneous value of each phase voltage. Moreover, it can be seen that V(t) is a rotating space vector associated with an amplitude of 1.5 times of the phase voltage peak value, which rotates anticlockwisely at an angular frequency of 2πf. In general, V(t) is also called general vector V. The DSV-DPWM control strategy aims to synthesize the general vector V by using different space voltage vectors in different sectors. For example, when the general vector V is located in the third region of the first sector, the general vector V is synthesized using the basic space vector as shown below. where the circle represents the acts of the zero vector: Since the general vector V is a rotated space vector, it is synthesized by different space voltage vectors when it is rotated to different sectors. Finally, when the general vector V forms a circle, while the simulation diagram of the output voltage vector of the inverter bridge arm becomes: The output voltage vector of the inverter bridge arm contains a large
640 20 adjustable
and f be the change frequency, gives
⎧Ua (t ) = Um cos(2πft ) Ub (t ) = Um cos(2πft − 2π /3) ⎨ ⎩Uc (t ) = Um cos(2πft + 2π /3)
3 Um e j2πft 2
(27)
Therefore, the space vector V(t) obtained by adding the three phase voltage space vectors can be expressed as: 7
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(2) Through gh-coordinate and parity sector conversion, the complexity of dynamic space vector is considerably reduced; (3) NPPO can be effectively eliminated via switching vector sequence with opposite effect on neutral point potential; (4) DSV-DPWM performance is thoroughly analyzed based on error current vector; (5) Simulation and hardware experiment verify the effectiveness and implementation feasibility of DSV-DPWM.
Table 8 Current THD of DSVPWM under different loads. Load
Fluctuating voltage /V
TSV-DPWM
DSV-DPWM
R1 R2 R3 R4
10 26 35 63
2.45% 2.87% 3.81% 5.36%
2.41% 2.34% 2.48% 2.59%
Declaration of Competing Interest
Table 9 Comparison of modulation efficiency. Load
R1 R2 R3 R4
CSVPWM
I can hereby confirm there is no interests conflict of the work to anyone.
DSV-DPWM
Pi/kW
Po/kW
η%
Pi/kW
Po/kW
η%
3.571 4.713 7.180 11.912
3.480 4.600 7.013 11.628
97.45 97.61 97.68 97.62
3.58 4.731 7.213 11.897
3.511 4.641 7.077 11.670
97.98 98.09 98.12 98.09
Acknowledgments The authors gratefully acknowledge the support National Natural Science Foundation of China (61963020, 51777078), the Fundamental Research Funds for the Central Universities (D2172920), the Key Projects of Basic Research and Applied Basic Research in Universities of Guangdong Province (2018KZDXM001), the Science and Technology Projects of China Southern Power Grid (GDKJXM20172831), and Science and Technology Project of State Grid Corporation of China (Research on Demand Strategies of Multi-Source Interconnected Distribution Network and Diversified Power Consumption in Energy Internet, No. 5210A0180004).
amount of high frequency components. When it is filtered by the inertial characteristics of the filter inductor, the output voltage vector forms a loop, as shown in Fig. 7d. Fig. 10 illustrates the change of output current harmonics distortion rate under different loads. Here, load resistor R1 ~ R5 represent 40 Ω, 30 Ω, 20 Ω, 12 Ω, and 6 Ω respectively. When a larger load is used, e.g., higher neutral point voltage fluctuation, current THD of TSV-DPWM increases from 2.0% to 8.0%, while DSV-DPWM keeps under 1.8%. In addition, current THD of DSV-DPWM is stabilized at 0.02 s, which is about 0.005 s faster than that of TSV-DPWM. This indicates that DSVDPWM can maintain a satisfactory sinusoidal output under DC voltage fluctuations.
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6. Hardware experiment In order to validate the implementation feasibility of the proposed approach, a hardware experiment of the three-level NPC inverter using digital signal processor (DSP) (TMS320F28335) controller is carried out. Table 7 shows the system parametersof hardware experiment. Fig. 11 illustrates the output voltage and current of inverter under light load (load resistance R1). Here, DC voltage fluctuation is small (about 10 V). The harmonics distortion rate of output current of TSVDPWM and DSV-DPWM is 2.45% and 2.41%, respectively. However, when load increases (load resistance R4), DC voltage fluctuation reaches about 63 V. The output current harmonics distortion of TSVDPWM increases to 5.36% while DSV-DPWM just slightly grows to 2.59%, as shown in Fig. 11. Table 8 gives the variation of output current distortion rate of two strategies under different load conditions. When they have the same load, the current THD of TSV-DPWM is higher than DSV-DPWM. When the load increases, the current THD of DSV-DPWM changes slightly, but the current THD of TSV-DPWM increases significantly. Moreover, Table 9 compares the modulation efficiency between CSVPWM and DSV-DPWM. Here, Pi and Po represent the input and output power, respectively. It is obvious that the efficiency of DSV-DPWM is around 0.5% higher than that of CSVPWM. 7. Conclusions In this paper, a novel DSV-DPWM is proposed which can provide great robustness to NPPF in three-level NPC inverter. The main finds/ contributions can be summarized as (1) Real-time dynamic space vector and accurate reference vector synthesis are obtained by detecting the upper and lower capacitance voltage of inverter; 8
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