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Effect of interfacial InZnO conducting layer on electrical performance and bias stress stability of InAlZnO thin-film transistors
Microelectronic Engineering 215 (2019) 111006
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Research paper
Effect of interfacial InZnO conducting layer on electrical performance and bias stress stability of InAlZnO thin-film transistors
T
Kyoungwan Wooa, Se Hyeong Leea, Sanghyun Leeb, So-Young Baka, Yoo-Jong Kima, ⁎ Moonsuk Yia, a b
Department of Electronics Engineering, Pusan National University, Busan 46241, Republic of Korea Department of Smart Hybrid Engineering, Pusan National University, Busan 46241, Republic of Korea
A R T I C LE I N FO
A B S T R A C T
Keywords: Amorphous oxide semiconductor Thin-film transistor InAlZnO Conducting layer Stability
InAlZnO (IAZO) thin-film transistors (TFTs) containing an InZnO (IZO) conducting layer at the interface between the IAZO channel layer and the gate insulator layer were fabricated. The electrical characteristics and bias stress stability of the IAZO/IZO TFTs were examined as functions of the thickness of the interfacial IZO conducting layer (which was set as 1, 2, and 3 nm), and optimal performance of the TFTs was achieved when the thickness was 2 nm. The optimized IAZO/IZO TFT showed a saturation mobility of 52.6 cm2/V·s, which is superior to that of a pristine IAZO TFT (29.8 cm2/V·s). Furthermore, the threshold voltage shifts under positive and negative bias stress conditions simultaneously improved from +2.1 V to +1.0 V and from −1.1 V to −1.0 V, respectively. IAZO/IZO interfaces were analyzed by X-ray photoelectron spectroscopy to elucidate the cause of the improved device characteristics.
1. Introduction
2. Experimental details
Amorphous oxide semiconductor (AOS)-based thin-film transistors (TFTs) have been used in active-matrix organic light-emitting diodes, liquid crystal displays, and flexible displays because of their higher mobility, higher transmittance in the visible range, large size scalability, and lower processing temperature than conventional amorphous‑silicon-based TFTs [1,2]. Among the available AOS materials, InGaZnO is the most commonly used material because of its high mobility and carrier concentration controllability [3,4]. Several studies have been conducted on other types of AOS materials, such as InZnO (IZO) incorporated with Ge, Ti, or Al [5–7]. In particular, the role of Al as a carrier suppressor has often been investigated by researchers, and Al is much less costly than Ga [8,9]. Thus, replacement of Ga with Al would provide competitive advantages in the display industry. Advances in display technology have led to a demand for high-mobility TFTs. Herein, we propose fabrication of a TFT by inserting an IZO conducting layer at the interface between an InAlZnO (IAZO) channel layer and a gate insulator layer to simultaneously achieve improved gate bias stress stability and saturation mobility.
Fig. 1(a) shows a cross-sectional schematic of the fabricated IAZO/ IZO TFT. TFTs with 1-, 2-, and 3-nm-thick IZO conducting layers fabricated using a p-type crystalline Si substrate coated with a 150 nm SiO2 layer grown by thermal oxidation. The interfacial IZO conducting layer was deposited by RF magnetron sputtering using an IZO (In2O3:ZnO = 60:40 (wt%), 99.99% purity) target at a power of 50 W. The initial pressure of the chamber was 4 × 10−4 Pa, and the process pressure was 0.267 Pa. The interfacial IZO conducting layer was deposited without O2 flow. The IAZO active layer was deposited using the IZO target and an Al2O3 (99.99% purity) target by RF magnetron cosputtering. The target powers of IZO and Al2O3 were 50 W and 10 W, respectively. In the deposition of IAZO, the [O2]/[Ar + O2] flow rate ratio was fixed at 5%. The initial and process pressures for IAZO deposition were identical to those for the deposition of the interfacial IZO conducting layer. The channels were deposited at room temperature, and the total channel thickness was 20 nm. After channel deposition, 100 nm Al electrodes were deposited by thermal evaporation. The channel width and length were 1000 μm and 50 μm, respectively. The fabricated TFTs were annealed in air for 1 h at 240 °C. In the fabrication of the IAZO TFT, all the processes were the same except that the interfacial IZO conducting layer was not deposited, as shown in Fig. 1(b).
⁎
Corresponding author. E-mail address: [email protected] (M. Yi).
https://doi.org/10.1016/j.mee.2019.111006 Received 8 May 2019; Received in revised form 20 May 2019; Accepted 21 May 2019 Available online 23 May 2019 0167-9317/ © 2019 Elsevier B.V. All rights reserved.
Microelectronic Engineering 215 (2019) 111006
K. Woo, et al.
Fig. 1. Cross-sectional schematics of (a) IAZO/IZO TFT and (b) IAZO TFT.
Fig. 2. (a) Transfer characteristic curves of TFTs with different channel-layer structures and (b) enlarged view of curves in red-dotted rectangular region in (a). (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)
3. Results and discussion
vacancies (VO), respectively [10,11]. Because the interfacial IZO conducting layer was deposited under oxygen-poor conditions, the ratio of OH to the total-binding-energy area (OTotal) in the XPS spectra in Fig. 3(b) was higher than that in Fig. 3(a). Because an increase in the VO atomic ratio indicates an increase in the channel carrier concentration [12,13], the carrier concentration in the channel layer at a depth of 18 nm was higher than that of channel layer at a depth of 3 nm. Fig. 3(c) shows the OH/OTotal ratio as a function of the channel depth. The carrier concentration in the channel layer increased drastically as the distance of the channel from the channel–interface reduced. The interfacial IZO conducting layer provided a carrier pathway with a higher electron concentration and led to improvements in μsat and Ion/ Ioff. However, there was a limitation on these improvements. The high electron concentration around the gate insulator of the IAZO/IZO (3 nm) TFT resulted in an increase in the off-current, as seen in the transfer characteristic curve of the IAZO/IZO (3 nm) TFT in Fig. 2. The bias stress stability of the TFTs was examined by positive bias stress (PBS) and negative bias stress (NBS) tests. PBS and NBS were applied for 3600 s each with VGS of +10 V and −10 V, respectively. The results of the PBS and NBS tests are summarized in Table 2 and shown in Fig. 4. From Table 2 and Fig. 4, we can conclude that the interfacial IZO conducting layer improved the bias stress stability under both the bias stress conditions. The VTH instability under the PBS condition degrades when the carrier concentration near the interface area increases, because this instability is known to be caused mainly by electron trapping at the interface between the channel layer and the insulator layer [14,15]. However, in this study, the IAZO/IZO TFTs showed improved VTH stability under the PBS condition despite the high carrier concentration around the interfacial IZO conducting layer. On the basis of the carrier trapping model, the improvement in the stability of the IAZO TFTs under PBS is explained by a decrease in the number of interfacial trap sites in the IAZO TFT upon the insertion of the interfacial IZO conducting layer which contains high electron concentration. It is proposed that the numerous electrons in the
Fig. 2 shows the transfer characteristic curves of the IAZO TFT and IAZO/IZO TFTs. For comparison, the figure also includes the corresponding curves of a single IZO conducting channel (20 nm) TFT, which behaves almost as a conductor. We measured these curves by sweeping the gate voltage (VGS) from −20 V to +20 V at a fixed drain voltage (VDS) of +20 V by means of a semiconductor parameter analyzer. Compared to the IAZO TFT, the IAZO/IZO TFTs mostly showed improved saturation mobility (μsat), a higher on/off current ratio (Ion/Ioff), and a lower threshold voltage (VTH), the exception being the IAZO/IZO (3 nm) TFT, whose off-current was remarkably high. Table 1 summarizes the electrical parameters of the IAZO/IZO TFTs and IAZO TFT, including their μsat, VTH, Ion/Ioff, and subthreshold swing (SS); the IAZO/IZO (2 nm) TFT exhibited the best electrical performance among all the TFTs. To investigate the effect of the interfacial IZO conducting layer on the IAZO TFT performance, we performed X-ray photoelectron spectroscopy (XPS) analysis of the IAZO/IZO (2 nm) TFT. As shown in Fig. 3(a) and (b), the O (1 s) spectra were deconvoluted into two different peaks, which were centered at 529.5 ± 0.1 eV and 530.5 ± 0.1 eV. The lower-binding-energy area (OL) in red and the higher-binding-energy area (OH) in blue correspond to lattice oxygen related to metal–oxide bonds and the metal oxide lattice with oxygen
Table 1 Electrical parameters of IAZO TFT and IAZO/IZO TFTs. Electrical parameter
IAZO
IAZO/IZO (1 nm)
IAZO/IZO (2 nm)
IAZO/IZO (3 nm)
μsat [cm2/V·s] VTH [V] Ion/Ioff SS [V/dec]
29.8 3.7 5.6 × 106 0.8
34.8 3.4 7.2 × 106 0.8
52.6 3.4 1.2 × 107 0.8
35.3 1.6 1.3 × 106 1.2
2
Microelectronic Engineering 215 (2019) 111006
K. Woo, et al.
Fig. 3. O (1 s) XPS spectra at depths of (a) 3 nm and (b) 18 nm and (c) OH/OTotal ratio for IAZO/IZO (2 nm) TFT as a function of channel depth.
condition decreased with increasing thickness of the IZO conducting layer. The VTH instability under the NBS condition is attributed to the interaction between holes which are minority carriers of the channel layer and the VO near the interface between the channel layer and the insulator layer. The VO near the interface are ionized by holes accumulated near to the interface under NBS and release electrons (VO + h+ → VO1+ + e− or VO + 2 h+ → VO2+ + 2 e−). The electron concentration in the channel layer increases because of the liberated electrons, which causes negative shifts of VTH. The interfacial IZO conducting layer has a higher electron concentration than the IAZO layer, which implies that the former has a smaller hole concentration than the latter. The hole concentration around the interface decreased upon the insertion of the interfacial IZO conducting layer, which led to an improvement in the VTH stability under the NBS condition.
Table 2 VTH shifts of IAZO TFT and IAZO/IZO TFTs after PBS and NBS tests for 3600 s each. VTH shifts [V]
IAZO
IAZO/IZO (1 nm)
IAZO/IZO (2 nm)
IAZO/IZO (3 nm)
PBS NBS
+2.1 −1.1
+1.6 −1.1
+1.0 −1.0
+0.6 −0.8
interfacial IZO conducing layer had already occupied the interfacial trap sites that cause the VTH instability under PBS by capturing electrons in the channel layer and decrease in number of unoccupied interfacial trap sites led to enhanced PBS stability. Another study similarly reported that the insertion of an interfacial InSnO conducting layer, having high conductivity, led to a decrease in the number of total defect sites in the InSnZnO TFT [16]. The NBS stability of the IAZO/IZO TFTs was also slightly improved. The VTH shifts under the NBS
Fig. 4. Transfer characteristic curves of (a), (c) IAZO and (b), (d) IAZO/IZO (2 nm) TFTs under (a), (b) PBS (VGS = +10 V) and (c), (d) NBS (VGS = −10 V). 3
Microelectronic Engineering 215 (2019) 111006
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4. Conclusion
(2004) 488–492, https://doi.org/10.1038/nature03090. [2] H. Yabuta, M. Sano, K. Abe, T. Aiba, T. Den, H. Kumomi, K. Nomura, T. Kamiya, H. Hosono, Appl. Phys. Lett. 89 (2006) 112123, , https://doi.org/10.1063/1. 2353811. [3] S.Y. Lee, S. Chang, J.S. Lee, Thin Solid Films 518 (2010) 3030–3032, https://doi. org/10.1016/j.tsf.2009.09.165. [4] D.H. Lee, S.M. Park, D.K. Kim, Y.S. Lim, M.S. Yi, J. Semicond. Technol. Sci. 14 (2) (2014) 163–168, https://doi.org/10.5573/JSTS.2014.14.2.163. [5] Y.J. Im, S.J. Kim, J.H. Shin, S.S. Ha, C.H. Park, M. Yi, J. Nanosci. Nanotechnol. 15 (2015) 7537–7541, https://doi.org/10.1166/jnn.2015.11156. [6] C. Park, Y. Lim, S. Ha, Y. Im, M. Jang, S. Choi, J. Park, M.S. Yi, J. SID 23 (2015) 371–376, https://doi.org/10.1002/jsid.321. [7] J. Sun, W. Yang, Y. Huang, W.S. Lai, A.Y.S. Lee, C.F. Wang, H. Gong, J. Appl. Phys. 112 (2012) 083709, , https://doi.org/10.1063/1.4758383. [8] J. Sun, Y. Huang, H. Gong, J. Appl. Phys. 110 (2011) 023709, , https://doi.org/10. 1063/1.3605547. [9] J. Park, Y. Lim, M. Jang, S. Choi, N. Hwang, M. Yi, Mater. Res. Bull. 96 (2017) 155–159, https://doi.org/10.1016/j.materresbull.2017.05.001. [10] M. Chen, Z.L. Pei, C. Sun, L.S. Wen, X. Wang, J. Cryst. Growth 220 (2000) 254–262, https://doi.org/10.1016/S0022-0248(00)00834-4. [11] C. Donley, D. Dunphy, D. Paine, C. Carter, K. Nebesny, P. Lee, D. Alloway, N.R. Armstrong, Langmuir 2002 (18) (2002) 450–457, https://doi.org/10.1021/ la011101t. [12] T.H. Jung, J.S. Park, D.H. Kim, Y. Jeong, S.G. Park, J.D. Kwon, J. Vac. Sci. Technol. A 31 (2013) 01A124, , https://doi.org/10.1116/1.4767813. [13] K. Nomura, T. Kamiya, E. Ikenaga, H. Yanagi, K. Kobayashi, H. Hosono, J. Appl. Phys. 109 (2011) 073726, , https://doi.org/10.1063/1.3560769. [14] M.J. Powell, IEEE Trans. Electron Devices 36 (12) (1989) 2753–2763, https://doi. org/10.1109/16.40933. [15] I.T. Cho, J.M. Lee, J.H. Lee, H.I. Kwon, Semicond. Sci. Technol. 24 (2009) 015013, , https://doi.org/10.1088/0268-1242/24/1/015013. [16] C.P.T. Nguyen, J. Raja, S. Kim, K. Jang, A.H.T. Le, Y.J. Lee, J. Yi, Appl. Surf. Sci. 396 (2017), https://doi.org/10.1016/j.apsusc.2016.11.194 1472–1447.
We investigated the electrical performance and bias stress stability of a pristine IAZO TFT and IAZO/IZO TFTs with 1-, 2-, and 3-nm-thick IZO layers. The optimal thickness of the interfacial IZO conducting layer was 2 nm, and the IAZO/IZO (2 nm) TFT showed μsat of 52.6 cm2/ V·s, VTH of 3.36 V, Ion/Ioff of 1.2 × 107, and SS of 0.81 V/dec. We performed XPS analysis of the channel layer of the IAZO/IZO (2 nm) TFT and found that the OH/OTotal ratio of this channel layer increased drastically near the channel–insulator interface. The high electron concentration in the IZO conducting layer led to enhancements of μsat and Ion/Ioff of the IAZO/IZO TFTs; the insertion of this layer also resulted in a simultaneous improvement in the bias stress stability under the PBS and NBS conditions. Funding This study was supported by BK21PLUS, Creative Human Resource Development Program for IT Convergence. This study was also supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No. 2017R1A2B4007526). Declaration of interest The authors report no conflicts of interest. The authors alone are responsible for the content and writing of this article. References [1] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, H. Hosono, Nature 432
4
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Research paper
Effect of interfacial InZnO conducting layer on electrical performance and bias stress stability of InAlZnO thin-film transistors
T
Kyoungwan Wooa, Se Hyeong Leea, Sanghyun Leeb, So-Young Baka, Yoo-Jong Kima, ⁎ Moonsuk Yia, a b
Department of Electronics Engineering, Pusan National University, Busan 46241, Republic of Korea Department of Smart Hybrid Engineering, Pusan National University, Busan 46241, Republic of Korea
A R T I C LE I N FO
A B S T R A C T
Keywords: Amorphous oxide semiconductor Thin-film transistor InAlZnO Conducting layer Stability
InAlZnO (IAZO) thin-film transistors (TFTs) containing an InZnO (IZO) conducting layer at the interface between the IAZO channel layer and the gate insulator layer were fabricated. The electrical characteristics and bias stress stability of the IAZO/IZO TFTs were examined as functions of the thickness of the interfacial IZO conducting layer (which was set as 1, 2, and 3 nm), and optimal performance of the TFTs was achieved when the thickness was 2 nm. The optimized IAZO/IZO TFT showed a saturation mobility of 52.6 cm2/V·s, which is superior to that of a pristine IAZO TFT (29.8 cm2/V·s). Furthermore, the threshold voltage shifts under positive and negative bias stress conditions simultaneously improved from +2.1 V to +1.0 V and from −1.1 V to −1.0 V, respectively. IAZO/IZO interfaces were analyzed by X-ray photoelectron spectroscopy to elucidate the cause of the improved device characteristics.
1. Introduction
2. Experimental details
Amorphous oxide semiconductor (AOS)-based thin-film transistors (TFTs) have been used in active-matrix organic light-emitting diodes, liquid crystal displays, and flexible displays because of their higher mobility, higher transmittance in the visible range, large size scalability, and lower processing temperature than conventional amorphous‑silicon-based TFTs [1,2]. Among the available AOS materials, InGaZnO is the most commonly used material because of its high mobility and carrier concentration controllability [3,4]. Several studies have been conducted on other types of AOS materials, such as InZnO (IZO) incorporated with Ge, Ti, or Al [5–7]. In particular, the role of Al as a carrier suppressor has often been investigated by researchers, and Al is much less costly than Ga [8,9]. Thus, replacement of Ga with Al would provide competitive advantages in the display industry. Advances in display technology have led to a demand for high-mobility TFTs. Herein, we propose fabrication of a TFT by inserting an IZO conducting layer at the interface between an InAlZnO (IAZO) channel layer and a gate insulator layer to simultaneously achieve improved gate bias stress stability and saturation mobility.
Fig. 1(a) shows a cross-sectional schematic of the fabricated IAZO/ IZO TFT. TFTs with 1-, 2-, and 3-nm-thick IZO conducting layers fabricated using a p-type crystalline Si substrate coated with a 150 nm SiO2 layer grown by thermal oxidation. The interfacial IZO conducting layer was deposited by RF magnetron sputtering using an IZO (In2O3:ZnO = 60:40 (wt%), 99.99% purity) target at a power of 50 W. The initial pressure of the chamber was 4 × 10−4 Pa, and the process pressure was 0.267 Pa. The interfacial IZO conducting layer was deposited without O2 flow. The IAZO active layer was deposited using the IZO target and an Al2O3 (99.99% purity) target by RF magnetron cosputtering. The target powers of IZO and Al2O3 were 50 W and 10 W, respectively. In the deposition of IAZO, the [O2]/[Ar + O2] flow rate ratio was fixed at 5%. The initial and process pressures for IAZO deposition were identical to those for the deposition of the interfacial IZO conducting layer. The channels were deposited at room temperature, and the total channel thickness was 20 nm. After channel deposition, 100 nm Al electrodes were deposited by thermal evaporation. The channel width and length were 1000 μm and 50 μm, respectively. The fabricated TFTs were annealed in air for 1 h at 240 °C. In the fabrication of the IAZO TFT, all the processes were the same except that the interfacial IZO conducting layer was not deposited, as shown in Fig. 1(b).
⁎
Corresponding author. E-mail address: [email protected] (M. Yi).
https://doi.org/10.1016/j.mee.2019.111006 Received 8 May 2019; Received in revised form 20 May 2019; Accepted 21 May 2019 Available online 23 May 2019 0167-9317/ © 2019 Elsevier B.V. All rights reserved.
Microelectronic Engineering 215 (2019) 111006
K. Woo, et al.
Fig. 1. Cross-sectional schematics of (a) IAZO/IZO TFT and (b) IAZO TFT.
Fig. 2. (a) Transfer characteristic curves of TFTs with different channel-layer structures and (b) enlarged view of curves in red-dotted rectangular region in (a). (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)
3. Results and discussion
vacancies (VO), respectively [10,11]. Because the interfacial IZO conducting layer was deposited under oxygen-poor conditions, the ratio of OH to the total-binding-energy area (OTotal) in the XPS spectra in Fig. 3(b) was higher than that in Fig. 3(a). Because an increase in the VO atomic ratio indicates an increase in the channel carrier concentration [12,13], the carrier concentration in the channel layer at a depth of 18 nm was higher than that of channel layer at a depth of 3 nm. Fig. 3(c) shows the OH/OTotal ratio as a function of the channel depth. The carrier concentration in the channel layer increased drastically as the distance of the channel from the channel–interface reduced. The interfacial IZO conducting layer provided a carrier pathway with a higher electron concentration and led to improvements in μsat and Ion/ Ioff. However, there was a limitation on these improvements. The high electron concentration around the gate insulator of the IAZO/IZO (3 nm) TFT resulted in an increase in the off-current, as seen in the transfer characteristic curve of the IAZO/IZO (3 nm) TFT in Fig. 2. The bias stress stability of the TFTs was examined by positive bias stress (PBS) and negative bias stress (NBS) tests. PBS and NBS were applied for 3600 s each with VGS of +10 V and −10 V, respectively. The results of the PBS and NBS tests are summarized in Table 2 and shown in Fig. 4. From Table 2 and Fig. 4, we can conclude that the interfacial IZO conducting layer improved the bias stress stability under both the bias stress conditions. The VTH instability under the PBS condition degrades when the carrier concentration near the interface area increases, because this instability is known to be caused mainly by electron trapping at the interface between the channel layer and the insulator layer [14,15]. However, in this study, the IAZO/IZO TFTs showed improved VTH stability under the PBS condition despite the high carrier concentration around the interfacial IZO conducting layer. On the basis of the carrier trapping model, the improvement in the stability of the IAZO TFTs under PBS is explained by a decrease in the number of interfacial trap sites in the IAZO TFT upon the insertion of the interfacial IZO conducting layer which contains high electron concentration. It is proposed that the numerous electrons in the
Fig. 2 shows the transfer characteristic curves of the IAZO TFT and IAZO/IZO TFTs. For comparison, the figure also includes the corresponding curves of a single IZO conducting channel (20 nm) TFT, which behaves almost as a conductor. We measured these curves by sweeping the gate voltage (VGS) from −20 V to +20 V at a fixed drain voltage (VDS) of +20 V by means of a semiconductor parameter analyzer. Compared to the IAZO TFT, the IAZO/IZO TFTs mostly showed improved saturation mobility (μsat), a higher on/off current ratio (Ion/Ioff), and a lower threshold voltage (VTH), the exception being the IAZO/IZO (3 nm) TFT, whose off-current was remarkably high. Table 1 summarizes the electrical parameters of the IAZO/IZO TFTs and IAZO TFT, including their μsat, VTH, Ion/Ioff, and subthreshold swing (SS); the IAZO/IZO (2 nm) TFT exhibited the best electrical performance among all the TFTs. To investigate the effect of the interfacial IZO conducting layer on the IAZO TFT performance, we performed X-ray photoelectron spectroscopy (XPS) analysis of the IAZO/IZO (2 nm) TFT. As shown in Fig. 3(a) and (b), the O (1 s) spectra were deconvoluted into two different peaks, which were centered at 529.5 ± 0.1 eV and 530.5 ± 0.1 eV. The lower-binding-energy area (OL) in red and the higher-binding-energy area (OH) in blue correspond to lattice oxygen related to metal–oxide bonds and the metal oxide lattice with oxygen
Table 1 Electrical parameters of IAZO TFT and IAZO/IZO TFTs. Electrical parameter
IAZO
IAZO/IZO (1 nm)
IAZO/IZO (2 nm)
IAZO/IZO (3 nm)
μsat [cm2/V·s] VTH [V] Ion/Ioff SS [V/dec]
29.8 3.7 5.6 × 106 0.8
34.8 3.4 7.2 × 106 0.8
52.6 3.4 1.2 × 107 0.8
35.3 1.6 1.3 × 106 1.2
2
Microelectronic Engineering 215 (2019) 111006
K. Woo, et al.
Fig. 3. O (1 s) XPS spectra at depths of (a) 3 nm and (b) 18 nm and (c) OH/OTotal ratio for IAZO/IZO (2 nm) TFT as a function of channel depth.
condition decreased with increasing thickness of the IZO conducting layer. The VTH instability under the NBS condition is attributed to the interaction between holes which are minority carriers of the channel layer and the VO near the interface between the channel layer and the insulator layer. The VO near the interface are ionized by holes accumulated near to the interface under NBS and release electrons (VO + h+ → VO1+ + e− or VO + 2 h+ → VO2+ + 2 e−). The electron concentration in the channel layer increases because of the liberated electrons, which causes negative shifts of VTH. The interfacial IZO conducting layer has a higher electron concentration than the IAZO layer, which implies that the former has a smaller hole concentration than the latter. The hole concentration around the interface decreased upon the insertion of the interfacial IZO conducting layer, which led to an improvement in the VTH stability under the NBS condition.
Table 2 VTH shifts of IAZO TFT and IAZO/IZO TFTs after PBS and NBS tests for 3600 s each. VTH shifts [V]
IAZO
IAZO/IZO (1 nm)
IAZO/IZO (2 nm)
IAZO/IZO (3 nm)
PBS NBS
+2.1 −1.1
+1.6 −1.1
+1.0 −1.0
+0.6 −0.8
interfacial IZO conducing layer had already occupied the interfacial trap sites that cause the VTH instability under PBS by capturing electrons in the channel layer and decrease in number of unoccupied interfacial trap sites led to enhanced PBS stability. Another study similarly reported that the insertion of an interfacial InSnO conducting layer, having high conductivity, led to a decrease in the number of total defect sites in the InSnZnO TFT [16]. The NBS stability of the IAZO/IZO TFTs was also slightly improved. The VTH shifts under the NBS
Fig. 4. Transfer characteristic curves of (a), (c) IAZO and (b), (d) IAZO/IZO (2 nm) TFTs under (a), (b) PBS (VGS = +10 V) and (c), (d) NBS (VGS = −10 V). 3
Microelectronic Engineering 215 (2019) 111006
K. Woo, et al.
4. Conclusion
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We investigated the electrical performance and bias stress stability of a pristine IAZO TFT and IAZO/IZO TFTs with 1-, 2-, and 3-nm-thick IZO layers. The optimal thickness of the interfacial IZO conducting layer was 2 nm, and the IAZO/IZO (2 nm) TFT showed μsat of 52.6 cm2/ V·s, VTH of 3.36 V, Ion/Ioff of 1.2 × 107, and SS of 0.81 V/dec. We performed XPS analysis of the channel layer of the IAZO/IZO (2 nm) TFT and found that the OH/OTotal ratio of this channel layer increased drastically near the channel–insulator interface. The high electron concentration in the IZO conducting layer led to enhancements of μsat and Ion/Ioff of the IAZO/IZO TFTs; the insertion of this layer also resulted in a simultaneous improvement in the bias stress stability under the PBS and NBS conditions. Funding This study was supported by BK21PLUS, Creative Human Resource Development Program for IT Convergence. This study was also supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No. 2017R1A2B4007526). Declaration of interest The authors report no conflicts of interest. The authors alone are responsible for the content and writing of this article. References [1] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, H. Hosono, Nature 432
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