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Negative bias illumination stress instability in amorphous InGaZnO thin film transistors with ITO local conducting buried layer
MR-12437; No of Pages 6 Microelectronics Reliability xxx (2016) xxx–xxx
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Negative bias illumination stress instability in amorphous InGaZnO thin film transistors with ITO local conducting buried layer Sang Min Kim a, Min-Soo Kang b, Won-Ju Cho b, Jong Tae Park a,⁎ a b
Dept. of Electronics Eng., Incheon National Univ., Incheon 406-772, Republic of Korea Dept. of Electronic Materials Eng., Kwangwoon Univ., Seoul 139-701, Republic of Korea
a r t i c l e
i n f o
Article history: Received 12 May 2017 Received in revised form 31 May 2017 Accepted 13 June 2017 Available online xxxx Keywords: InGaZnO thin film transistor Negative bias illumination stress ITO conducting layer
a b s t r a c t The investigations on the device instabilities of amorphous InGaZnO thin film transistors (a-IGZO TFTs) with ITO local conducting buried layer (LCBL) under the source/drain region and in the middle of the active channel region have been performed under negative bias and illumination stress. From the increased drain current of a-IGZO with ITO LCBL, one can control the drive current by modulating the length of ITO LCBL without changing the ratio of channel width and length. The reason for the less degradation of a-IGZO TFTs with LCBL under negative bias stress than that of device without LCBL was explained by the fact that ITO LCBL could act to reduce the effective energy barrier and act as a hole damping layer. However, the device degradation of a-IGZO with ITO LCBL under negative bias and illumination stress was more significant than that of one without LCBL due to the electron hole pair generation in ITO layer under illumination. © 2016 Elsevier Ltd. All rights reserved.
1. Introduction Due to the wide band gap and the excellent electronic properties compared to amorphous Si thin film transistors, amorphous InGaZnO thin film transistors (a-IGZO TFTs) have been extensively studied for the applications in next-generation display devices. Currently the applications of a-IGZO TFTs have been extended to the logic circuits, RAM (Random Access Memory), 3-D stacking memory, and BEOL (Back End of Line) transistors for PMIC (Power Management IC) [1–5]. For the applications in display and electronic devices, the extensive studies for better device performances are required including high electron mobility and high On/Off current ratio. Accordingly, many studies on various heat treatments, high-K dielectric materials, engineered stacked gate dielectric layers, and advanced device structures have been suggested [6–9]. Especially, the experimental studies on the device characterization of a-IGZO TFTs with ITO local conducting buried extended layer under both source and drain regions, and in the middle of channel region have been reported to enhance the electron mobility and high On/Off current ratio [10–12]. By introducing optimized thin ITO layer (5 nm) between the gate insulator and InGaZnO channel, the reduction of threshold voltage shifts has been reported [13]. In spite of these advantages, the device instability caused by gate bias and illumination during display panel operation is the prime concern. For display devices, the light induced device instability of a-IGZO under negative gate bias illumination stress (NBIS) condition is more important because the turn⁎ Corresponding author. E-mail address: [email protected] (J.T. Park).
off time of device is longer than turn on time. Although the enhanced device performances of a-IGZO TFTs with ITO local conducting buried extended layer under both source and drain regions, and in the middle of channel region have been reported, the device instabilities have not been investigated in depth. In this work, the device instabilities of a-IGZO TFTs according to the different length of ITO LCBL under both source and drain regions (aIGZO TFTs with LCBL-S/D) and in the middle of channel region (aIGZO TFTs with LBCL-C) have been investigated under negative bias stress (NBS) and NBIS. 2. Device fabrication a-IGZO TFTs with LCBL have been fabricated using a p-type (100) silicon wafer substrate grown on thermal oxide (SiO2) having a resistivity of 10 Ω·cm. After RCA cleaning, a 30 nm thick of ITO was deposited to form LCBL using the RF magnetron sputtering method (Ar flow of 20 sccm, working pressure of 3 mTorr). The thickness of ITO (TITO) was ranged from 10 nm to 40 nm for a-IGZO TFTs with LCBL-S/D. According to the different device structures of a-IGZO with LCBL-S/D and LCBL-C, the patterning of LCBLs was carried out by using a conventional photo-lithography and chemical etching in an ITO etchant. To form the active region, a 50 nm thick of InGaZnO layer (In2O3:Ga2O3:ZnO = 1:1:1 mol%) was deposited using the RF sputtering method with an Ar flow of 20 sccm, working pressure of 6 mTorr and an RF power of 100 W at room temperature. The IGZO layer was then patterned by photo-lithography and etched using a buffered oxide etchant (BOE 30:1). After the patterning of active layer, a microwave annealing was
http://dx.doi.org/10.1016/j.microrel.2017.06.020 0026-2714/© 2016 Elsevier Ltd. All rights reserved.
Please cite this article as: S.M. Kim, et al., Negative bias illumination stress instability in amorphous InGaZnO thin film transistors with ITO local conducting buried layer, Microelectronics Reliability (2016), http://dx.doi.org/10.1016/j.microrel.2017.06.020
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S.M. Kim et al. / Microelectronics Reliability xxx (2016) xxx–xxx
conducted at a frequency of 2.45 GHz and a power of 1 kW for 2 min to remove the defects in InGaZnO layer and at the interface between active layer and gate dielectric layer. Subsequently, a 100 nm thick ITO and 20 nm thick Ti/130 nm thick Al were deposited for the source and drain electrodes of a-IGZO TFTs with LCBL-S/D and a-IGZO TFTs with LCBL-C, respectively. The channel width (W) and length (L) of a-IGZO TFTs with LCBL-S/D were 20 μm and 10 μm, respectively. The space distance (DITO) between ITO LCBL under the source and drain regions were ranged from 2 μm to 10 μm. In evaluating the effect of DITO on device instability under NBIS, the reference device without ITO LCBL was also fabricated using the same process. The W and L of a-fabricated a-IGZO TFTs with LCBL-C were 160 μm and 100 μm, respectively. The length of ITO buried layer in the middle of channel region (LITO) was split into 20, 40, 60, and 80 μm with constant channel width of 80 μm. To evaluate the effect of LITO on device instability, the reference device without ITO LCBL was also fabricated using the same process. Fig. 1 shows the schematic diagrams of fabricated a-IGZO TFTs with LCBL-S/D and a-IGZO TFTs with LCBL-C. The electrical characteristics were measured with the use of a semiconductor parameter analyzer and all measurements were performed in a dark box in order to avoid light or external influence.
3. Results and discussion
Fig. 1. Schematic diagrams of (a) a-IGZO TFTs with LCBL-S/D and (b) a-IGZO TFTs with LCBL-C.
From the transfer curves of the fabricated a-IGZO TFTs with LCBL-S/D and LCBL-C as shown in Figs. 2 and 3, one can observe that ON currents of a-IGZO TFTs with LCBL-S/D and LCBL-C increase with the decrease of
Fig. 2. Transfer curves of a-IGZO TFTs with LCBL-S/D.
Fig. 3. Transfer curves of a-IGZO TFTs with LCBL-C.
Please cite this article as: S.M. Kim, et al., Negative bias illumination stress instability in amorphous InGaZnO thin film transistors with ITO local conducting buried layer, Microelectronics Reliability (2016), http://dx.doi.org/10.1016/j.microrel.2017.06.020
S.M. Kim et al. / Microelectronics Reliability xxx (2016) xxx–xxx
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Table 1 Summary of device performance parameters at dark condition. Dark a-IGZO TFT with LCBL-S/D a-IGZO TFT with LCBL-C
Ref DITO = 2[μm] Ref LITO = 80[μm]
VTH (V)
S (V/dec)
μ (cm2/V·s)
ION (A)
IOFF (A)
ION/IOFF
2.3 1.8 2.2 1.8
0.36 0.23 0.34 0.21
13.3 67.4 10.4 44.3
2.9E − 5 1.5E − 4 2.4E − 5 1.1E − 4
6.3E − 12 4.6E − 12 1.1E − 11 5.3E − 12
4.6E + 6 3.2E + 7 2.2E + 6 2.1E + 7
DITO and the increase of LITO, respectively. This is due to the decrease of overall series resistance by enhancing the conductivity of the inner channel layer [12] and due to reduce the effective channel length. The summary of measured device performance parameters was shown in Table 1. It is worth noting that the field effect mobility (μFE) of a-IGZO without LCBL-S/D is noticeably enhanced from 14.2 cm2/V·s to 69.4 cm2/V·s when the LCBL with DITO = 2 μm is embedded. The measured VTH was defined as the VGS required to reach a drain current of 2.5 μA ∗ L/W[μA] at VDS = 2.0 V and the μFE was determined from following equation.
μ FE ¼
Lgm ∂IDS ; gm ¼ VDS ¼ const WCox VDS ∂VGS
ð1Þ
The On/Off current ratio is also increased from 6.5 × 106 to 4.8 × 107. When the LCBL with LITO = 80 μm is embedded, the μFE of a-IGZO without LCBL-C is enhanced from 10.9 cm2/V·s to 44.3 cm2/V·s. The On/Off current ratio is also increased from 2.2 × 106 to 2.1 × 107. The subthreshold characteristics are enhanced with ITO LCBL. The enhancement of μFE can be attributed to the increase of the channel conductance due to the embedded ITO BCBL. Therefore, without changing the ratio of W/L and device structures such as double gate, we can control the drive current of a-IGZO TFTs with modulation of DITO in a-IGZO TFTs with LCBL-S/D or LITO in a-IGZO without LCBL-C.
Fig. 4 shows the evolution of transfer curves as a function of NBS stress time for a-IGZO TFTs without LCBL and with DITO = 2 μm. From the comparison of the transfer curves, it can be seen that the positive shifts of transfer curves with NBS stress time are more significant in aIGZO TFTs without LCBL than in a-IGZO TFTs with DITO = 2 μm. From the time dependence of threshold voltage shifts (|ΔVTH | = |VTH(t) − VTH(t = 0)|) under NBS as shown in Fig. 5, it can be clearly seen that |ΔVTH | is decreased with the decrease of DITO. It means that ITO LCBL can play an important role acting as a hole damping layer or as a protecting layer to reduce the hole injection into the interface between the channel and the gate dielectric layer. Since the negative shift of threshold voltage under NBS is generally accepted due to the hole trapping at the interface between the channel and the gate dielectric layer, the average effective energy barrier (Eτ) that holes in the channel needed to overcome to enter the gate insulator was extracted from fitting the measurement with the commonly used stretchedexponential equation for different DITO [14,15]. From a plot of the characteristic trapping time (τ) as a function of 1/ KT as shown in Fig. 6, Eτ increases as DITO decreases. These results suggest that ITO LCBL may be acting as a protecting layer to reduce the hole injection into the gate insulator. From the energy band diagram of a-IGZO TFT with LCBL at the equilibrium as shown in Fig. 7, ITO one can speculate that LCBL can reduce the hole injection from the active channel into the gate dielectric layer. We also confirmed that Eτ of a-IGZO with LCBL-C increases as LITO increases.
Fig. 5. Time dependences of |ΔVTH | of a-IGZO TFTs with LCBL-S/D under NBS.
Fig. 4. Evolution of transfer curves of (a) a-IGZO TFTs without LCBL and (b) with DITO = 2 μm as a function of NBS stress time.
Fig. 6. τ as a function of 1/KT for a-IGZO TFTs with LCBL-S/D.
Please cite this article as: S.M. Kim, et al., Negative bias illumination stress instability in amorphous InGaZnO thin film transistors with ITO local conducting buried layer, Microelectronics Reliability (2016), http://dx.doi.org/10.1016/j.microrel.2017.06.020
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Fig. 7. Energy band diagram of a-IGZO TFT with LCBL-C at the equilibrium.
Fig. 8. Comparison of electric field distribution for (a) a-IGZO TFTs without LCBL and (b) with DITO = 10 μm.
In order to investigate the electric field distribution of a-IGZO TFTs with LCBL-S/D, the device simulation has been carried out using the 2dimensional SIVACO ATLAS software [16]. The setup is matched with fabricated devices by simulating with the device. To address the effect of LCBL on the device performances, the initial transfer and output characteristics of the referenced device was calibrated using optimization of analytical TFTs models including the sub-bandgap DOS and material properties. From the comparison of the electric field distribution for device without LCBL and with DITO = 10μmas shown in Fig. 8, one can clearly observe that the electric field near the interface between ITO and the channel layer for device with DITO = 10 μm is increased significantly. Therefore, it is believed that the increased field collects more holes and ITO acts as a hole damping layer. Table 2 shows the summary of measured device performance parameters under illumination condition. A white halogen lamp ranging from 500 nm to 700 nm wavelength and with the intensity of IL = 0.22 mW/cm2 was used as a light source. The subthreshold swing S of ITO device was slightly increased under illumination. Due to the increased electron concentration from the electron-hole pair generation under illumination, ION/IOFF and μFE are increased. It has been generally accepted that the negative shift of VT under NBIS is due to the hole trapping at the interface of the gate insulator/
active channel and photoionization of neutral oxygen vacancy (VO) to charged oxygen vacancy (Vo2+) state which exhibits positively charged defects [17–19]. Due to the combination of hole trapping and charged oxygen vacancy, Off current is increased and the stretch-out in the subthreshold characteristics can be observed. Fig. 9 shows the evolution of transfer curves as a function of NBIS stress time for a-IGZO TFTs without LCBL and with DITO = 2 μm. From the comparison of the transfer curves, it can be seen that the negative shifts of transfer curves with stress time are more significant in a-IGZO TFTs with DITO = 2 μm of LCBL than device without LCBL. After NBIS, the subthreshold swing S of a-IGZO TFTs with LCBL-S/D is increased from 0.23 dec/V at dark condition to 0.48 dec/V at illumination condition. With the increase of NBIS time, the hump occurrence resulted from the turn-on of a parasitic transistor is observed more clearly in device with DITO = 2 μm than device without LCBL. The reason may be attributed to the increased electric field for the device with LCBL. The increased electric field leads to more hole accumulation at the interface region between ITO and channel layer. From the time dependence of |ΔVTH | under NBIS as shown in Fig. 10, the |ΔVTH | for a-IGZO TFTs with LCBL-S/D and a-IGZO TFTs with LCBL-C increase as DITO decreases and as LITO increases, respectively. The
Table 2 Summary of device performance parameters at illumination condition. Light a-IGZO TFT with LCBL-S/D a-IGZO TFT with LCBL-C
Ref DITO = 2[μm] Ref LITO = 80[μm]
VTH (V)
S (V/dec)
μ (cm2/V·s)
ION (A)
IOFF (A)
ION/IOFF
2.1 1.6 1.9 1.6
0.38 0.48 0.40 0.43
14.2 69.4 11.8 47.0
2.9E − 5 1.6E − 4 2.5E − 5 1.2E − 4
4.6E − 12 3.3E − 12 4.5E − 12 2.1E − 12
6.3E + 6 4.8E + 7 5.6E + 6 5.7E + 7
Please cite this article as: S.M. Kim, et al., Negative bias illumination stress instability in amorphous InGaZnO thin film transistors with ITO local conducting buried layer, Microelectronics Reliability (2016), http://dx.doi.org/10.1016/j.microrel.2017.06.020
S.M. Kim et al. / Microelectronics Reliability xxx (2016) xxx–xxx
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Fig. 11. Transfer curves of a-IGZO TFTs with LCBL-S/D for different TITO at IL = 0.66 mW/cm2.
transparent [20]. To confirm the photo-generation of electron-hole pairs in ITO layer, the transfer characteristics for different TITO were measured under light illumination (IL = 0.66 mW/cm2). Fig. 11 shows that the negative shifts of transfer curves are more significant with increasing TITO. It indicates that the more electron-hole pairs were generated with increasing TITO. The time dependence of |ΔVTH | for different TITO under NBIS as shown in Fig. 12 indicates also that the more electron-hole pairs in ITO layer were generated as TITO increases. 4. Conclusion Fig. 9. Evolution of transfer curves as a function of NBIS stress time for (a) a-IGZO TFTs without LCBL and (b) with DITO = 2 μm.
increased device degradations in a-IGZO TFTs with ITO LCBL mean that photo-generated holes within ITO layer may be injected into the gate insulator under light illumination although the ITO layer is almost
Due to the enhanced effective mobility, the drain currents of a-IGZO TFTs with ITO LCBL were increased. One can control the drive current by modulating the length of ITO LCBL without changing the ratio of channel width and length or modifying the device structures. The reason for the less degradation of a-IGZO TFTs with ITO LCBL under negative bias stress than that of device without ITO LCBL was explained by the fact that ITO LCBL could act to reduce the effective energy barrier and act as a hole damping layer. However, the device degradations of a-IGZO with ITO LCBL under negative bias and illumination stress were more significant than that of one without LCBL due to the electron hole pair generation in ITO layer under illumination. Therefore, a-IGZO TFTs with ITO LCBL may be better for the application of logic circuits or BEOL transistors than for the display devices. Acknowledgement This work was supported by the Incheon National University Research Grant in 2016.
Fig. 10. Time dependences of |ΔVTH | under NBIS for (a) a-IGZO TFTs with LCBL-S/D (b) aIGZO TFTs with LCBL-C.
Fig. 12. Time dependence of |ΔVTH | under NBIS for (a) a-IGZO TFTs with LCBL-S/D with different TITO.
Please cite this article as: S.M. Kim, et al., Negative bias illumination stress instability in amorphous InGaZnO thin film transistors with ITO local conducting buried layer, Microelectronics Reliability (2016), http://dx.doi.org/10.1016/j.microrel.2017.06.020
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[10] M. Kim, D. Choi, Effects of enhanced-mobility current path on the mobility of AOS TFT, Microelectron. Reliab. 52 (2012) 1346. [11] C. Lim, W. Cho, High performance microwave-annealed IGZO thin film transistors with buried conductive layers, J. Nanosci. Technol. 17 (05) (2017) 3401. [12] M. Ahn, W. Cho, Performance enhancement of a-IGZO TFTs with partial heterojunction channel layer, J. Nanosci. Technol. 16 (2016) 11347. [13] Y. Chung, U. Kim, E. Hwang, C. Hwang, Indium tin oxide/InGaZnO bilayer stacks for enhanced mobility and optical stability in amorphous oxide thin film transistors, Appl. Phys. Lett. 105 (2014) 013508. [14] J.M. Lee, I.T. Cho, J.H. Lee, H.I. Kwon, Bias-stress-induced stretched-exponential time dependence of threshold voltage shift in InGaZnO thin film transistors, Appl. Phys. Lett. 93 (2008) 093504. [15] S. Kim, M. Ahn, W. Cho, J. Park, Device instability of amorphous InGaZnO thin film transistor with transparent source and drain, Microelectron. Reliab. 64 (2016) 575. [16] http://www.silvaco.com/products/device_simulation/atlas.html. [17] B. Ryu, H. Noh, E. Choi, K. Chang, O-vacancy as the origin of negative bias illumination stress instability in amorphous In-Ga-Zn-O thin film transistors, Appl. Phys. Lett. 97 (2010) 022108. [18] H. Oh, S. Yoon, M. Ryu, C. Hwang, S. Yang, S. Park, Photo-accelerated negative bias instability involving subgap states creation in amorphous In-Ga-Zn-O thin film transistor, Appl. Phys. Lett. 97 (2010) 183502. [19] K. Ji, J. Kim, H. Jung, S. Park, R. Choi, U. Kim, C. Hwang, D. Lee, H. Hwang, J. Jeong, Effects of high-pressure oxygen annealing on negative bias illumination stressinduced instability of InGaZnO thin film transistors, Appl. Phys. Lett. 98 (2011) 103509. [20] K. Sugiyama, H. Ishii, Y. Ouchi, Dependence of indium-tin-oxide work function on surface cleaning method as studied by ultraviolet and X-ray photoemission spectroscopies, J. Appl. Phys. 87 (1) (2000) 295.
Please cite this article as: S.M. Kim, et al., Negative bias illumination stress instability in amorphous InGaZnO thin film transistors with ITO local conducting buried layer, Microelectronics Reliability (2016), http://dx.doi.org/10.1016/j.microrel.2017.06.020
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Negative bias illumination stress instability in amorphous InGaZnO thin film transistors with ITO local conducting buried layer Sang Min Kim a, Min-Soo Kang b, Won-Ju Cho b, Jong Tae Park a,⁎ a b
Dept. of Electronics Eng., Incheon National Univ., Incheon 406-772, Republic of Korea Dept. of Electronic Materials Eng., Kwangwoon Univ., Seoul 139-701, Republic of Korea
a r t i c l e
i n f o
Article history: Received 12 May 2017 Received in revised form 31 May 2017 Accepted 13 June 2017 Available online xxxx Keywords: InGaZnO thin film transistor Negative bias illumination stress ITO conducting layer
a b s t r a c t The investigations on the device instabilities of amorphous InGaZnO thin film transistors (a-IGZO TFTs) with ITO local conducting buried layer (LCBL) under the source/drain region and in the middle of the active channel region have been performed under negative bias and illumination stress. From the increased drain current of a-IGZO with ITO LCBL, one can control the drive current by modulating the length of ITO LCBL without changing the ratio of channel width and length. The reason for the less degradation of a-IGZO TFTs with LCBL under negative bias stress than that of device without LCBL was explained by the fact that ITO LCBL could act to reduce the effective energy barrier and act as a hole damping layer. However, the device degradation of a-IGZO with ITO LCBL under negative bias and illumination stress was more significant than that of one without LCBL due to the electron hole pair generation in ITO layer under illumination. © 2016 Elsevier Ltd. All rights reserved.
1. Introduction Due to the wide band gap and the excellent electronic properties compared to amorphous Si thin film transistors, amorphous InGaZnO thin film transistors (a-IGZO TFTs) have been extensively studied for the applications in next-generation display devices. Currently the applications of a-IGZO TFTs have been extended to the logic circuits, RAM (Random Access Memory), 3-D stacking memory, and BEOL (Back End of Line) transistors for PMIC (Power Management IC) [1–5]. For the applications in display and electronic devices, the extensive studies for better device performances are required including high electron mobility and high On/Off current ratio. Accordingly, many studies on various heat treatments, high-K dielectric materials, engineered stacked gate dielectric layers, and advanced device structures have been suggested [6–9]. Especially, the experimental studies on the device characterization of a-IGZO TFTs with ITO local conducting buried extended layer under both source and drain regions, and in the middle of channel region have been reported to enhance the electron mobility and high On/Off current ratio [10–12]. By introducing optimized thin ITO layer (5 nm) between the gate insulator and InGaZnO channel, the reduction of threshold voltage shifts has been reported [13]. In spite of these advantages, the device instability caused by gate bias and illumination during display panel operation is the prime concern. For display devices, the light induced device instability of a-IGZO under negative gate bias illumination stress (NBIS) condition is more important because the turn⁎ Corresponding author. E-mail address: [email protected] (J.T. Park).
off time of device is longer than turn on time. Although the enhanced device performances of a-IGZO TFTs with ITO local conducting buried extended layer under both source and drain regions, and in the middle of channel region have been reported, the device instabilities have not been investigated in depth. In this work, the device instabilities of a-IGZO TFTs according to the different length of ITO LCBL under both source and drain regions (aIGZO TFTs with LCBL-S/D) and in the middle of channel region (aIGZO TFTs with LBCL-C) have been investigated under negative bias stress (NBS) and NBIS. 2. Device fabrication a-IGZO TFTs with LCBL have been fabricated using a p-type (100) silicon wafer substrate grown on thermal oxide (SiO2) having a resistivity of 10 Ω·cm. After RCA cleaning, a 30 nm thick of ITO was deposited to form LCBL using the RF magnetron sputtering method (Ar flow of 20 sccm, working pressure of 3 mTorr). The thickness of ITO (TITO) was ranged from 10 nm to 40 nm for a-IGZO TFTs with LCBL-S/D. According to the different device structures of a-IGZO with LCBL-S/D and LCBL-C, the patterning of LCBLs was carried out by using a conventional photo-lithography and chemical etching in an ITO etchant. To form the active region, a 50 nm thick of InGaZnO layer (In2O3:Ga2O3:ZnO = 1:1:1 mol%) was deposited using the RF sputtering method with an Ar flow of 20 sccm, working pressure of 6 mTorr and an RF power of 100 W at room temperature. The IGZO layer was then patterned by photo-lithography and etched using a buffered oxide etchant (BOE 30:1). After the patterning of active layer, a microwave annealing was
http://dx.doi.org/10.1016/j.microrel.2017.06.020 0026-2714/© 2016 Elsevier Ltd. All rights reserved.
Please cite this article as: S.M. Kim, et al., Negative bias illumination stress instability in amorphous InGaZnO thin film transistors with ITO local conducting buried layer, Microelectronics Reliability (2016), http://dx.doi.org/10.1016/j.microrel.2017.06.020
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S.M. Kim et al. / Microelectronics Reliability xxx (2016) xxx–xxx
conducted at a frequency of 2.45 GHz and a power of 1 kW for 2 min to remove the defects in InGaZnO layer and at the interface between active layer and gate dielectric layer. Subsequently, a 100 nm thick ITO and 20 nm thick Ti/130 nm thick Al were deposited for the source and drain electrodes of a-IGZO TFTs with LCBL-S/D and a-IGZO TFTs with LCBL-C, respectively. The channel width (W) and length (L) of a-IGZO TFTs with LCBL-S/D were 20 μm and 10 μm, respectively. The space distance (DITO) between ITO LCBL under the source and drain regions were ranged from 2 μm to 10 μm. In evaluating the effect of DITO on device instability under NBIS, the reference device without ITO LCBL was also fabricated using the same process. The W and L of a-fabricated a-IGZO TFTs with LCBL-C were 160 μm and 100 μm, respectively. The length of ITO buried layer in the middle of channel region (LITO) was split into 20, 40, 60, and 80 μm with constant channel width of 80 μm. To evaluate the effect of LITO on device instability, the reference device without ITO LCBL was also fabricated using the same process. Fig. 1 shows the schematic diagrams of fabricated a-IGZO TFTs with LCBL-S/D and a-IGZO TFTs with LCBL-C. The electrical characteristics were measured with the use of a semiconductor parameter analyzer and all measurements were performed in a dark box in order to avoid light or external influence.
3. Results and discussion
Fig. 1. Schematic diagrams of (a) a-IGZO TFTs with LCBL-S/D and (b) a-IGZO TFTs with LCBL-C.
From the transfer curves of the fabricated a-IGZO TFTs with LCBL-S/D and LCBL-C as shown in Figs. 2 and 3, one can observe that ON currents of a-IGZO TFTs with LCBL-S/D and LCBL-C increase with the decrease of
Fig. 2. Transfer curves of a-IGZO TFTs with LCBL-S/D.
Fig. 3. Transfer curves of a-IGZO TFTs with LCBL-C.
Please cite this article as: S.M. Kim, et al., Negative bias illumination stress instability in amorphous InGaZnO thin film transistors with ITO local conducting buried layer, Microelectronics Reliability (2016), http://dx.doi.org/10.1016/j.microrel.2017.06.020
S.M. Kim et al. / Microelectronics Reliability xxx (2016) xxx–xxx
3
Table 1 Summary of device performance parameters at dark condition. Dark a-IGZO TFT with LCBL-S/D a-IGZO TFT with LCBL-C
Ref DITO = 2[μm] Ref LITO = 80[μm]
VTH (V)
S (V/dec)
μ (cm2/V·s)
ION (A)
IOFF (A)
ION/IOFF
2.3 1.8 2.2 1.8
0.36 0.23 0.34 0.21
13.3 67.4 10.4 44.3
2.9E − 5 1.5E − 4 2.4E − 5 1.1E − 4
6.3E − 12 4.6E − 12 1.1E − 11 5.3E − 12
4.6E + 6 3.2E + 7 2.2E + 6 2.1E + 7
DITO and the increase of LITO, respectively. This is due to the decrease of overall series resistance by enhancing the conductivity of the inner channel layer [12] and due to reduce the effective channel length. The summary of measured device performance parameters was shown in Table 1. It is worth noting that the field effect mobility (μFE) of a-IGZO without LCBL-S/D is noticeably enhanced from 14.2 cm2/V·s to 69.4 cm2/V·s when the LCBL with DITO = 2 μm is embedded. The measured VTH was defined as the VGS required to reach a drain current of 2.5 μA ∗ L/W[μA] at VDS = 2.0 V and the μFE was determined from following equation.
μ FE ¼
Lgm ∂IDS ; gm ¼ VDS ¼ const WCox VDS ∂VGS
ð1Þ
The On/Off current ratio is also increased from 6.5 × 106 to 4.8 × 107. When the LCBL with LITO = 80 μm is embedded, the μFE of a-IGZO without LCBL-C is enhanced from 10.9 cm2/V·s to 44.3 cm2/V·s. The On/Off current ratio is also increased from 2.2 × 106 to 2.1 × 107. The subthreshold characteristics are enhanced with ITO LCBL. The enhancement of μFE can be attributed to the increase of the channel conductance due to the embedded ITO BCBL. Therefore, without changing the ratio of W/L and device structures such as double gate, we can control the drive current of a-IGZO TFTs with modulation of DITO in a-IGZO TFTs with LCBL-S/D or LITO in a-IGZO without LCBL-C.
Fig. 4 shows the evolution of transfer curves as a function of NBS stress time for a-IGZO TFTs without LCBL and with DITO = 2 μm. From the comparison of the transfer curves, it can be seen that the positive shifts of transfer curves with NBS stress time are more significant in aIGZO TFTs without LCBL than in a-IGZO TFTs with DITO = 2 μm. From the time dependence of threshold voltage shifts (|ΔVTH | = |VTH(t) − VTH(t = 0)|) under NBS as shown in Fig. 5, it can be clearly seen that |ΔVTH | is decreased with the decrease of DITO. It means that ITO LCBL can play an important role acting as a hole damping layer or as a protecting layer to reduce the hole injection into the interface between the channel and the gate dielectric layer. Since the negative shift of threshold voltage under NBS is generally accepted due to the hole trapping at the interface between the channel and the gate dielectric layer, the average effective energy barrier (Eτ) that holes in the channel needed to overcome to enter the gate insulator was extracted from fitting the measurement with the commonly used stretchedexponential equation for different DITO [14,15]. From a plot of the characteristic trapping time (τ) as a function of 1/ KT as shown in Fig. 6, Eτ increases as DITO decreases. These results suggest that ITO LCBL may be acting as a protecting layer to reduce the hole injection into the gate insulator. From the energy band diagram of a-IGZO TFT with LCBL at the equilibrium as shown in Fig. 7, ITO one can speculate that LCBL can reduce the hole injection from the active channel into the gate dielectric layer. We also confirmed that Eτ of a-IGZO with LCBL-C increases as LITO increases.
Fig. 5. Time dependences of |ΔVTH | of a-IGZO TFTs with LCBL-S/D under NBS.
Fig. 4. Evolution of transfer curves of (a) a-IGZO TFTs without LCBL and (b) with DITO = 2 μm as a function of NBS stress time.
Fig. 6. τ as a function of 1/KT for a-IGZO TFTs with LCBL-S/D.
Please cite this article as: S.M. Kim, et al., Negative bias illumination stress instability in amorphous InGaZnO thin film transistors with ITO local conducting buried layer, Microelectronics Reliability (2016), http://dx.doi.org/10.1016/j.microrel.2017.06.020
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Fig. 7. Energy band diagram of a-IGZO TFT with LCBL-C at the equilibrium.
Fig. 8. Comparison of electric field distribution for (a) a-IGZO TFTs without LCBL and (b) with DITO = 10 μm.
In order to investigate the electric field distribution of a-IGZO TFTs with LCBL-S/D, the device simulation has been carried out using the 2dimensional SIVACO ATLAS software [16]. The setup is matched with fabricated devices by simulating with the device. To address the effect of LCBL on the device performances, the initial transfer and output characteristics of the referenced device was calibrated using optimization of analytical TFTs models including the sub-bandgap DOS and material properties. From the comparison of the electric field distribution for device without LCBL and with DITO = 10μmas shown in Fig. 8, one can clearly observe that the electric field near the interface between ITO and the channel layer for device with DITO = 10 μm is increased significantly. Therefore, it is believed that the increased field collects more holes and ITO acts as a hole damping layer. Table 2 shows the summary of measured device performance parameters under illumination condition. A white halogen lamp ranging from 500 nm to 700 nm wavelength and with the intensity of IL = 0.22 mW/cm2 was used as a light source. The subthreshold swing S of ITO device was slightly increased under illumination. Due to the increased electron concentration from the electron-hole pair generation under illumination, ION/IOFF and μFE are increased. It has been generally accepted that the negative shift of VT under NBIS is due to the hole trapping at the interface of the gate insulator/
active channel and photoionization of neutral oxygen vacancy (VO) to charged oxygen vacancy (Vo2+) state which exhibits positively charged defects [17–19]. Due to the combination of hole trapping and charged oxygen vacancy, Off current is increased and the stretch-out in the subthreshold characteristics can be observed. Fig. 9 shows the evolution of transfer curves as a function of NBIS stress time for a-IGZO TFTs without LCBL and with DITO = 2 μm. From the comparison of the transfer curves, it can be seen that the negative shifts of transfer curves with stress time are more significant in a-IGZO TFTs with DITO = 2 μm of LCBL than device without LCBL. After NBIS, the subthreshold swing S of a-IGZO TFTs with LCBL-S/D is increased from 0.23 dec/V at dark condition to 0.48 dec/V at illumination condition. With the increase of NBIS time, the hump occurrence resulted from the turn-on of a parasitic transistor is observed more clearly in device with DITO = 2 μm than device without LCBL. The reason may be attributed to the increased electric field for the device with LCBL. The increased electric field leads to more hole accumulation at the interface region between ITO and channel layer. From the time dependence of |ΔVTH | under NBIS as shown in Fig. 10, the |ΔVTH | for a-IGZO TFTs with LCBL-S/D and a-IGZO TFTs with LCBL-C increase as DITO decreases and as LITO increases, respectively. The
Table 2 Summary of device performance parameters at illumination condition. Light a-IGZO TFT with LCBL-S/D a-IGZO TFT with LCBL-C
Ref DITO = 2[μm] Ref LITO = 80[μm]
VTH (V)
S (V/dec)
μ (cm2/V·s)
ION (A)
IOFF (A)
ION/IOFF
2.1 1.6 1.9 1.6
0.38 0.48 0.40 0.43
14.2 69.4 11.8 47.0
2.9E − 5 1.6E − 4 2.5E − 5 1.2E − 4
4.6E − 12 3.3E − 12 4.5E − 12 2.1E − 12
6.3E + 6 4.8E + 7 5.6E + 6 5.7E + 7
Please cite this article as: S.M. Kim, et al., Negative bias illumination stress instability in amorphous InGaZnO thin film transistors with ITO local conducting buried layer, Microelectronics Reliability (2016), http://dx.doi.org/10.1016/j.microrel.2017.06.020
S.M. Kim et al. / Microelectronics Reliability xxx (2016) xxx–xxx
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Fig. 11. Transfer curves of a-IGZO TFTs with LCBL-S/D for different TITO at IL = 0.66 mW/cm2.
transparent [20]. To confirm the photo-generation of electron-hole pairs in ITO layer, the transfer characteristics for different TITO were measured under light illumination (IL = 0.66 mW/cm2). Fig. 11 shows that the negative shifts of transfer curves are more significant with increasing TITO. It indicates that the more electron-hole pairs were generated with increasing TITO. The time dependence of |ΔVTH | for different TITO under NBIS as shown in Fig. 12 indicates also that the more electron-hole pairs in ITO layer were generated as TITO increases. 4. Conclusion Fig. 9. Evolution of transfer curves as a function of NBIS stress time for (a) a-IGZO TFTs without LCBL and (b) with DITO = 2 μm.
increased device degradations in a-IGZO TFTs with ITO LCBL mean that photo-generated holes within ITO layer may be injected into the gate insulator under light illumination although the ITO layer is almost
Due to the enhanced effective mobility, the drain currents of a-IGZO TFTs with ITO LCBL were increased. One can control the drive current by modulating the length of ITO LCBL without changing the ratio of channel width and length or modifying the device structures. The reason for the less degradation of a-IGZO TFTs with ITO LCBL under negative bias stress than that of device without ITO LCBL was explained by the fact that ITO LCBL could act to reduce the effective energy barrier and act as a hole damping layer. However, the device degradations of a-IGZO with ITO LCBL under negative bias and illumination stress were more significant than that of one without LCBL due to the electron hole pair generation in ITO layer under illumination. Therefore, a-IGZO TFTs with ITO LCBL may be better for the application of logic circuits or BEOL transistors than for the display devices. Acknowledgement This work was supported by the Incheon National University Research Grant in 2016.
Fig. 10. Time dependences of |ΔVTH | under NBIS for (a) a-IGZO TFTs with LCBL-S/D (b) aIGZO TFTs with LCBL-C.
Fig. 12. Time dependence of |ΔVTH | under NBIS for (a) a-IGZO TFTs with LCBL-S/D with different TITO.
Please cite this article as: S.M. Kim, et al., Negative bias illumination stress instability in amorphous InGaZnO thin film transistors with ITO local conducting buried layer, Microelectronics Reliability (2016), http://dx.doi.org/10.1016/j.microrel.2017.06.020
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Please cite this article as: S.M. Kim, et al., Negative bias illumination stress instability in amorphous InGaZnO thin film transistors with ITO local conducting buried layer, Microelectronics Reliability (2016), http://dx.doi.org/10.1016/j.microrel.2017.06.020