- Email: [email protected]
Effect of interfacial layer on device performance of metal oxide thin-film transistor with a multilayer high-k gate stack
Thin Solid Films xxx (xxxx) xxx–xxx
Contents lists available at ScienceDirect
Thin Solid Films journal homepage: www.elsevier.com/locate/tsf
Effect of interfacial layer on device performance of metal oxide thin-film transistor with a multilayer high-k gate stack ⁎
Dun-Bao Ruana, Po-Tsun Liub, , Yu-Chuan Chiub, Po-Yi Kuob, Min-Chin Yub, Kai-Zhi Kana, Ta-Chun Chienb, Yi-Heng Chenb, Simon M. Szea a b
Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu 30010, Taiwan, ROC Department of Photonics and Institute of Electro-Optical Engineering, National Chiao Tung University, Hsinchu 30010, Taiwan, ROC
A R T I C LE I N FO
A B S T R A C T
Keywords: Indium-gallium-zinc-oxide Thin-film transistors Multilayer high-k Low temperature process Interfacial layer engineering
The amorphous indium gallium zinc oxide thin-film transistors (TFTs) with a multilayer high-k gate stack are investigated in this research. In order to achieve a high quality gate insulator for plastic flexible display application, the multilayer high-k gate stacks (SiO2/TiO2/HfO2) are deposited by a low-temperature physical vapor deposition (PVD) process. On the other hands, an interfacial layer between the high-k stack and metal oxide channel is important for the device performance. The effects of interfacial layer material (SiO2 or Ga2O3) are also discussed in this report. The devices with SiO2 interfacial layer show a high on/off current ratio of ~7 × 107 for its low gate leakage current, a small sub-threshold swing of 0.093 V/decade and a high field-effect mobility of ∼37.8 cm2/Vs for its good interface condition and low interface defeats. This research shows that the interface engineering of multilayer PVD gate stacks is necessary for oxide TFT fabrication.
1. Introduction Recently, transparent amorphous oxide semiconductor (TAOS) has attracted many attentions for its excellent electrical performance and transparent characteristics [1]. Among many TAOS materials [2–5], the amorphous indium gallium zinc oxide (a-IGZO) is the most potential candidate serving as semiconductor layer in thin film transistor (TFT) due to its low off-current (IOFF) originated from its large energy band gap and high mobility of overlapped s-orbitals. Moreover, high dielectric constant (high-k) gate insulator was widely investigated in aIGZO TFTs to achieve low operating voltage owing to their outstanding capability of gate control [6,7]. Besides, some multilayer high-k structure, like, SiO2/Ta2O5/SiO2 [8], Al2O3/HfO2/Al2O3 [9], SiO2/HfO2/ SiO2 [10], are proposed to further improve the field effect mobility and adjust the negative threshold voltage. However, it is difficult to achieve large on/off current ratio and higher mobility simultaneously. Although some works exhibit many advantages such as low gate-leakage current and higher stability, there are still several drawbacks for high-k gate insulators such as large surface roughness and low band offset barrier, which may restrict the carrier mobility and standby power consumption [11,12]. Therefore, the interfacial layer engineering is necessary for the TFT device performance, while the interfacial layer material and effect are worthy of further discussion. In the present work, a multilayer high-k gate insulator HfO2/TiO2/ ⁎
SiO2 structure (HTS) is proposed to increase the effective dielectric constant and reduce the device leakage current. In addition, two types of high quality interfacial layer materials, SiO2 and Ga2O3, are selected for comparison, in order to either improve the surface morphology between the channel layer and multilayer gate insulator after the inevitable thermal process or enlarge the energy band offset between the HfO2 and channel material without introducing more interface defeat states. The mechanisms for enhancement of electrical characteristics are also well discussed in detail by the physical analysis and operation energy band model of a-IGZO TFT. 2. Experiment TFT devices with bottom gate staggered structure were fabricated on a doped n-type Si wafer with 100-nm thick thermal buffer oxide layer grown on top. The gate electrodes were then formed and patterned by sputtering 60-nm thick TaN thin film through a shadow mask. Then, a multilayer gate dielectric stack of 3-nm SiO2, 30-nm TiO2 and 40-nm HfO2 was deposited as gate insulator (GI) layer by electron gun evaporation. Afterward, two types of interfacial layer was deposited in the in-situ chamber, using with 1-nm thick SiO2 interfacial layer or 1nm thick Ga2O3 interfacial layer which named SHTS GI sample and GHTS GI sample, respectively. Simultaneously, the multilayer high-k TFT device without interfacial layer named HTS GI sample is used as
Corresponding author. E-mail address: [email protected] (P.-T. Liu).
https://doi.org/10.1016/j.tsf.2018.05.024 Received 18 November 2017; Received in revised form 10 May 2018; Accepted 10 May 2018 0040-6090/ © 2018 Elsevier B.V. All rights reserved.
Please cite this article as: Ruan, D.-B., Thin Solid Films (2018), https://doi.org/10.1016/j.tsf.2018.05.024
Thin Solid Films xxx (xxxx) xxx–xxx
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Fig. 1. 3D structure view and schematic process flow in this work.
focused ion beam (FEI Helios 1200+, accelerating voltage: 30 kV; ion source: gallium liquid metal). In addition, the chemical bonding states of a-IGZO films were investigated by X-ray photoelectron spectroscopy (XPS). The XPS signal was obtained from a PHI Quantera SXM apparatus from an Al Kα X-ray source operated at 25 W after the sample was sputter-cleaned with an Argon ion beam power and emission current set at 40 W and 4.025 mA, respectively. The binding energy scales of all XP spectra were calibrated by taking the C1s (~284.8 eV) as the reference. The peak fit analysis was performed using the XPSPEAK41 software application. The O1s spectra were fitted to examine the oxygen binding states. Near Gaussian peak shapes were used, the FWHM of the synthetic peak were fixed to 1.5–1.6 eV, and the binding energy of the synthetic peaks were not allowed to change from one spectrum to the other.
the control one. After the multilayer GI layer deposition, a post deposition annealing was performed at 300 °C in oxygen ambient for 30 min by a thermal furnace, in order to improve the quality of dielectrics film and fix the bulk defeats in the multilayer GI. After gate region formation, a 40-nm thick a-IGZO thin film was deposited as the channel layer by RF magnetron sputtering process using a target with the atomic ratio of In:Ga:Zn:O = 1:1:1:4 at room temperature. During the deposition, the flow rate of O2 and Ar was set at 1 and 20 sccm, respectively. The total gas pressure in the sputter chamber was controlled to be 0.4 Pa, while the optimization case of a-IGZO channel deposition was applied for device fabrication in this work. Then, the channel material was annealed by the thermal furnace at 300 °C in the oxygen atmosphere for 30 min. Afterward, in order to achieve a low work function and high conductivity metal contact, the source and drain electrodes were formed by 20-nm thick Ti and 120-nm thick Pt metal film stacks and patterned through the shadow mask with channel width (W) of 500 μm and length (L) of 50 μm. A detailed process flow chart and a three-dimensional (3D) view of the prepared samples are shown in Fig. 1. Electrical measurements were conducted in the dark chamber at room temperature using Agilent 4156C semiconductor parameter analyzer and 4284A precision LCR meter. Besides, the cross-sectional transmission electron microscope images were taken by JEM-2010F under an operating voltage of 200 kV with the sample prepared by
3. Results and discussion Fig. 2 shows the cross-sectional transmission electron microscope images of IGZO TFT with (a) HTS, (b) SHTS and (c) GHTS GI stacks, respectively, while the atomic force microscope images of the interfacial layer and the root-mean-square surface roughness values are also included. The IGZO channel and multilayer gate dielectric are examined by fast Fourier transform, where the diffraction image exhibits the amorphous phases. Besides, a TFT device structure with TaN metal-
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A. The value of μFE was extracted by the transconductance in the linear region (VD = 0.1 V). The threshold voltage was defined by VGS at constant normalized drain current (ID/(W/L)) of 10 nA. The DIT at the interface of gate dielectric/a-IGZO was calculated based on the SS value by the following Eq. (1) [13]:
SS⋅lg e C DIT = ⎜⎛ − 1⎟⎞⋅ OX 2 kT / q ⎝ ⎠ q
(1)
where k is the Boltzmann constant, T is the absolute temperature, q is the unit electron charge and COX is the gate dielectric capacitance per unit area. As a result, the SHTS GI device exhibits a lower S.S. of 93 mV/dec, a higher μFE of 37.8 cm2/Vs, a higher ION/IOFF of 7 × 107 and a lower DIT of 1.67 × 1012 eV−1 cm−2 compared with other samples. It suggests that the SiO2 interfacial layer shows a best interface condition for its high band offset and good material stability, which can further suppress the gate leakage current and surface roughness. In addition, there is a desirable positive threshold voltage and acceptable sub-threshold swing improvement for the GHTS GI sample. It can be attributed to that the Ga2O3 interfacial layer can reduce the frontchannel oxygen deficiency, which may lower the control barrier of channel. Nevertheless, the carrier mobility and driving current of the GHTS GI sample are not influenced by the suppressed carrier concentration. It may benefit from the lower surface roughness, which is caused by the interaction between front-channel and high-k GI. The output characteristics of the sample are also shown in Fig. 3(b) HTS, (c) SHTS and (d) GHTS GI stacks, respectively. The ION of all samples shows similar values, while the GHTS GI sample exhibits typical transistor characteristics and excellent linear/saturation behavior in enhancement mode. Since the HTS and SHTS sample may have a higher carrier concentration, the channel region of these two samples is not totally depleted, and the undepleted region will contribute the excess drain current in the linear operation region of the output characteristics. Fig. 3(e) and (f) show the capacitance-voltage (C–V) and current density-voltage (J–V) characteristics of Pt/Ti/GI stacks/TaN (Metal/Insulator/Metal) capacitor fabricated during the TFT process, respectively. The capacitance density of all the samples, measured at the frequency of 100 KHz, also shows a similar value which is about 0.493 μF/cm2 (HTS), 0.473 μF/cm2 (SHTS) and 0.481 μF/cm2 (GHTS), respectively. Besides, the effective dielectric constant of the HTS, SHTS and GHTS GI stacks is about 40.67, 39.55 and 40.22, respectively. It suggests that the influence of a 1-nm thick interfacial layer for the capacitance can be negligible. On the other hand, all the samples show a very low leakage current which means that the multilayer gate stacks can provide a good capability of gate control. In order to investigate the origin of this result, the chemical and structural evolution of the a-IGZO films with different interfacial layer were analyzed by XPS, calibrated by tacking the C1s (~284.8 eV) as the reference. The XPS spectra of O1s signal were shown in Fig. 4 to examine the oxygen binding states at the different locations of IGZO thin film: (a) HTS (near back-channel), (b) HTS (near front-channel), (c) SHTS (near back-channel), (d) SHTS (near front-channel), (e) GHTS (near back-channel) and (f) GHTS (near front-channel). The O1s signal is fitted by three nearly Gaussian distributions with the peak fitting software named XPSPEAK41, approximately centered at 530 ± 0.1 eV, 531 ± 0.3 eV and 532 ± 0.2 eV, respectively [14]. For the lowest binding energy peak located at 529.9 eV with a full-width half-maximum (FWHM) of 1.6 eV, the signal is denoted by oxygen-lattice bond, which is related to the O2– ions combined with the Ga, In, Zn atoms in the IGZO compound system. Then, the signal is denoted by oxygenhydroxide bond for the highest binding energy peak located at 531.8 eV with a FWHM of 1.6 eV. The peak is associated with the loosely
Fig. 2. The cross-sectional transmission electron microscope images of IGZO TFT with (a) HTS, (b) SHTS and (c) GHTS GI stacks, while the atomic force microscope images of the interfacial layer and the root-mean-square surface roughness values are also included.
gate, 3-nm thick SiO2, 30-nm thick TiO2, 40-nm thick HfO2 multilayer gate dielectric stack, interfacial layer, and the IGZO channel can be clearly observed. The interfacial layer between high-k dielectric and active channel layer plays an important role on the suppression of the interaction at the front-channel, which also can be proved by the atomic force microscope images and the values of the root-mean-square surface roughness for different interfacial layer engineering. Fig. 3(a) shows the transfer characteristics of TFT device with three types of GI stacks. The electrical parameters for all the samples including sub-threshold swing (S.S.), field-effect mobility (μFE), on/off current ratio (ION/IOFF), threshold voltage (VTH) and the interfacial trap density (DIT), are summarized in Table 1. The sub-threshold swing was determined by an increase decade in drain current (ID) from 1010 to 108
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Fig. 3. (a) The transfer characteristics of TFT device with three types of GI stacks and the output characteristics of the sample with (b) HTS, (c) SHTS and (d) GHTS GI stacks; (e) the capacitance-voltage (C–V) and (f) current density-voltage (J–V) characteristics of Pt/Ti/GI stacks/TaN capacitor fabricated during the TFT process.
amount of oxygen-hydroxide bond signal and a similar proportion of donor-like oxygen-vacancy bond (11%–15%) at the back-channel surface, which is easily excited into the charged states in the form of ionized oxygen vacancies (VO2+). On the contrary, the sample with HTS GI exhibits the highest proportion of donor-like oxygen-vacancy bond (15.76%) near the front-channel of a-IGZO film, while the sample with GHTS GI shows the lowest value (8.61%). As a whole, it means that the front-channel interfacial layer may be the main reason influencing the channel conductivity, while the incorporation of Ga3+ cation in Ga2O3 material could effectively suppress carrier generation in the a-IGZO due to its stronger chemical bonds with oxygen than zinc or indium ions [15]. To further clarify the mechanisms of the interface effects, Fig. 5 shows the energy band diagram of hetero-structure interface for the sample with (a) HTS, (b) SHTS and (c) GHTS GI stacks [16–18]. As shown in the band structure of HTS GI, the TiO2 has higher k value than HfO2, which can further lower the equivalent oxide thickness, but it suffers from high leakage current due to a very high conduction band offset (ΔEC) and a serious reliability problem caused by the Ti out-diffusion in the thermal process. Thus, the structure of HfO2/TiO2/SiO2 is
Table 1 Electrical performance of device with different GI stacks for comparison, including sub-threshold swing (S.S.), field effect mobility (μFE), on/off current ratio (ION/IOFF), threshold voltage (VTH), and the interfacial trap density (DIT). Gate insulator materials
SS (V/decade)
μEF (cm2/V·s)
ION/IOFF
VTH (V)
DIT (eV−1 cm−1)
HfO2/TiO2/ SiO2(HTS) SiO2/HfO2/TiO2/ SiO2(SHTS) Ga2O3/HfO2/TiO2/ SiO2(GHTS)
0.135
~30.5
~3 ∗ 106
−0.128
3.91 ∗ 1012
0.093
~37.8
~7 ∗ 107
0.065
1.67 ∗ 1012
0.097
~32.4
~2 ∗ 107
0.295
1.90 ∗ 1012
bounded oxygen at the surface of IGZO film, which can be terminated with the specific chemisorbed oxygen, such as CO2, absorbed O2, or absorbed H2O. For the middle binding energy component located at 531.1 eV with a FWHM of 1.5 eV, the signal is denoted by oxygen-vacancy bond. The peak of OV is attributed to O2– ions that are in oxygen deficient region of the IGZO matrix. All the samples show a negligible
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Fig. 4. Analysis of XPS O1s spectrum at the different location of IGZO thin film with different GI stacks: (a) HTS (near back-channel), (b) HTS (near front-channel), (c) SHTS (near back-channel), (d) SHTS (near front-channel), (e) GHTS (near back-channel) and (f) GHTS (near front-channel).
material, the SHTS sample and GHTS sample should exhibit a better hysteresis characteristic than the HTS sample. However, in the IGZO TFT device with SHTS or GHTS GI stacks, there are two interfacial surfaces existed at the interfaces of IGZO/interfacial layer (SiO2 or Ga2O3) and interfacial layer (SiO2 or Ga2O3)/HfO2. Both the interfaces increase the probability of electron trapping in TFT device and cause a higher hysteresis behavior. That is why the TFT with SHTS or GHTS GI stacks exhibited a larger change in threshold voltage as compared to the one only with a single IGZO/HfO2 interface in the TFT device with HTS GI, while all the TFT show the similar value of the DIT data. In addition, the reliability issue is also investigated. Fig. 7 shows threshold voltage shift of the three types of GI stacks versus stress time under (a) 1MV/cm positive gate bias stress and (b) -1MV/cm negative gate bias stress for aIGZO TFTs. It is found that the TFT with SHTS GI shows an excellent reliability characteristic under both positive and negative gate bias stress, compared to the ones with HTS or GHTS GI. This result indicates that the existence of stable SiO2 interfacial layer, which was not consumed by the channel layer or GI layer during the thermal processes,
proposed to lower the leakage current and suppress the out-diffusion by the band engineering. Then, for SHTS sample, a 1-nm thick SiO2 interfacial layer is added to further enlarge the conduction band offset from 2.39 eV to 4.27 eV and reduce the concentration of interface trap charge between HfO2 and IGZO channel. On the other hand, for GHTS sample, a 1-nm thick Ga2O3 interfacial layer is added to suppress potential interface reaction between the HfO2 and IGZO channel and lower the front channel oxygen deficiency for comparison. It seems that the sample with SHTS GI stacks exhibits a better electrical performance according to the Table 1. Fig. 6 shows the hysteresis characteristics of a-IGZO TFT with (a) HTS, (b) SHTS and (c) GHTS GI stacks. The hysteresis can reveal the phenomenon of electron trapping in the gate stack, the interface of front-channel and active layer. All the TFT devices exhibit an acceptable and similar value of hysteresis (< 105 mV). The multilayer GI structure can effectively improve the hysteresis characteristics by high conduction band offset of TiO2 and HfO2 hetero-structure. On the other hand, with a better interface characteristic of GI layer and channel
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Fig. 6. The hysteresis characteristics of a-IGZO TFT with (a) HTS, (b) SHTS and (c) GHTS GI stacks.
Fig. 5. Energy band diagram of hetero-structure interface for the sample with (a) HTS, (b) SHTS and (c) GHTS GI stacks.
which can be proved by the XPS results in the Fig. 4, the anomalous negative shift of VTH of GHTS sample is also induced by the additional interface and border traps in the gate stacks, while the influence of additional interface for the SHTS sample might be limited by its good material stability.
can effectively improve GI quality by reducing the interfacial trap density and suppressing the phenomenon of the interaction at the frontchannel. On the other hand, there is an anomalous negative shift of VTH for the sample with GHTS GI under negative gate bias stress. According to the physical model proposed in previous documents [19], the negative shift of VTH is mainly related to the presence of VO2+ in the aIGZO film, which may exist in shallow levels below the conduction band minimum and are derived from high concentration of natural vacancies that generate defect states near the valence band maximum. Due to the electron quasi-Fermi level locating within donor-like state levels of the n-channel a-IGZO TFT, more ionized oxygen vacancies, which may be accumulated at the front-channel and dielectric interface, may result in a more negative shift of VTH under negative gate bias stress. With a lower carrier concentration at the front-channel interface,
4. Conclusions The electrical characteristics, physical analysis and operation energy band model of a-IGZO TFTs with different interfacial layer for a multilayer GI structure (HfO2/TiO2/SiO2) are investigated in this work, The TFT device with Ga2O3 interfacial layer shows a desirable positive threshold voltage and acceptable electrical performance improvement. However, a more stable interfacial layer like SiO2, which will not be consumed by channel layer or GI layer during the thermal process, may further improve the electrical performance, interface quality and reliability characteristics.
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References [1] E. Fortunato, P. Barquinha, R. Martins, Oxide semiconductor thin-film transistors: a review of recent advances, Adv. Mater. 24 (2012) 2945–2986. [2] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, H. Hosono, Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors, Nature 432 (2004) 488–492. [3] T. Kamiya, K. Nomura, H. Hosono, Present status of amorphous In-Ga-Zn-O thinfilm transistors, Sci. Technol. Adv. Mater. 11 (2010) 044305. [4] K. Nomura, T. Kamiya, H. Hosono, Stability and high-frequency operation of amorphous In-Ga-Zn-O thin-film transistors with various passivation layers, Thin Solid Films 520 (2012) 3778–3782. [5] C.S. Fuh, S.M. Sze, P.T. Liu, L.F. Teng, Y.T. Chou, Role of environmental and annealing conditions on the passivation-free In-Ga-Zn-O TFT, Thin Solid Films 520 (2011) 1489–1494. [6] Y. Shao, X. Xiao, X. He, W. Deng, S. Zhang, Low-voltage a-InGaZnO thin-film transistors with anodized thin HfO2-gate dielectric, IEEE Electron. Device Lett. 36 (2015) 573–575. [7] Y. Gao, J. Zhang, X. Li, Solution-processed zirconium oxide gate insulators for top gate and low operating voltage thin-film transistor, IEEE J. Disp. Technol. 11 (2015) 764–767. [8] L. Zhang, J. Li, X.W. Zhang, X.Y. Jiang, Z.L. Zhang, High-performance ZnO thinfilm transistors with sputtering SiO2/Ta2O5/SiO2 multilayer gate dielectric, Thin Solid Films 518 (2010) 6130–6133. [9] S. Chang, Y.W. Song, S. Lee, S.Y. Lee, B.K. Ju, Efficient suppression of charge trapping in ZnO-based transparent thin film transistors with novel Al2O3/HfO2/ Al2O3 structure, Appl. Phys. Lett. 92 (2008) 192104. [10] H. Zhang, Y. Zhang, X. Chen, C. Li, X. Ding, Low-voltage-drive and high output current InGaZnO thin-film transistors with novel SiO2/HfO2/SiO2 structure, Mol. Cryst. Liq. Cryst. 651 (2017) 228–234. [11] H.H. Hsu, C.Y. Chang, C.H. Cheng, A flexible IGZO thin-film transistor with stacked TiO2-based dielectrics fabricated at room temperature, IEEE Electron Device Lett. 34 (2013) 768–770. [12] L.Y. Su, H.K. Lin, C.C. Hung, J. Huang, Role of HfO2/SiO2 gate dielectric on the reduction of low-frequent noise and the enhancement of a-IGZO TFT electrical performance, IEEE J. Disp. Technol. 8 (2012) 695–698. [13] L.L. Zheng, S.B. Qian, Y.H. Wang, W.J. Liu, S.J. Ding, Mobility and stability enhancement of amorphous In-Ga-Zn-O TFTs with atomic layer deposited Al2O3/SiO2 stacked insulators, IEEE J. Electron. Devices Soc. 4 (2016) 347–352. [14] H. Xie, G. Liu, L. Zhang, Y. Zhou, C. Dong, Amorphous oxide thin film transistors with nitrogen-doped hetero-structure channel layers, Appl. Sci. 7 (2017) 1099. [15] K. Nomura, T. Kamiya, H. Ohta, K. Ueda, M. Hirano, H. Hosono, Carrier transport in transparent oxide semiconductor with intrinsic structural randomness probed using single-crystalline InGaO3(ZnO)5 films, Appl. Phys. Lett. 85 (2004) 1993–1995. [16] T.C. Fung, C.S. Chuang, C. Chen, K. Abe, R. Cottle, M. Townsend, H. Kumomi, J. Kanicki, Two-dimensional numerical simulation of radio frequency sputter amorphous In-Ga-Zn-O thin-film transistors, J. Appl. Phys. 106 (2009) 084511. [17] D.C. Hays, B.P. Gila, S.J. Pearton, F. Ren, Energy band offsets of dielectrics on InGaZnO4, Appl. Phys. Rev. 4 (2017) 021301. [18] S.J. Chang, T.H. Chang, W.Y. Weng, C.J. Chiu, S.P. Chang, Amorphous InGaZnO ultraviolet phototransistors with a thin Ga2O3 layer, IEEE J. Sel. Top. Quantum Electron. 20 (2014) 3803605. [19] T.M. Pan, C.H. Chen, J.L. Her, K. Koyama, Comparison of structural and electrical properties of Lu2O3 and Lu2TiO5 gate dielectrics for a-InGaZnO thin-film transistors, J. Appl. Phys. 116 (2014) 194510.
Fig. 7. Threshold voltage shift as a function of stress time under (a) positive gate bias stress and (b) negative gate bias stress for a-IGZO TFTs, including the sample with three types of GI stack.
Acknowledgment This work was performed at National Nano Device Laboratories (NDL) Taiwan and financially supported by the Ministry of Science and Technology, Taiwan, under Contract MOST 106-2221-E-009-107-MY3.
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Contents lists available at ScienceDirect
Thin Solid Films journal homepage: www.elsevier.com/locate/tsf
Effect of interfacial layer on device performance of metal oxide thin-film transistor with a multilayer high-k gate stack ⁎
Dun-Bao Ruana, Po-Tsun Liub, , Yu-Chuan Chiub, Po-Yi Kuob, Min-Chin Yub, Kai-Zhi Kana, Ta-Chun Chienb, Yi-Heng Chenb, Simon M. Szea a b
Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu 30010, Taiwan, ROC Department of Photonics and Institute of Electro-Optical Engineering, National Chiao Tung University, Hsinchu 30010, Taiwan, ROC
A R T I C LE I N FO
A B S T R A C T
Keywords: Indium-gallium-zinc-oxide Thin-film transistors Multilayer high-k Low temperature process Interfacial layer engineering
The amorphous indium gallium zinc oxide thin-film transistors (TFTs) with a multilayer high-k gate stack are investigated in this research. In order to achieve a high quality gate insulator for plastic flexible display application, the multilayer high-k gate stacks (SiO2/TiO2/HfO2) are deposited by a low-temperature physical vapor deposition (PVD) process. On the other hands, an interfacial layer between the high-k stack and metal oxide channel is important for the device performance. The effects of interfacial layer material (SiO2 or Ga2O3) are also discussed in this report. The devices with SiO2 interfacial layer show a high on/off current ratio of ~7 × 107 for its low gate leakage current, a small sub-threshold swing of 0.093 V/decade and a high field-effect mobility of ∼37.8 cm2/Vs for its good interface condition and low interface defeats. This research shows that the interface engineering of multilayer PVD gate stacks is necessary for oxide TFT fabrication.
1. Introduction Recently, transparent amorphous oxide semiconductor (TAOS) has attracted many attentions for its excellent electrical performance and transparent characteristics [1]. Among many TAOS materials [2–5], the amorphous indium gallium zinc oxide (a-IGZO) is the most potential candidate serving as semiconductor layer in thin film transistor (TFT) due to its low off-current (IOFF) originated from its large energy band gap and high mobility of overlapped s-orbitals. Moreover, high dielectric constant (high-k) gate insulator was widely investigated in aIGZO TFTs to achieve low operating voltage owing to their outstanding capability of gate control [6,7]. Besides, some multilayer high-k structure, like, SiO2/Ta2O5/SiO2 [8], Al2O3/HfO2/Al2O3 [9], SiO2/HfO2/ SiO2 [10], are proposed to further improve the field effect mobility and adjust the negative threshold voltage. However, it is difficult to achieve large on/off current ratio and higher mobility simultaneously. Although some works exhibit many advantages such as low gate-leakage current and higher stability, there are still several drawbacks for high-k gate insulators such as large surface roughness and low band offset barrier, which may restrict the carrier mobility and standby power consumption [11,12]. Therefore, the interfacial layer engineering is necessary for the TFT device performance, while the interfacial layer material and effect are worthy of further discussion. In the present work, a multilayer high-k gate insulator HfO2/TiO2/ ⁎
SiO2 structure (HTS) is proposed to increase the effective dielectric constant and reduce the device leakage current. In addition, two types of high quality interfacial layer materials, SiO2 and Ga2O3, are selected for comparison, in order to either improve the surface morphology between the channel layer and multilayer gate insulator after the inevitable thermal process or enlarge the energy band offset between the HfO2 and channel material without introducing more interface defeat states. The mechanisms for enhancement of electrical characteristics are also well discussed in detail by the physical analysis and operation energy band model of a-IGZO TFT. 2. Experiment TFT devices with bottom gate staggered structure were fabricated on a doped n-type Si wafer with 100-nm thick thermal buffer oxide layer grown on top. The gate electrodes were then formed and patterned by sputtering 60-nm thick TaN thin film through a shadow mask. Then, a multilayer gate dielectric stack of 3-nm SiO2, 30-nm TiO2 and 40-nm HfO2 was deposited as gate insulator (GI) layer by electron gun evaporation. Afterward, two types of interfacial layer was deposited in the in-situ chamber, using with 1-nm thick SiO2 interfacial layer or 1nm thick Ga2O3 interfacial layer which named SHTS GI sample and GHTS GI sample, respectively. Simultaneously, the multilayer high-k TFT device without interfacial layer named HTS GI sample is used as
Corresponding author. E-mail address: [email protected] (P.-T. Liu).
https://doi.org/10.1016/j.tsf.2018.05.024 Received 18 November 2017; Received in revised form 10 May 2018; Accepted 10 May 2018 0040-6090/ © 2018 Elsevier B.V. All rights reserved.
Please cite this article as: Ruan, D.-B., Thin Solid Films (2018), https://doi.org/10.1016/j.tsf.2018.05.024
Thin Solid Films xxx (xxxx) xxx–xxx
D.-B. Ruan et al.
Fig. 1. 3D structure view and schematic process flow in this work.
focused ion beam (FEI Helios 1200+, accelerating voltage: 30 kV; ion source: gallium liquid metal). In addition, the chemical bonding states of a-IGZO films were investigated by X-ray photoelectron spectroscopy (XPS). The XPS signal was obtained from a PHI Quantera SXM apparatus from an Al Kα X-ray source operated at 25 W after the sample was sputter-cleaned with an Argon ion beam power and emission current set at 40 W and 4.025 mA, respectively. The binding energy scales of all XP spectra were calibrated by taking the C1s (~284.8 eV) as the reference. The peak fit analysis was performed using the XPSPEAK41 software application. The O1s spectra were fitted to examine the oxygen binding states. Near Gaussian peak shapes were used, the FWHM of the synthetic peak were fixed to 1.5–1.6 eV, and the binding energy of the synthetic peaks were not allowed to change from one spectrum to the other.
the control one. After the multilayer GI layer deposition, a post deposition annealing was performed at 300 °C in oxygen ambient for 30 min by a thermal furnace, in order to improve the quality of dielectrics film and fix the bulk defeats in the multilayer GI. After gate region formation, a 40-nm thick a-IGZO thin film was deposited as the channel layer by RF magnetron sputtering process using a target with the atomic ratio of In:Ga:Zn:O = 1:1:1:4 at room temperature. During the deposition, the flow rate of O2 and Ar was set at 1 and 20 sccm, respectively. The total gas pressure in the sputter chamber was controlled to be 0.4 Pa, while the optimization case of a-IGZO channel deposition was applied for device fabrication in this work. Then, the channel material was annealed by the thermal furnace at 300 °C in the oxygen atmosphere for 30 min. Afterward, in order to achieve a low work function and high conductivity metal contact, the source and drain electrodes were formed by 20-nm thick Ti and 120-nm thick Pt metal film stacks and patterned through the shadow mask with channel width (W) of 500 μm and length (L) of 50 μm. A detailed process flow chart and a three-dimensional (3D) view of the prepared samples are shown in Fig. 1. Electrical measurements were conducted in the dark chamber at room temperature using Agilent 4156C semiconductor parameter analyzer and 4284A precision LCR meter. Besides, the cross-sectional transmission electron microscope images were taken by JEM-2010F under an operating voltage of 200 kV with the sample prepared by
3. Results and discussion Fig. 2 shows the cross-sectional transmission electron microscope images of IGZO TFT with (a) HTS, (b) SHTS and (c) GHTS GI stacks, respectively, while the atomic force microscope images of the interfacial layer and the root-mean-square surface roughness values are also included. The IGZO channel and multilayer gate dielectric are examined by fast Fourier transform, where the diffraction image exhibits the amorphous phases. Besides, a TFT device structure with TaN metal-
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A. The value of μFE was extracted by the transconductance in the linear region (VD = 0.1 V). The threshold voltage was defined by VGS at constant normalized drain current (ID/(W/L)) of 10 nA. The DIT at the interface of gate dielectric/a-IGZO was calculated based on the SS value by the following Eq. (1) [13]:
SS⋅lg e C DIT = ⎜⎛ − 1⎟⎞⋅ OX 2 kT / q ⎝ ⎠ q
(1)
where k is the Boltzmann constant, T is the absolute temperature, q is the unit electron charge and COX is the gate dielectric capacitance per unit area. As a result, the SHTS GI device exhibits a lower S.S. of 93 mV/dec, a higher μFE of 37.8 cm2/Vs, a higher ION/IOFF of 7 × 107 and a lower DIT of 1.67 × 1012 eV−1 cm−2 compared with other samples. It suggests that the SiO2 interfacial layer shows a best interface condition for its high band offset and good material stability, which can further suppress the gate leakage current and surface roughness. In addition, there is a desirable positive threshold voltage and acceptable sub-threshold swing improvement for the GHTS GI sample. It can be attributed to that the Ga2O3 interfacial layer can reduce the frontchannel oxygen deficiency, which may lower the control barrier of channel. Nevertheless, the carrier mobility and driving current of the GHTS GI sample are not influenced by the suppressed carrier concentration. It may benefit from the lower surface roughness, which is caused by the interaction between front-channel and high-k GI. The output characteristics of the sample are also shown in Fig. 3(b) HTS, (c) SHTS and (d) GHTS GI stacks, respectively. The ION of all samples shows similar values, while the GHTS GI sample exhibits typical transistor characteristics and excellent linear/saturation behavior in enhancement mode. Since the HTS and SHTS sample may have a higher carrier concentration, the channel region of these two samples is not totally depleted, and the undepleted region will contribute the excess drain current in the linear operation region of the output characteristics. Fig. 3(e) and (f) show the capacitance-voltage (C–V) and current density-voltage (J–V) characteristics of Pt/Ti/GI stacks/TaN (Metal/Insulator/Metal) capacitor fabricated during the TFT process, respectively. The capacitance density of all the samples, measured at the frequency of 100 KHz, also shows a similar value which is about 0.493 μF/cm2 (HTS), 0.473 μF/cm2 (SHTS) and 0.481 μF/cm2 (GHTS), respectively. Besides, the effective dielectric constant of the HTS, SHTS and GHTS GI stacks is about 40.67, 39.55 and 40.22, respectively. It suggests that the influence of a 1-nm thick interfacial layer for the capacitance can be negligible. On the other hand, all the samples show a very low leakage current which means that the multilayer gate stacks can provide a good capability of gate control. In order to investigate the origin of this result, the chemical and structural evolution of the a-IGZO films with different interfacial layer were analyzed by XPS, calibrated by tacking the C1s (~284.8 eV) as the reference. The XPS spectra of O1s signal were shown in Fig. 4 to examine the oxygen binding states at the different locations of IGZO thin film: (a) HTS (near back-channel), (b) HTS (near front-channel), (c) SHTS (near back-channel), (d) SHTS (near front-channel), (e) GHTS (near back-channel) and (f) GHTS (near front-channel). The O1s signal is fitted by three nearly Gaussian distributions with the peak fitting software named XPSPEAK41, approximately centered at 530 ± 0.1 eV, 531 ± 0.3 eV and 532 ± 0.2 eV, respectively [14]. For the lowest binding energy peak located at 529.9 eV with a full-width half-maximum (FWHM) of 1.6 eV, the signal is denoted by oxygen-lattice bond, which is related to the O2– ions combined with the Ga, In, Zn atoms in the IGZO compound system. Then, the signal is denoted by oxygenhydroxide bond for the highest binding energy peak located at 531.8 eV with a FWHM of 1.6 eV. The peak is associated with the loosely
Fig. 2. The cross-sectional transmission electron microscope images of IGZO TFT with (a) HTS, (b) SHTS and (c) GHTS GI stacks, while the atomic force microscope images of the interfacial layer and the root-mean-square surface roughness values are also included.
gate, 3-nm thick SiO2, 30-nm thick TiO2, 40-nm thick HfO2 multilayer gate dielectric stack, interfacial layer, and the IGZO channel can be clearly observed. The interfacial layer between high-k dielectric and active channel layer plays an important role on the suppression of the interaction at the front-channel, which also can be proved by the atomic force microscope images and the values of the root-mean-square surface roughness for different interfacial layer engineering. Fig. 3(a) shows the transfer characteristics of TFT device with three types of GI stacks. The electrical parameters for all the samples including sub-threshold swing (S.S.), field-effect mobility (μFE), on/off current ratio (ION/IOFF), threshold voltage (VTH) and the interfacial trap density (DIT), are summarized in Table 1. The sub-threshold swing was determined by an increase decade in drain current (ID) from 1010 to 108
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Fig. 3. (a) The transfer characteristics of TFT device with three types of GI stacks and the output characteristics of the sample with (b) HTS, (c) SHTS and (d) GHTS GI stacks; (e) the capacitance-voltage (C–V) and (f) current density-voltage (J–V) characteristics of Pt/Ti/GI stacks/TaN capacitor fabricated during the TFT process.
amount of oxygen-hydroxide bond signal and a similar proportion of donor-like oxygen-vacancy bond (11%–15%) at the back-channel surface, which is easily excited into the charged states in the form of ionized oxygen vacancies (VO2+). On the contrary, the sample with HTS GI exhibits the highest proportion of donor-like oxygen-vacancy bond (15.76%) near the front-channel of a-IGZO film, while the sample with GHTS GI shows the lowest value (8.61%). As a whole, it means that the front-channel interfacial layer may be the main reason influencing the channel conductivity, while the incorporation of Ga3+ cation in Ga2O3 material could effectively suppress carrier generation in the a-IGZO due to its stronger chemical bonds with oxygen than zinc or indium ions [15]. To further clarify the mechanisms of the interface effects, Fig. 5 shows the energy band diagram of hetero-structure interface for the sample with (a) HTS, (b) SHTS and (c) GHTS GI stacks [16–18]. As shown in the band structure of HTS GI, the TiO2 has higher k value than HfO2, which can further lower the equivalent oxide thickness, but it suffers from high leakage current due to a very high conduction band offset (ΔEC) and a serious reliability problem caused by the Ti out-diffusion in the thermal process. Thus, the structure of HfO2/TiO2/SiO2 is
Table 1 Electrical performance of device with different GI stacks for comparison, including sub-threshold swing (S.S.), field effect mobility (μFE), on/off current ratio (ION/IOFF), threshold voltage (VTH), and the interfacial trap density (DIT). Gate insulator materials
SS (V/decade)
μEF (cm2/V·s)
ION/IOFF
VTH (V)
DIT (eV−1 cm−1)
HfO2/TiO2/ SiO2(HTS) SiO2/HfO2/TiO2/ SiO2(SHTS) Ga2O3/HfO2/TiO2/ SiO2(GHTS)
0.135
~30.5
~3 ∗ 106
−0.128
3.91 ∗ 1012
0.093
~37.8
~7 ∗ 107
0.065
1.67 ∗ 1012
0.097
~32.4
~2 ∗ 107
0.295
1.90 ∗ 1012
bounded oxygen at the surface of IGZO film, which can be terminated with the specific chemisorbed oxygen, such as CO2, absorbed O2, or absorbed H2O. For the middle binding energy component located at 531.1 eV with a FWHM of 1.5 eV, the signal is denoted by oxygen-vacancy bond. The peak of OV is attributed to O2– ions that are in oxygen deficient region of the IGZO matrix. All the samples show a negligible
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Fig. 4. Analysis of XPS O1s spectrum at the different location of IGZO thin film with different GI stacks: (a) HTS (near back-channel), (b) HTS (near front-channel), (c) SHTS (near back-channel), (d) SHTS (near front-channel), (e) GHTS (near back-channel) and (f) GHTS (near front-channel).
material, the SHTS sample and GHTS sample should exhibit a better hysteresis characteristic than the HTS sample. However, in the IGZO TFT device with SHTS or GHTS GI stacks, there are two interfacial surfaces existed at the interfaces of IGZO/interfacial layer (SiO2 or Ga2O3) and interfacial layer (SiO2 or Ga2O3)/HfO2. Both the interfaces increase the probability of electron trapping in TFT device and cause a higher hysteresis behavior. That is why the TFT with SHTS or GHTS GI stacks exhibited a larger change in threshold voltage as compared to the one only with a single IGZO/HfO2 interface in the TFT device with HTS GI, while all the TFT show the similar value of the DIT data. In addition, the reliability issue is also investigated. Fig. 7 shows threshold voltage shift of the three types of GI stacks versus stress time under (a) 1MV/cm positive gate bias stress and (b) -1MV/cm negative gate bias stress for aIGZO TFTs. It is found that the TFT with SHTS GI shows an excellent reliability characteristic under both positive and negative gate bias stress, compared to the ones with HTS or GHTS GI. This result indicates that the existence of stable SiO2 interfacial layer, which was not consumed by the channel layer or GI layer during the thermal processes,
proposed to lower the leakage current and suppress the out-diffusion by the band engineering. Then, for SHTS sample, a 1-nm thick SiO2 interfacial layer is added to further enlarge the conduction band offset from 2.39 eV to 4.27 eV and reduce the concentration of interface trap charge between HfO2 and IGZO channel. On the other hand, for GHTS sample, a 1-nm thick Ga2O3 interfacial layer is added to suppress potential interface reaction between the HfO2 and IGZO channel and lower the front channel oxygen deficiency for comparison. It seems that the sample with SHTS GI stacks exhibits a better electrical performance according to the Table 1. Fig. 6 shows the hysteresis characteristics of a-IGZO TFT with (a) HTS, (b) SHTS and (c) GHTS GI stacks. The hysteresis can reveal the phenomenon of electron trapping in the gate stack, the interface of front-channel and active layer. All the TFT devices exhibit an acceptable and similar value of hysteresis (< 105 mV). The multilayer GI structure can effectively improve the hysteresis characteristics by high conduction band offset of TiO2 and HfO2 hetero-structure. On the other hand, with a better interface characteristic of GI layer and channel
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Fig. 6. The hysteresis characteristics of a-IGZO TFT with (a) HTS, (b) SHTS and (c) GHTS GI stacks.
Fig. 5. Energy band diagram of hetero-structure interface for the sample with (a) HTS, (b) SHTS and (c) GHTS GI stacks.
which can be proved by the XPS results in the Fig. 4, the anomalous negative shift of VTH of GHTS sample is also induced by the additional interface and border traps in the gate stacks, while the influence of additional interface for the SHTS sample might be limited by its good material stability.
can effectively improve GI quality by reducing the interfacial trap density and suppressing the phenomenon of the interaction at the frontchannel. On the other hand, there is an anomalous negative shift of VTH for the sample with GHTS GI under negative gate bias stress. According to the physical model proposed in previous documents [19], the negative shift of VTH is mainly related to the presence of VO2+ in the aIGZO film, which may exist in shallow levels below the conduction band minimum and are derived from high concentration of natural vacancies that generate defect states near the valence band maximum. Due to the electron quasi-Fermi level locating within donor-like state levels of the n-channel a-IGZO TFT, more ionized oxygen vacancies, which may be accumulated at the front-channel and dielectric interface, may result in a more negative shift of VTH under negative gate bias stress. With a lower carrier concentration at the front-channel interface,
4. Conclusions The electrical characteristics, physical analysis and operation energy band model of a-IGZO TFTs with different interfacial layer for a multilayer GI structure (HfO2/TiO2/SiO2) are investigated in this work, The TFT device with Ga2O3 interfacial layer shows a desirable positive threshold voltage and acceptable electrical performance improvement. However, a more stable interfacial layer like SiO2, which will not be consumed by channel layer or GI layer during the thermal process, may further improve the electrical performance, interface quality and reliability characteristics.
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Fig. 7. Threshold voltage shift as a function of stress time under (a) positive gate bias stress and (b) negative gate bias stress for a-IGZO TFTs, including the sample with three types of GI stack.
Acknowledgment This work was performed at National Nano Device Laboratories (NDL) Taiwan and financially supported by the Ministry of Science and Technology, Taiwan, under Contract MOST 106-2221-E-009-107-MY3.
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