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Effect of mechanical stress induced by etch-stop nitride: impact on deep-submicron transistor performance
Microelectronics Reliability 42 (2002) 201–209 www.elsevier.com/locate/microrel
Effect of mechanical stress induced by etch-stop nitride: impact on deep-submicron transistor performance Shinya Ito *, Hiroaki Namba, Tsuyoshi Hirata, Koichi Ando, Shin Koyama, Nobuyuki Ikezawa, Tatsuya Suzuki, Takehiro Saitoh, Tadahiko Horiuchi Advanced CMOS Technology Group, ULSI Device Development Division, NEC Corporation, 1120 Shimokuzawa, Sagamihara, Kanagawa 229-1198, Japan Received 12 June 2001; received in revised form 13 September 2001
Abstract This paper reports that process-induced mechanical stress affects the performance of short-channel MOSFETs, and focuses on the effect of a plasma-enhanced CVD nitride contact-etch-stop layer. The stress in the channel region induced by the nitride layer changes transconductance ðGm Þ, thereby changing the device performance. When the nitride stress varies from þ300 MPa (tensile) to 1:4 GPa (compressive), NMOSFET performance degrades by up to 8% and PMOSFET performance improves up to 7%. These changes are caused by the modulation of the electron/hole mobilities, so controlling process-induced stress and considering this mobility change in a precise transistor model are necessary for deep-submicron transistor design. Ó 2002 Elsevier Science Ltd. All rights reserved.
1. Introduction Because recent MOS devices are being fabricated from a large variety of materials having very different mechanical properties, large amount of mechanical stress can be generated in a transistor. The stress which is generated in the shallow trench isolation (STI) step causes crystal defects in silicon and generates anomalous leakage current [1]. Thus, the STI process has been refined to decrease the stress caused by buried material in the trench [2]. The drive current is also affected by the mechanical stress. Even if the crystal defects are not generated in the device, a recent paper reported that a few hundred megapascals of STI-induced stress reduces the drive current of an NMOSFET by as much as 13% [3]. The transconductance has also been reported to be similarly affected by the silicide-induced stress in the source/drain region [4]. Some studies have investigated altering transistor performance by positively changing the stress in the channel [5].
*
Corresponding author. Tel.: +81-42-771-0710; fax: +81-42771-0938. E-mail address: [email protected] (S. Ito).
Silicon nitride is widely used in device fabrication and is well-known to have a high degree of stress. Depending on the deposition conditions, the nitride film can have gigapascal-order stress that is either tensile or compressive. In recent MOS devices, the nitride film is placed directly over the transistor for the following reason: Because the p–n junction in the source/drain region is very shallow, at the contact located on the edge of the active area (e.g., the contact in a small SRAM cell [6]), anomalous leakage current flows from the contact to the substrate when excess overetching is done during contact opening. Therefore an etch-stop layer is used so that the contact etching can be stopped at the surface of the silicon substrate. The main step of the etching is stopped in the etch-stop layer, and then the layer is carefully removed by an etching process that is not damaging to the substrate. Silicon nitride is generally used as this etch-stop layer. In particular, plasmaenhanced CVD (PECVD) nitride is more suitable than low-pressure CVD (LPCVD) nitride, because the hightemperature process (>700 °C) of LPCVD nitride causes the depletion in the gate electrode and degrades the device performance [7]. Although several studies have dealt with the influence of the stress and the hydrogen content in the nitride
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layer on the hot carrier reliability [8–10], very little has been reported about the ways in which device performance is affected by the etch-stop nitride stress. In this paper we discuss the performance of 0.13 lm CMOS devices having a variety of nitride etch-stop layers, and analyze the relationship between the performance and some properties of nitride films including mechanical stress.
flow rate, pressure, electrode gap, and high-frequency power. We focused in particular on the mechanical stress of the films because our preliminary study indicated that film stress is an important factor in the performance. A device without a nitride layer was also fabricated for reference. The device characteristics were evaluated at VG ¼ j1:2j V, VD ¼ j0:05j or j1:2j V. 3. Results and discussion 3.1. Dependence of device performance on nitride properties
2. Device fabrication Each of the CMOSFETs was fabricated by using 0.13 lm CMOS technology [11] and had a nitride contactetch-stop layer that was deposited by PECVD (Fig. 1). The optical thickness of the gate oxynitride was 1.9 nm and the gate polysilicon thickness was 0.15 lm. The minimum gate length of the transistor we evaluated was 0.09 lm and the transistor width was 10 lm. The sidewall spacer was a SiO2 /SiN/SiO2 structure. The nitride contact-etch-stop layer was 0.05 lm thick and the interlayer dielectric above the nitride was 0.62–0.78 lm thick. We evaluated devices having eight different types of nitride (Table 1), that were deposited using an SiH4 /N2 / He gas mixture at 550–600 °C. The nitride films having different properties were deposited by changing the gas
Fig. 1. Cross-sectional SEM photograph of a sample MOSFET.
The Ion –Ioff characteristic of a short-channel NMOSFET is degraded by the presence of a nitride layer, but that of a short-channel PMOSFET is improved (Fig. 2). As shown in Fig. 3, the Ion when the Ioff is 5 nA is closely correlated with the internal stress of the nitride. The nitride stress was determined by measuring the change in the bow of the wafer on which only the nitride film was deposited. When the nitride stress in an NMOSFET is 1.4 GPa (compressive), this performance measure (i.e. Ion @ Ioff ¼ 5nA) is 8% worse than it is when the stress is þ300 MPa (tensile), whereas the same stress difference in a PMOSFET improved this performance measure by 7%. Fig. 4 shows that there is no significant correlation between the MOSFET performance and the following other properties of the nitride: (i) film porosity, which correlates with the amount of Si in the film and is evaluated by measuring the refractive index, (ii) hydrogen content, which is determined from the transmission infrared spectra of N–H and Si–H bonds, and (iii) the amount of hydrogen incorporated into the device during the nitride deposition (i.e. hydrogen content in the plasma atmosphere, not in the nitride itself), which is evaluated by the partial pressure of SiH4 gas. These tendencies are the same in both NMOS and PMOSFETs. This variation of the Ion –Ioff characteristic is the result of the change of the Gm (Fig. 5). In Fig. 6, the Gm multiplied by the Lpoly is plotted in order to clearly distinguish the dependence of the Gm on the nitride film. For instance, the short-channel MOSFET with a large
Table 1 Physical properties of the nitride films used A B C D E F G H
Stress (MPa)
RI
H content (cm3 )
SiH4 pressure (Torr)
474:7 112:2 60.2 333.5 87:7 87:7 1405 329:1
2.043 2.019 2.047 2.021 1.914 1.978 2.057 2.135
5.30Eþ21 2.80Eþ21 3.30Eþ21 4.50Eþ21 1.00Eþ22 1.50Eþ22 3.50Eþ21 3.20Eþ21
2.21E02 1.71E02 2.49E02 4.76E02 2.99E02 2.51E02 3.61E02 3.22E02
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Fig. 2. Off-current vs. on-current. Devices with nitride films F and G are compared to the device without a nitride etch-stop layer.
Fig. 3. Dependence of the MOSFETs performance on the stress of nitride A–H.
compressive nitride A shows smaller Gm in the NMOSFET but larger one in the PMOSFET. The Gm variation is found to be dependent on the gate length and the difference among the nitride films is great in the shortchannel region. Interestingly, the order of the Gm in the long-channel region is opposite to that in the shortchannel region in the NMOSFET, whereas the Gm in the PMOSFET shows monotonic change. We can explain this tendency for NMOSFET in view of the dependence of the stress in the channel on the gate length, but there may be other factors for PMOSFET in addition to the stress. Besides, the Gm of the NMOSFET without nitride is larger than those of devices with nitride films (and vice versa in PMOSFET) and this result is also discussed in the later section.
3.2. The Gm change from nitride stress The Gm is expressed approximately as follows and depends on the carrier mobility ðlÞ and the capacitance of the gate dielectric ðCox Þ:
Gm ¼ oID =oVG ¼ ðW =LÞlCox VD Carrier mobility is dependent on the impurity profile and the mechanical stress in the channel region [12,13]. The Cox includes the capacitance of the depletion layer in the gate electrode. Three possible effects caused by stress are considered: (1) the gate depletion effect, (2) the impurity profile change, and (3) the carrier mobility change. First, the capacitance of the inversion layer is the same for all of the devices (Fig. 7). This result shows that the gate depletion is not dependent on the nitride film. Second, the impurity profile change is evaluated by the gateinduced drain leakage (GIDL) current and the draininduced barrier lowering (DIBL). The GIDL, which depends on the electrical field across the gate oxide, is influenced by the impurity concentration in the drain overlapped by the gate. The DIBL depends on the effective channel length and indirectly shows the change of the impurity profile. These two measures do not vary with the nitride (Fig. 8) and we can say that the impurity profile does not change from the nitride stress. In contrast to the transient enhanced diffusion (TED) of the channel
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Fig. 4. Dependence of the MOSFETs performance on the physical index of nitride A–H.
Fig. 5. The device performance and the transconductance of the NMOSFET with/without the nitride layer.
dopant in the annealing step for activating the source/ drain dopant [14], the interstitial Si does not exist at the deposition step of the nitride, because there is no ion implantation step and the high-temperature annealing (>1000 °C) is completed before the nitride deposition. Thus the redistribution of the dopant is unlikely to occur. Consequently, we believe that the Gm is changed by the carrier mobility depending on the nitride stress. 3.3. Threshold voltage and subthreshold slope The threshold voltage ðVth Þ dependence on the nitride is different between an NMOSFET and a PMOSFET
(Fig. 9). In an NMOSFET, the Vth in the long channel is the same for all the devices but splits in the shortchannel region. This tendency is similar to the case of the TED [15]. One might suspect that there is a redistribution of the channel impurities towards the channel edge, but it should be noted that the minimum gate length ðLmin Þ at which the Vth drops sharply is not changed, unlike the TED case. Although we cannot explain this change of Vth , it may be possible that the potential between the source and the channel may be changed by the nitride. In the PMOSFET, the longchannel Vth is varied with the nitride. Because hydrogen enhances the diffusion of boron [16], this Vth variation
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Fig. 6. Lpoly dependence of the maximum transconductance multiplied by Lpoly to emphasize the difference.
find clear correlation between the PMOSFET performance and the hydrogen content. This question must await more detailed study. Though the subthreshold slope (SS) depends slightly on the nitride (Fig. 10), the value does not clearly correlate with the stress and the hydrogen content. The SS fails to explain the large performance change in both types of MOSFETs. 3.4. Mobility and local stress in channel area
Fig. 7. Capacitance in the inversion layer of the short-channel NMOSFET.
might be related to hydrogen-induced boron penetration. But, as shown in the previous section, we could not
It is well known that electron mobility is decreased with increasing compressive stress in an NMOSFET, whereas the hole mobility in a PMOSFET is increased [12,13]. One might think that a large compressive nitride layer causes tensile stress in the silicon and increases the electron mobility in an NMOSFET. Indeed, the effective mobility estimated from the long-channel NMOSFET is consistent with this prediction (Fig. 11). When
Fig. 8. Lpoly dependence of the DIBL and the GIDL of the NMOSFET. DIBL is defined by ðVG @ ID fixed ðVD ¼ 0:05 VÞ VG @ ID fixed ðVD ¼ 1:2 VÞÞ=1:15.
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Fig. 9. Threshold voltage roll-off of the MOSFETs. Vth is defined by the VG at ID ¼ W =L 0:1 lA at VD ¼ 1:2 V.
Fig. 10. Subthreshold slope of the MOSFETs.
compressive nitride is applied, the effective mobility becomes large. We cannot evaluate the effective mobility in short-channel devices, but the Gm indicates that the electron mobility is small for a large compressive nitride layer (Fig. 5). This means that a compressive nitride layer causes compressive stress in a short-channel MOSFET. The point is that the local stress underneath the gate in a short-channel MOSFET seems to be different from that in a long-channel MOSFET. To clarify how the strain in the channel area affects the electrical characteristics in the MOSFET, we carried out numerical stress analysis on the internal strain field in the MOSFET by the finite element method. The analysis code used in the calculation was ANSYS. The calculation was based on the following assumptions: (a) all the materials comprising the device are isotropic and linearly elastic solids; (b) analysis modeling is done for one-half of the cross-section of the MOSFET which is
parallel to the channel and is based on the two-dimensional (2D) plane strain condition; (c) the initial strain of silicon regions such as the source/drain and the channel is assumed to be zero. The boundary conditions, dimensions and geometry of the model are illustrated in Fig. 12. The node and element numbers for the model are 30931-51051 and 30632-50703, respectively. The strain field of the MOSFET can be derived from elastic constants of each material and the source of stress generation. Young’s moduli we used are as follows: SiO2 (66 GPa), poly-Si (170 GPa), SiN (392 GPa), CoSi2 (280 GPa), BPSG (120 GPa), Si substrate (170 GPa). Poisson’s ratio is fixed at 0.3 for all the materials. In this study, the stress of films deposited on a Si substrate are assumed to be the source of stress generation. For CoSi2 and the gate dielectric, the film stress was calculated from the difference in the thermal expansion from the deposition temperature to room temperature. For the
S. Ito et al. / Microelectronics Reliability 42 (2002) 201–209
Fig. 11. Nitride-stress dependence of the maximum effective mobility in the inversion layer of the NMOSFET. These values were determined from the drain conductance and gate-channel capacitance at L=W ¼ 100=100 lm. The mobility of the device without a nitride film is also shown.
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Fig. 13. Process-induced strain calculated using ANSYS for the short-channel MOSFET. The gate length is 0.09 lm and nitride stress is 300 MPa (compressive). The strain is indicated as a 1000 times value in the figure.
Fig. 14. Simulated strain dependence on the distance from the gate edge and the gate length. Nitride stress is fixed at 300 MPa (compressive).
Fig. 12. The device structure for the stress simulation with the boundary conditions, dimensions and geometry.
other materials, the film stress at room temperature was qualified using Si substrate curvature techniques, because intrinsic stress was generated during film deposition. As an example, the calculated strain distribution is shown for the device (Lpoly ¼ 0:09 lm) with a 300 MPa nitride in Fig. 13. In the case of a 300 MPa nitride, the strain under the gate varies from 5:8 104 to
7:2 105 (i.e., toward relatively tensile) with increasing the gate length from 0.09 to 10 lm (Fig. 14). For the Lpoly of 0.09 lm, the device without nitride has a relatively large tensile stress under the gate and the stress value is equivalent to that of the device with a 600 MPa (tensile) nitride (Fig. 15). This explains that the Gm of the device without nitride is larger than those of the devices with nitride A–D (Fig. 5). As shown in Fig. 16, for the device with a 10 lm gate, the stress under the gate is relatively compressive when the nitride stress is tensile, and this result explains that the electron mobility obtained by the long-channel device is small for a tensile nitride (Fig. 11). Small mobility of the device without nitride can also be explained in the same manner. The
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Fig. 15. Simulated strain dependence on the distance from the center of the gate electrode for the devices with/without the nitride. The gate length is fixed at 0.09 lm.
compressive nitride causes more compressive stress underneath the gate electrode than the tensile nitride does. A compressive nitride layer decreases the electron mobility in the short-channel MOSFET compared to the tensile nitride. Whereas a large amount of the nitride over the gate electrode is dominant in the stress under the gate in the long-channel MOSFET, the nitride placed on the sidewall portion dominates the channel stress in the short-channel MOSFET (Fig. 17). Thus, the stress calculation supports the explanation of the performance variation caused by the nitride layer for the short/long-channel NMOSFET and for the short-channel PMOSFET. However we cannot completely explain the PMOSFET performance dependence on the nitride at this time, because there may be other factors such as the hydrogen content which relates to the performance for the long-channel region.
4. Conclusion
Fig. 16. Dependence of simulated strain under the gate on the nitride stress and the gate length.
dependence of the stress in the channel region on the nitride stress is inverted at submicron gate lengths. In particular, for the device with a 0.09 lm gate, the
The mechanical stress induced by the nitride etch-stop layer greatly affects the device performance. This effect is opposite in NMOS/PMOSFETs and also depends on the gate length. The performance change is particularly remarkable in the short-channel device. In the NMOSFET with a tensile nitride, the stress under the gate becomes more tensile and the performance improves in the short-channel region, but the stress under the gate becomes more compressive and the performance degrades in the long-channel region. The PMOSFET shows the opposite dependence of the performance on the nitride stress in the short-channel region. Thus, controlling the mechanical stress in the channel and being able to take the stress-induced mobility change into consideration when modeling short-channel transistors are crucial to deep-submicron transistor design.
Fig. 17. Schematic drawing to show the nitride stress effect on the channel region.
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References [1] Ohzone T, Iwata H. Nonuniform reverse-breakdown characteristics of nþ -diodes fabricated by LOCOS and trench isolation. IEEE Trans Electron Dev 1994;41: 2477–80. [2] Park MH, Hong SH, Hong SJ, Park T, Song S, Park JH, et al. Stress minimization in deep sub-micron full CMOS devices by using an optimized combination of the trench filling CVD oxides. In: Technical Digest of International Electron Devices Meeting, 1997. p. 669–72. [3] Scott G, Lutze J, Rubin M, Nouri F, Manley M. NMOS drive current reduction caused by transistor layout and trench isolation induced stress. In: Technical Digest of International Electron Devices Meeting, 1999. p. 827–30. [4] Steegen A, Stucchi M, Lauwers A, Maex K. Silicide induced pattern density and orientation dependent transconductance in MOS transistors. In: Technical Digest of International Electron Devices Meeting, 1999. p. 497–500. [5] Welser J, Hoyt JL, Takagi S, Gibbons JF. Strain dependence of the performance enhancement in strained-Si nMOSFETs. In: Technical Digest of International Electron Devices Meeting, 1994. p. 373–6. [6] Masuoka S, Noda K, Ito S, Matsui K, Imai K, Yasuzato N, et al. A 0.99-lm2 loadless four-transistor SRAM cell in 0.13-lm generation CMOS technology. In: Digest of Technical Papers of Symposium on VLSI Technology, 2000. p. 164–5. [7] Inaba S, Murakoshi A, Tanaka M, Takagi MT, Koyama H, Koike H, et al. Increase of parasitic resistance of shallow pþ extension with SiN sidewall process by hydrogen passivation of boron and its improvement by preamorphization for sub-0.25 lm pMOSFETs. In: Digest of Technical Papers of Symposium on VLSI Technology, 1996. p. 168–9. [8] Mitsuhashi J, Nakao S, Matsukawa T. Mechanical stress and hydrogen effects on hot carrier injection. In: Technical
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Digest of International Electron Devices Meeting, 1986. p. 386–9. Stinebaugh WH, Harrus Jr A, Knolle WR. Correlation of Gm degradation of submicrometer MOSFET’s with refractive index and mechanical stress of encapsulation materials. IEEE Trans Electron Dev 1989;36(3):542–7. Tokitoh S, Uchida H, Shibusawa K, Murakami N, Nakamura T, Aoki H, et al. Enhancement of hot-carrier induced degradation under low gate voltage stress due to hydrogen for NMOSFETs with SiN films. In: Technical Digest of International Electron Devices Meeting, 1997. p. 307–11. Imai K, Yamaguchi K, Kudo T, Kimizuka N, Onishi H, Ono A, et al. CMOS device optimization for systemon-a-chip applications. In: Technical Digest of International Electron Devices Meeting, 2000. p. 455–8. Momose HS, Morimoto T, Yamabe K, Iwai H. Relationship between mobility and residual-mechanical-stress as measured by Raman spectroscopy for nitrided-oxide-gate MOSFETs. In: Technical Digest of International Electron Devices Meeting, 1990. p. 65–8. Tsaur BY, Fan JCC, Geis MW. Stress-enhanced carrier mobility in zone melting recrystallized polycrystalline Si films on SiO2 -coated substrates. Appl Phys Lett 1982; 40(4):322–4. Sedgwick TO, Michel AE, Deline VR, Cohen SA, Lasky JB. Transient boron diffusion in ion-implanted crystalline and amorphous silicon. J Appl Phys 1988;63:1452– 63. Hanafi H, Noble WP, Bass RS, Varahramyan K, Lii Y, Dally AJ. A model for anomalous short-channel behavior in MOSFETs. IEEE Electron Dev Lett 1993;14(2):575–7. Aoyama T, Suzuki K, Tashiro H, Tada Y, Kataoka Y, Arimoto H, et al. Hydrogen-enhancing boron penetration in p-MOS devices during SiO2 chemical vapor deposition. In: Extended Abstracts of the International Conference on Solid State Devices and Materials, 1998. p. 16–7.
Effect of mechanical stress induced by etch-stop nitride: impact on deep-submicron transistor performance Shinya Ito *, Hiroaki Namba, Tsuyoshi Hirata, Koichi Ando, Shin Koyama, Nobuyuki Ikezawa, Tatsuya Suzuki, Takehiro Saitoh, Tadahiko Horiuchi Advanced CMOS Technology Group, ULSI Device Development Division, NEC Corporation, 1120 Shimokuzawa, Sagamihara, Kanagawa 229-1198, Japan Received 12 June 2001; received in revised form 13 September 2001
Abstract This paper reports that process-induced mechanical stress affects the performance of short-channel MOSFETs, and focuses on the effect of a plasma-enhanced CVD nitride contact-etch-stop layer. The stress in the channel region induced by the nitride layer changes transconductance ðGm Þ, thereby changing the device performance. When the nitride stress varies from þ300 MPa (tensile) to 1:4 GPa (compressive), NMOSFET performance degrades by up to 8% and PMOSFET performance improves up to 7%. These changes are caused by the modulation of the electron/hole mobilities, so controlling process-induced stress and considering this mobility change in a precise transistor model are necessary for deep-submicron transistor design. Ó 2002 Elsevier Science Ltd. All rights reserved.
1. Introduction Because recent MOS devices are being fabricated from a large variety of materials having very different mechanical properties, large amount of mechanical stress can be generated in a transistor. The stress which is generated in the shallow trench isolation (STI) step causes crystal defects in silicon and generates anomalous leakage current [1]. Thus, the STI process has been refined to decrease the stress caused by buried material in the trench [2]. The drive current is also affected by the mechanical stress. Even if the crystal defects are not generated in the device, a recent paper reported that a few hundred megapascals of STI-induced stress reduces the drive current of an NMOSFET by as much as 13% [3]. The transconductance has also been reported to be similarly affected by the silicide-induced stress in the source/drain region [4]. Some studies have investigated altering transistor performance by positively changing the stress in the channel [5].
*
Corresponding author. Tel.: +81-42-771-0710; fax: +81-42771-0938. E-mail address: [email protected] (S. Ito).
Silicon nitride is widely used in device fabrication and is well-known to have a high degree of stress. Depending on the deposition conditions, the nitride film can have gigapascal-order stress that is either tensile or compressive. In recent MOS devices, the nitride film is placed directly over the transistor for the following reason: Because the p–n junction in the source/drain region is very shallow, at the contact located on the edge of the active area (e.g., the contact in a small SRAM cell [6]), anomalous leakage current flows from the contact to the substrate when excess overetching is done during contact opening. Therefore an etch-stop layer is used so that the contact etching can be stopped at the surface of the silicon substrate. The main step of the etching is stopped in the etch-stop layer, and then the layer is carefully removed by an etching process that is not damaging to the substrate. Silicon nitride is generally used as this etch-stop layer. In particular, plasmaenhanced CVD (PECVD) nitride is more suitable than low-pressure CVD (LPCVD) nitride, because the hightemperature process (>700 °C) of LPCVD nitride causes the depletion in the gate electrode and degrades the device performance [7]. Although several studies have dealt with the influence of the stress and the hydrogen content in the nitride
0026-2714/02/$ - see front matter Ó 2002 Elsevier Science Ltd. All rights reserved. PII: S 0 0 2 6 - 2 7 1 4 ( 0 1 ) 0 0 2 3 8 - 4
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layer on the hot carrier reliability [8–10], very little has been reported about the ways in which device performance is affected by the etch-stop nitride stress. In this paper we discuss the performance of 0.13 lm CMOS devices having a variety of nitride etch-stop layers, and analyze the relationship between the performance and some properties of nitride films including mechanical stress.
flow rate, pressure, electrode gap, and high-frequency power. We focused in particular on the mechanical stress of the films because our preliminary study indicated that film stress is an important factor in the performance. A device without a nitride layer was also fabricated for reference. The device characteristics were evaluated at VG ¼ j1:2j V, VD ¼ j0:05j or j1:2j V. 3. Results and discussion 3.1. Dependence of device performance on nitride properties
2. Device fabrication Each of the CMOSFETs was fabricated by using 0.13 lm CMOS technology [11] and had a nitride contactetch-stop layer that was deposited by PECVD (Fig. 1). The optical thickness of the gate oxynitride was 1.9 nm and the gate polysilicon thickness was 0.15 lm. The minimum gate length of the transistor we evaluated was 0.09 lm and the transistor width was 10 lm. The sidewall spacer was a SiO2 /SiN/SiO2 structure. The nitride contact-etch-stop layer was 0.05 lm thick and the interlayer dielectric above the nitride was 0.62–0.78 lm thick. We evaluated devices having eight different types of nitride (Table 1), that were deposited using an SiH4 /N2 / He gas mixture at 550–600 °C. The nitride films having different properties were deposited by changing the gas
Fig. 1. Cross-sectional SEM photograph of a sample MOSFET.
The Ion –Ioff characteristic of a short-channel NMOSFET is degraded by the presence of a nitride layer, but that of a short-channel PMOSFET is improved (Fig. 2). As shown in Fig. 3, the Ion when the Ioff is 5 nA is closely correlated with the internal stress of the nitride. The nitride stress was determined by measuring the change in the bow of the wafer on which only the nitride film was deposited. When the nitride stress in an NMOSFET is 1.4 GPa (compressive), this performance measure (i.e. Ion @ Ioff ¼ 5nA) is 8% worse than it is when the stress is þ300 MPa (tensile), whereas the same stress difference in a PMOSFET improved this performance measure by 7%. Fig. 4 shows that there is no significant correlation between the MOSFET performance and the following other properties of the nitride: (i) film porosity, which correlates with the amount of Si in the film and is evaluated by measuring the refractive index, (ii) hydrogen content, which is determined from the transmission infrared spectra of N–H and Si–H bonds, and (iii) the amount of hydrogen incorporated into the device during the nitride deposition (i.e. hydrogen content in the plasma atmosphere, not in the nitride itself), which is evaluated by the partial pressure of SiH4 gas. These tendencies are the same in both NMOS and PMOSFETs. This variation of the Ion –Ioff characteristic is the result of the change of the Gm (Fig. 5). In Fig. 6, the Gm multiplied by the Lpoly is plotted in order to clearly distinguish the dependence of the Gm on the nitride film. For instance, the short-channel MOSFET with a large
Table 1 Physical properties of the nitride films used A B C D E F G H
Stress (MPa)
RI
H content (cm3 )
SiH4 pressure (Torr)
474:7 112:2 60.2 333.5 87:7 87:7 1405 329:1
2.043 2.019 2.047 2.021 1.914 1.978 2.057 2.135
5.30Eþ21 2.80Eþ21 3.30Eþ21 4.50Eþ21 1.00Eþ22 1.50Eþ22 3.50Eþ21 3.20Eþ21
2.21E02 1.71E02 2.49E02 4.76E02 2.99E02 2.51E02 3.61E02 3.22E02
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Fig. 2. Off-current vs. on-current. Devices with nitride films F and G are compared to the device without a nitride etch-stop layer.
Fig. 3. Dependence of the MOSFETs performance on the stress of nitride A–H.
compressive nitride A shows smaller Gm in the NMOSFET but larger one in the PMOSFET. The Gm variation is found to be dependent on the gate length and the difference among the nitride films is great in the shortchannel region. Interestingly, the order of the Gm in the long-channel region is opposite to that in the shortchannel region in the NMOSFET, whereas the Gm in the PMOSFET shows monotonic change. We can explain this tendency for NMOSFET in view of the dependence of the stress in the channel on the gate length, but there may be other factors for PMOSFET in addition to the stress. Besides, the Gm of the NMOSFET without nitride is larger than those of devices with nitride films (and vice versa in PMOSFET) and this result is also discussed in the later section.
3.2. The Gm change from nitride stress The Gm is expressed approximately as follows and depends on the carrier mobility ðlÞ and the capacitance of the gate dielectric ðCox Þ:
Gm ¼ oID =oVG ¼ ðW =LÞlCox VD Carrier mobility is dependent on the impurity profile and the mechanical stress in the channel region [12,13]. The Cox includes the capacitance of the depletion layer in the gate electrode. Three possible effects caused by stress are considered: (1) the gate depletion effect, (2) the impurity profile change, and (3) the carrier mobility change. First, the capacitance of the inversion layer is the same for all of the devices (Fig. 7). This result shows that the gate depletion is not dependent on the nitride film. Second, the impurity profile change is evaluated by the gateinduced drain leakage (GIDL) current and the draininduced barrier lowering (DIBL). The GIDL, which depends on the electrical field across the gate oxide, is influenced by the impurity concentration in the drain overlapped by the gate. The DIBL depends on the effective channel length and indirectly shows the change of the impurity profile. These two measures do not vary with the nitride (Fig. 8) and we can say that the impurity profile does not change from the nitride stress. In contrast to the transient enhanced diffusion (TED) of the channel
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Fig. 4. Dependence of the MOSFETs performance on the physical index of nitride A–H.
Fig. 5. The device performance and the transconductance of the NMOSFET with/without the nitride layer.
dopant in the annealing step for activating the source/ drain dopant [14], the interstitial Si does not exist at the deposition step of the nitride, because there is no ion implantation step and the high-temperature annealing (>1000 °C) is completed before the nitride deposition. Thus the redistribution of the dopant is unlikely to occur. Consequently, we believe that the Gm is changed by the carrier mobility depending on the nitride stress. 3.3. Threshold voltage and subthreshold slope The threshold voltage ðVth Þ dependence on the nitride is different between an NMOSFET and a PMOSFET
(Fig. 9). In an NMOSFET, the Vth in the long channel is the same for all the devices but splits in the shortchannel region. This tendency is similar to the case of the TED [15]. One might suspect that there is a redistribution of the channel impurities towards the channel edge, but it should be noted that the minimum gate length ðLmin Þ at which the Vth drops sharply is not changed, unlike the TED case. Although we cannot explain this change of Vth , it may be possible that the potential between the source and the channel may be changed by the nitride. In the PMOSFET, the longchannel Vth is varied with the nitride. Because hydrogen enhances the diffusion of boron [16], this Vth variation
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Fig. 6. Lpoly dependence of the maximum transconductance multiplied by Lpoly to emphasize the difference.
find clear correlation between the PMOSFET performance and the hydrogen content. This question must await more detailed study. Though the subthreshold slope (SS) depends slightly on the nitride (Fig. 10), the value does not clearly correlate with the stress and the hydrogen content. The SS fails to explain the large performance change in both types of MOSFETs. 3.4. Mobility and local stress in channel area
Fig. 7. Capacitance in the inversion layer of the short-channel NMOSFET.
might be related to hydrogen-induced boron penetration. But, as shown in the previous section, we could not
It is well known that electron mobility is decreased with increasing compressive stress in an NMOSFET, whereas the hole mobility in a PMOSFET is increased [12,13]. One might think that a large compressive nitride layer causes tensile stress in the silicon and increases the electron mobility in an NMOSFET. Indeed, the effective mobility estimated from the long-channel NMOSFET is consistent with this prediction (Fig. 11). When
Fig. 8. Lpoly dependence of the DIBL and the GIDL of the NMOSFET. DIBL is defined by ðVG @ ID fixed ðVD ¼ 0:05 VÞ VG @ ID fixed ðVD ¼ 1:2 VÞÞ=1:15.
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Fig. 9. Threshold voltage roll-off of the MOSFETs. Vth is defined by the VG at ID ¼ W =L 0:1 lA at VD ¼ 1:2 V.
Fig. 10. Subthreshold slope of the MOSFETs.
compressive nitride is applied, the effective mobility becomes large. We cannot evaluate the effective mobility in short-channel devices, but the Gm indicates that the electron mobility is small for a large compressive nitride layer (Fig. 5). This means that a compressive nitride layer causes compressive stress in a short-channel MOSFET. The point is that the local stress underneath the gate in a short-channel MOSFET seems to be different from that in a long-channel MOSFET. To clarify how the strain in the channel area affects the electrical characteristics in the MOSFET, we carried out numerical stress analysis on the internal strain field in the MOSFET by the finite element method. The analysis code used in the calculation was ANSYS. The calculation was based on the following assumptions: (a) all the materials comprising the device are isotropic and linearly elastic solids; (b) analysis modeling is done for one-half of the cross-section of the MOSFET which is
parallel to the channel and is based on the two-dimensional (2D) plane strain condition; (c) the initial strain of silicon regions such as the source/drain and the channel is assumed to be zero. The boundary conditions, dimensions and geometry of the model are illustrated in Fig. 12. The node and element numbers for the model are 30931-51051 and 30632-50703, respectively. The strain field of the MOSFET can be derived from elastic constants of each material and the source of stress generation. Young’s moduli we used are as follows: SiO2 (66 GPa), poly-Si (170 GPa), SiN (392 GPa), CoSi2 (280 GPa), BPSG (120 GPa), Si substrate (170 GPa). Poisson’s ratio is fixed at 0.3 for all the materials. In this study, the stress of films deposited on a Si substrate are assumed to be the source of stress generation. For CoSi2 and the gate dielectric, the film stress was calculated from the difference in the thermal expansion from the deposition temperature to room temperature. For the
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Fig. 11. Nitride-stress dependence of the maximum effective mobility in the inversion layer of the NMOSFET. These values were determined from the drain conductance and gate-channel capacitance at L=W ¼ 100=100 lm. The mobility of the device without a nitride film is also shown.
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Fig. 13. Process-induced strain calculated using ANSYS for the short-channel MOSFET. The gate length is 0.09 lm and nitride stress is 300 MPa (compressive). The strain is indicated as a 1000 times value in the figure.
Fig. 14. Simulated strain dependence on the distance from the gate edge and the gate length. Nitride stress is fixed at 300 MPa (compressive).
Fig. 12. The device structure for the stress simulation with the boundary conditions, dimensions and geometry.
other materials, the film stress at room temperature was qualified using Si substrate curvature techniques, because intrinsic stress was generated during film deposition. As an example, the calculated strain distribution is shown for the device (Lpoly ¼ 0:09 lm) with a 300 MPa nitride in Fig. 13. In the case of a 300 MPa nitride, the strain under the gate varies from 5:8 104 to
7:2 105 (i.e., toward relatively tensile) with increasing the gate length from 0.09 to 10 lm (Fig. 14). For the Lpoly of 0.09 lm, the device without nitride has a relatively large tensile stress under the gate and the stress value is equivalent to that of the device with a 600 MPa (tensile) nitride (Fig. 15). This explains that the Gm of the device without nitride is larger than those of the devices with nitride A–D (Fig. 5). As shown in Fig. 16, for the device with a 10 lm gate, the stress under the gate is relatively compressive when the nitride stress is tensile, and this result explains that the electron mobility obtained by the long-channel device is small for a tensile nitride (Fig. 11). Small mobility of the device without nitride can also be explained in the same manner. The
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Fig. 15. Simulated strain dependence on the distance from the center of the gate electrode for the devices with/without the nitride. The gate length is fixed at 0.09 lm.
compressive nitride causes more compressive stress underneath the gate electrode than the tensile nitride does. A compressive nitride layer decreases the electron mobility in the short-channel MOSFET compared to the tensile nitride. Whereas a large amount of the nitride over the gate electrode is dominant in the stress under the gate in the long-channel MOSFET, the nitride placed on the sidewall portion dominates the channel stress in the short-channel MOSFET (Fig. 17). Thus, the stress calculation supports the explanation of the performance variation caused by the nitride layer for the short/long-channel NMOSFET and for the short-channel PMOSFET. However we cannot completely explain the PMOSFET performance dependence on the nitride at this time, because there may be other factors such as the hydrogen content which relates to the performance for the long-channel region.
4. Conclusion
Fig. 16. Dependence of simulated strain under the gate on the nitride stress and the gate length.
dependence of the stress in the channel region on the nitride stress is inverted at submicron gate lengths. In particular, for the device with a 0.09 lm gate, the
The mechanical stress induced by the nitride etch-stop layer greatly affects the device performance. This effect is opposite in NMOS/PMOSFETs and also depends on the gate length. The performance change is particularly remarkable in the short-channel device. In the NMOSFET with a tensile nitride, the stress under the gate becomes more tensile and the performance improves in the short-channel region, but the stress under the gate becomes more compressive and the performance degrades in the long-channel region. The PMOSFET shows the opposite dependence of the performance on the nitride stress in the short-channel region. Thus, controlling the mechanical stress in the channel and being able to take the stress-induced mobility change into consideration when modeling short-channel transistors are crucial to deep-submicron transistor design.
Fig. 17. Schematic drawing to show the nitride stress effect on the channel region.
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