- Email: [email protected]
The impact of process-induced mechanical stress on CMOS buffer design using multi-fingered devices
Microelectronics Reliability 53 (2013) 379–385
Contents lists available at SciVerse ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
The impact of process-induced mechanical stress on CMOS buffer design using multi-fingered devices Naushad Alam, Bulusu Anand, S. Dasgupta ⇑ Microelectronics and VLSI Group, ECE Department, Indian Institute of Technology Roorkee, Roorkee 247 667, India
a r t i c l e
i n f o
Article history: Received 7 June 2012 Received in revised form 9 August 2012 Accepted 18 September 2012 Available online 15 October 2012
a b s t r a c t In this paper we propose a modified model of logical effort for designing optimized buffers in multifingered layout scenario in the presence of process induced mechanical stress. It is observed that mechanical stresses induced by tensile and compressive Etch Stop Liner (t-ESL and c-ESL), embedded SiGe (eSiGe) and Shallow Trench Isolation (STI) are not uniform in all the fingers sharing an active region. As a result there is an unaccounted change in the drive current with the number of fingers; thereby causing an unaccounted change in the performance of logic gates implemented using multi-fingered layouts. We explore the impact of mechanical stress induced variability in inverters with multi-fingered devices and derive relationship between the logical effort (LE) and number of fingers (NFs). We use this relationship for predicting CMOS buffer delays more accurately and thus reducing the need for post-layout resizing of their transistors. Ó 2012 Elsevier Ltd. All rights reserved.
1. Introduction Deep submicron technology faces several process and performance related challenges which pose as a roadblock for miniaturization of the transistors [1]. The rate of supply voltage scaling has been reduced to maintain a required gate overdrive to meet performance requirement. This has resulted into increased lateral as well as transverse electric field in the channel. Also channel doping requirement in modern devices is very high to suppress short channel effects. Therefore, increased electric field and high doping in the channel results into degraded carrier mobility. Strain engineering has helped process engineers to makeup for this loss [2]. Mobility enhancement through strain engineering has emerged as an attractive solution for the device performance increase commensurately with dimensional scaling. Strain engineering delivers a performance gain that is equivalent to generations of technology scaling [3]. Therefore, it has become an integral part of a stateof-the-art CMOS process flow since its inception at 90 nm technology node [4,5]. Over a decade, various strain engineering techniques [6] have been proposed and are being used for introducing favourable stress [7] in the channel of a transistor. On a standard wafer with orientation (1 0 0)/h1 1 0i, for electron mobility (NMOSFET), tensile stress in the longitudinal and transverse direction and compressive stress in the vertical (to the wafer plane) direction is beneficial. On the other hand, compressive
⇑ Corresponding author. Tel./fax: +91 1332 285666. E-mail addresses: [email protected] (N. Alam), [email protected] (B. Anand), [email protected] (S. Dasgupta). 0026-2714/$ - see front matter Ó 2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.microrel.2012.09.011
stress in the longitudinal direction and tensile stress in the transverse and vertical direction improves the hole mobility (PMOSFET). Favorable stress itself in the channel is beneficial; however, the layout-dependent variability due to the use of stressors is a problem. Stress introduced in the channel through Stress Memorization (SMT), gate metal, and spacer material is least dependent on the layout. But, other major stressors that are essentially used in modern technologies add to the variability issues. Stress induced in the channel of a transistor through stressors like tensile/compressive Etch Stop Liner (t/c-ESL), embedded Silicon–Germanium/Carbon (eSiGe/eSiC) source/drain depends on various layout parameters such as source/drain length (LSD), poly-pitch (LPP), number of fingers (NFs) sharing an active region and ESL boundary [8–10]. Apart from the intentional sources of stress mentioned above, stress originating from Shallow Trench Isolation (STI) is inherent in the process technology and adds to the layout-dependent effects (LDEs) variability due to the use of stressors. LDE variability due to the use of stressors has led to various modeling and optimization issues at circuit and physical design stages [9,11–13]. While, most of the modeling and optimization work consider the average stress in a single finger in isolated or nested configuration, the impact of number of fingers (NFs) on the drive current of strain engineered multi-fingered devices remains unexplored. It has been reported that in nested configuration the stress in all the fingers are not equal and the drive current of a finger depends on the position of the finger in a nested layout [8]. The issue, that we intend to study and address in this paper, originates from this very fact that there is an unaccounted change in the drive current of fingers (of equal width) sharing an active region depending on the position of the finger and number of fingers
380
N. Alam et al. / Microelectronics Reliability 53 (2013) 379–385
(NFs) sharing an active region in a multi-fingered layout. Recently, the impact of NF on a multi-fingered device performance has been reported in [12,14] while considering only STI stress. However, none of the above work proposes a model that relates the effective drive current and number of fingers in multi-fingered devices. In this paper we investigate and model the number of fingers dependent stress-induced drive current and logical effort variability in multi-fingered layouts and its implication on CMOS buffer design. Buffers are widely employed to drive highly capacitive loads, and hence they frequently lie in the critical path. For this reason, it is important to understand how their delay is affected by LDE variability due to the use of stressors. We analyze the delay variability as a function of the number of stages N and the number of fingers NF in multi-fingered devices. We propose a modified model of CMOS buffer delay in terms of modified logical effort of inverters designed using multi-fingered devices. We organize our paper as follows: In Section 2 we describe our TCAD simulation setup. In Section 3 we study the variations in the channel stress and effective drive current of multi-fingered devices quantitatively and derive a physics based semi-empirical relationship between stress and drive current. In Section 4 we present a modified model for logical effort considering the impact of stress on multi-fingered layouts. We use our modified model of logical effort for predicting buffer delay and compare it with HSPICE simulation results in Sections 5 and 6 concludes our paper.
2. TCAD simulation setup We study the strain induced performance enhancement in multi-fingered devices in a 45 nm technology flow using well calibrated Synopsys Sentaurus TCAD tool [15]. We generate N/P MOSFET device structures with a physical gate length of 25 nm, spacer width of 30 nm and 60 nm tall poly gate on a (1 0 0) silicon wafer with h1 1 0i channel orientation using Sentaurus process simulation. A 60 nm thick t/c-ESL of 1.7 GPa (3.3 GPa) intrinsic stress is deposited on N/P MOSFET using multi-layer model for stressor deposition. A 50 nm thick eSiGe (with 25% Ge) source/ drain with 10 nm proximity to channel is used for PMOSFET. While STI and NiSi stress is modeled by assigning intrinsic stresses of 500 MPa compressive and 300 MPa tensile respectively; poly gate and spacer materials are modeled as stress free materials in our process simulation setup. Contacted gate pitch is taken to be 160 nm as suggested for 45 nm technology node. We assume a fixed separation of 210 nm between the finger located at the edge and t/c-ESL boundary. We calculate the longitudinal channel stress (rxx) and vertical channel stress (ryy) using 2D process simulation where all intentional stress sources such as t/c-ESL, poly SMT (for NMOSFET only), eSiGe (for PMOSFET only) and unintentional (STI) stress sources is taken into account. For large finger widths, plain strain condition in width direction can be assumed; therefore, a 2D process simulation for stress calculation is justified [16]. A simplified layout of an inverter using multi-fingered devices and a cross-sectional view of a typical four finger MOSFET structure which forms part of an inverter is shown in Fig. 1a and b respectively. Similar structures with number of fingers varying from one to seven and with different stress sources were also generated using process simulations. We use appropriate physical models [17] in Sentaurus device simulation to account for the ionized impurity scattering, carrier–carrier scattering, lateral field dependence and perpendicular field dependence effects on carrier mobility. We also include deformation potential and piezoresistance carrier mobility model that accounts for the bandgap narrowing and mobility enhancement due to mechanical stress. To include carrier quantization effects, we use density-gradient transport model.
3. Multi-fingered devices In integrated circuits, MOSFETs are generally realized in multifingered layouts. This is true in particular in standard cell based designs where the device finger widths are also mostly kept constant. Fingering is extensively used in full-custom design, too, to minimize area of layout. In strain engineered devices the number of fingers has an impact on the channel stress of fingers sharing an active region. We observe that the average value of channel stress per finger varies with number of fingers in multi-finger gate structures. Linear relationship between mobility enhancement and stress through piezoresistive coefficients is widely accepted for modeling and analysis purpose [18,19]; therefore, we use average stress per finger in multi-fingered devices for our analysis and modeling purpose. We plot the normalized average longitudinal channel stress per finger in multi-fingered devices in Fig. 2a. Please note that STI stress is inherent for each case shown in the figure and, therefore, we have not mentioned it exclusively. The stress in this figure is normalized to that in a corresponding single finger device. Stress variation amongst multi-fingered NMOSFET with t-ESL and SMT is small because t-ESL and STI induced stresses act in opposite direction and SMT induced longitudinal channel stress is uniform in all the fingers. Average stress per finger in multi-fingered PMOSFETs with eSiGe source/drain increases with number of fingers as the total volume of eSiGe surrounding the fingers increases. Average stress per finger in multi-fingered PMOSFETs with c-ESL decreases with number of fingers because every new finger added to the device has relatively smaller c-ESL and STI induced stress. The simulated stress shown in Fig. 2a can be described by the following equation [20]:
rxx;NF NF ¼ y0 þ A1 exp t1 rxx;ref
ð1Þ
where rxx,NF represents the average longitudinal stress in the fingers of a multi-fingered device with NF number of fingers. The symbol rxx,ref represents the longitudinal stress in the channel of the reference single-finger device and y0, A1, and t1 are fitting parameters specific to a given process technology. Stress and carrier mobility in the channel of a stressed device is related by the following equation [18]:
lstress l0 ¼ Pk rxx l0
ð2Þ
where l0 and lstress are the carrier mobility in unstressed and stressed devices respectively and Pk is piezoresistive coefficient. Please note that we consider only longitudinal stress in Eq. (2) for the reason as follows: The combined stress of t-ESL and poly SMT in vertical direction is much smaller than the stress in longitudinal direction. Our assumption (rxx ryy) in context of NMOSFET is also supported by the reported data in [16]. Ignoring vertical stress (ryy) is valid for PMOSFET also; however, for a different reason. The hole mobility is least sensitive (1% per 1 GPa) to the vertical stress [16]. Regarding transverse stress (width direction), we have already stated that for a wide finger width plain strain condition can be assumed in the width direction. The effective drive current in a CMOS inverter for delay estimation is given by [21]:
Ieff ¼
I H þ IL 2
ð3Þ
where IL = Ids (at Vgs = Vdd/2 and Vds = Vdd), and IH = Ids (at Vgs = Vdd and Vds = Vdd/2) Mechanical stress induced change in effective drive current is given by [11]:
381
N. Alam et al. / Microelectronics Reliability 53 (2013) 379–385
S/D
S/D
Gate
ESL
Gate
ESL
ESL
Gate
ESL
Gate
ESL
S/D
S/D
ESL S/D
STI
STI
σzz σxx σyy
Silicon Substrate
(a)
(b)
Fig. 1. (a) Simplified layout of an inverter using multi-fingered devices. (b) Cross-sectional view of a four finger device structure with stress components appropriately marked. Dotted lines in (a) represent the TCAD 2D simulation region.
eSiGe + c-ESL c-ESL eSiGe t-ESL + poly SMT
1.4 1.2
eSiGe + c-ESL c-ESL eSiGe t-ESL + poly SMT
1.14
(a)
1.0 0.8 0.6 0.4
Normalized Ieff
Normalized Stress
1.6
1.08
(b)
1.02 0.96 0.90 0.84
0.2 1
2
3
4
5
6
7
Number of Fingers
1
2
3
4
5
6
7
Number of Fingers
Fig. 2. (a) Average stress (rxx,NF) per finger in multi-fingered MOSFETs normalized to the stress (rxx,ref) in single finger reference MOSFET. Please note that STI stress is inherent to the layout for each case shown in figure. Symbols represent simulated data and lines represent Eq. (1). (b) Average effective drive current (Ieff,NF) per finger in multi-fingered MOSFETs normalized to the effective drive current (Ieff,ref) in the reference single finger MOSFET. Symbols represent the simulated data and lines represent Eq. (5).
Ieff;Stress Ieff l l0 DV th;Stress ¼ K 2 stress Ieff l0 ð3 dÞ V4dd V th
ð4aÞ
where Ieff,Stress is the effective drive current of a strain engineered device, Ieff is the effective drive current in reference device, K2 is a constant equal to 0.85 [11], d is drain-induced barrier lowering, Vth is the threshold voltage and DVth,Stress is stress induced change in the threshold voltage of reference device. Using widely accepted linear relationship between DVth,Stress and channel stress [22], we write above equation as:
Ieff;Stress Ieff ¼ Ieff
K2
ð3 dÞ V4dd V th
Ieff;Stress Ieff ¼ K 4 Pk rxx ; Ieff where K 4 ¼
K2
!
K3
K3 ð3 dÞ V4dd V th
Pk rxx
ð4bÞ
! ð4cÞ
Using (4c), we derive the value of the average effective drive current per finger in strain engineered multi-fingered devices with NF number of fingers, Ieff,NF. We express the value of Ieff,NF in terms of the current in reference strain engineered single-finger device, Ieff,ref. This derived value of Ieff,NF is:
Ieff;NF 1 þ K 4 Pk rxx;NF ¼ Ieff;ref 1 þ K 4 Pk rxx;ref
ð5Þ
The above equation models the average effective drive current in the fingers of multi-fingered devices in terms of the effective drive current in strain engineered single-finger device. Eq. (5) fits well on simulated values of effective drive current (Ieff,NF), as we show in Fig. 2b.
4. Logical effort modeling The method of logical effort is simple yet accurate way to estimate the delay in a CMOS circuit. Logical effort (g) of a gate is defined as the ratio of the input capacitance of the gate to the input capacitance of an inverter that can deliver the same output current [23]. According to the method of LE, the delay of any logic gate is decomposed in two components; (a) a fixed part of the delay of any logic gate is called the parasitic delay (p), and (b) another part that is proportional to the load connected at the output is called the effort delay (f). Further, the effort delay depends upon the logical effort (g) and fan-out (h) of the driver and is given as f = gh. The total delay (d) measured is a sum of parasitic delay (p) and effort delay (f). Therefore, the delay of any logic gate in units of s (a technology specific parameter) is given as d = gh + p. In the conventional logical effort approach [23] all inverters of a given technology with a constant aspect ratio (WP/WN) are assigned a logical effort of 1 regardless of the size of inverters. However, from our observation in the previous section, the effective drive current of strain engineered multi-fingered devices is a function of NF. Therefore, the logical effort of inverters designed using strain engineered multi-fingered devices shall also be a function of NF and cannot be assigned a fixed value of 1. Several modified models has been reported to increase the accuracy of the method of logical effort by considering the effects such as input-slope, temperature and voltage variations, and RC interconnects [24–26]. However, modified model of logical effort considering the layout dependent effect (LDE) variability due to the use of stressors has not been reported earlier. The layout dependent effect of variability due to the use of stressors causes significant variation in device performance [8,10]. Therefore, not considering its impact on the logical effort of a gate can result into inaccuracy in delay estimation and optimization.
382
N. Alam et al. / Microelectronics Reliability 53 (2013) 379–385
In this section we present a modified model for logical effort of CMOS inverters designed using multi-fingered devices. The value of logical effort of a logic gate is proportional to its Cin/Iout, where Cin is the input capacitance of the gate and Iout is the effective drive current (Ieff) charging/discharging the output capacitor. This is because the slope of delay versus Cout/Cin is assumed constant for all such inverters. However, we observe that this assumption is not valid in multi-fingered devices with mechanical stress. This is because of an unaccounted change in the drive current and Cin/Iout with the number of fingers in strain engineered multi-fingered devices. Please note that Cin normalized to number of fingers remains constant. Therefore, logical effort of inverters using multi-fingered devices (with respect to the reference inverter using single-finger device) in terms of effective drive current can be expressed as:
g NF ¼
Ieff;ref Ieff;NF
ð6aÞ
where gNF is the logical effort of inverters with multi-fingered device having NF number of fingers, Ieff,ref is the effective drive current of the reference single-finger device and Ieff,NF is the effective drive current per finger in multi-fingered devices. From (5) and (6a), we express logical effort in terms of stress as follows:
g NF ¼
1 þ K 4 Pk rxx;ref 1 þ K 4 Pk rxx;NF
ð6bÞ
where K4 is the parameter that relates change in effective drive current for a given relative change in carrier mobility. We express logical effort of an inverter designed with strain engineered multifingered devices using (1) and (6b) as:
g NF ¼
1 þ K 4 Pk rxx;ref 1 þ K 4 Pk rxx;ref y0 þ A1 exp NF t1
finger width constant. This constant finger width is equal to that in corresponding single finger Inverters. We plot the pull-up and pull-down logical effort of multi-fingered inverters as a function of number of fingers, computed using (6c) in Fig. 4. In the same figure we also show the logical effort extracted from mixed mode simulations. It is evident from the plot that the logical effort estimated using our model closely matches with that extracted from simulation. Thus, using our approach the logical efforts of inverters of all sizes can be estimated using stress parameters for a given technology. 5. Delay model of CMOS buffer In high speed CMOS circuits, tapered buffers are extensively used for clock and data signals distribution. Tapering factor is usually achieved through increase in the number of fingers in the inverters of successive stages. However, in strain engineered multi-fingered devices, increase in the number of fingers results into unaccounted change in the drive strength which subsequently causes unaccounted change in delays. Deviations of signal propagation delay from a target value (often called as delay uncertainty) can be critical for high speed circuits. Therefore, reducing delay uncertainty improves the robustness of a circuit and enhances the circuit performance. In order to develop design methodologies that reduce delay uncertainty, the effects that cause uncertainty in the signal propagation delay should be included in the model. In this section we present a buffer delay model while accounting for the logical effort variability arising from the use of strain engineered multi-fingered devices. An N stage buffer delay in the units of ‘s’ is given by [27]:
Buffer delay ¼ N ðg h þ pÞ
ð7aÞ
ð6cÞ
where NF is the number of fingers in multi-fingered devices and y0, A1, and t1 are fitting parameters obtained by fitting (1) into measured values of stresses (shown in Fig. 2a). To validate our modified model for LE, we measure logical efforts of CMOS inverters with different number of fingers in the devices while keeping the aspect ratio (WP/WN) of inverters constant. We define the logical effort of multi-fingered inverters as the ratio of the slope of its delay versus fan-out curve divided by the slope of the reference single finger inverter’s delay versus fan-out curve. We simulated inverters using mixed-mode simulations with number of fingers in both N and P devices varying from one to seven. For each of these inverters the load capacitance (Cout) values are kept proportional to the number of fingers. We adjust input signal slope to keep the input–output transition times equal (<5% error) in each case. Fig. 3a–d shows the pull-down and pull-up delays respectively of various inverters with respect to normalized load. We name our inverters on the basis of stressors used for performance enhancement as follows: Type-A inverter (PMOSFET with c-ESL and NMOSFET with t-ESL + SMT), Type-B inverter (PMOSFET with eSiGe and NMOSFET with t-ESL + SMT) and TypeC inverter (PMOSFET with c-ESL + eSiGe and NMOSFET with t-ESL + SMT). We repeat above mentioned simulations to extract the logical effort of all types of inverters defined above. For each type of Inverters (i.e. Type-A, Type-B, and Type-C) with single finger devices, equal transition time at the output is achieved through finger width adjustment. We keep finger width of NMOSFET constant and adjust PMOSFET finger widths for achieving equal pullup and pull-down transition time at the output of each type of Inverters with single finger devices. Thereafter, we implement the methodology of width increase (or drive strength increase) by increasing the number of fingers in the devices while keeping
where g, h, and p are logical effort, fan-out and parasitic delay respectively of each stage. In inverters with strain engineered multi-fingered devices, logical effort depends upon the number of fingers (NF). Therefore, the above expression for delay estimation needs to be modified. We write the buffer delay in terms of modified logical efforts as follows:
Buffer delay ¼ h
N X
g NF¼jhði1Þ þ N p
ð7bÞ
i¼1
where ‘gNF’ is the logical effort of inverters with ‘NF’ number of fingers, ‘N’ is the number of stages in the buffer, ‘h’ is fan-out of each stage, ‘p’ is parasitic delay and ‘j’ is the number of fingers in the first stage of any buffer. To validate our CMOS buffer delay model, we simulate different types of buffers using TCAD calibrated HSPICE simulation setup described in [9]. We name buffers as Buffer-A, Buffer-B and Buffer-C after the names of inverters as defined in Section 4. For each buffer we consider number of stages (N) varying from two to five. We also consider three differently sized buffers for each type such as Buffer-A_x1, Buffer-A_x2, and Buffer-A_x3. Here x1, x2, and x3 represent the number of fingers in the first stage inverter of a buffer. We show the measured delay of each type of buffers from HSPICE simulations in Fig. 5. In the same figure we also show the delay calculated using conventional logical effort (7a) and modified logical effort (7b). We also show the magnitude of error in calculated delays w.r.t. the measured delays in the same figure. We observe that for buffers using Type-A and Type-C Inverters (i.e. Buffer-A and Buffer-C) conventional logical effort model underestimates the delay. This is because in conventional logical effort model the logical effort of Inverters is considered independent of the number of fingers in the devices; whereas, from Fig. 4a, b and d it is clear that the logical effort increases with increase in number of fingers. On the
383
1 Finger 2 Finger 3 Finger 4 Finger 5 Finger 6 Finger 7 Finger
28 24 20 16
(a) NMOSFET with t-ESL and SMT
12 8 4
2
4
6
8
24 20 16 12
4
10
1 Finger 2 Finger 3 Finger 4 Finger 5 Finger 6 Finger 7 Finger
20 16
(c) PMOSFET with eSiGe
8 2
4
6
8
4
6
8
10
1 Finger 2 Finger 3 Finger 4 Finger 5 Finger 6 Finger 7 Finger
24
12
4
2
Load Capacitance (xCin)
Pull-Up Delay (ps)
Pull-Up Delay (ps)
24
(b) PMOSFET with c-ESL
8
Load Capacitance (xCin) 28
1 Finger 2 Finger 3 Finger 4 Finger 5 Finger 6 Finger 7 Finger
28
Pull-Up Delay (ps)
Pull-Down Delay (ps)
N. Alam et al. / Microelectronics Reliability 53 (2013) 379–385
20 16 12
4
10
(d) PMOSFET with eSiGe and c-ESL
8
Load Capacitance (xCin)
2
4
6
8
10
Load Capacitance (xCin)
Fig. 3. (a) Pull-down delay of inverters (NMOSFET with t-ESL + SMT). (b)–(d) Pull-up delay of inverters (PMOSFET with c-ESL, eSiGe and c-ESL + eSiGe) as a function of load capacitance normalized to input capacitance.
Simulation
1.04 1.03 1.02 1.01
1
2
3
4
5
6
1.15 1.10 1.05
(a) NMOSFET with t-ESL
1.00
Model
1.20
Pull-up LE
Pull-down LE
1.25
Simulation Model
1.05
(b) PMOSFET with c-ESL
1.00
7
1
Number of Fingers
3
4
5
6
7
Number of Fingers 1.08
Model Simulation
1.00
2
Model Simulation
0.96
(c) PMOSFET with eSiGe
0.92 0.88 0.84
Pull-up LE
Pull-up LE
1.06
1.04
(d) PMOSFET with eSiGe and c-ESL
1.02
1.00 1
2
3
4
5
6
7
Number of Fingers
1
2
3
4
5
6
7
Number of Fingers
Fig. 4. Logical effort of inverters as a function of number of fingers in the inverters. (a) Pull-down logical. (b)–(d) Pull-up logical effort. Symbols show the values of logical effort extracted through simulations and lines represent calculated values using (6c).
other hand, for buffer using Type-B Inverter (i.e. Buffer-B) conventional method overestimates the delay because it does not take into account the decrease in logical effort with increase in number of fingers; please see Fig. 4c. Since our modified model of logical effort accounts for the change in logical effort with increase in
number of fingers, therefore, the estimated delays are in close agreement with the simulated delays. It is apparent from the results that CMOS buffer delay estimation using modified logical effort (7b) is more accurate than the conventional method (7a). Since buffers are essentially required to drive loads widely used as a part
N. Alam et al. / Microelectronics Reliability 53 (2013) 379–385
2
3
4
5
Buffer Delay (ps)
2 0
6 40 4 30 20
2
2
3
4
0
5
50
8 6
40 4 30 20
2
2
3
4
Number of Stage (N)
Number of Stage (N)
Number of Stage (N)
(a) Buffer-A_x1
(b) Buffer-A_x2
(c) Buffer-A_x3
30
2
Simulation Conv. LE Modified LE Conv. LE Error Mod. LE Error
30
4 2
Buffer Delay (ps)
4
6
40
0
10 Simulation Conv. LE Modified LE Conv. LE Error Mod. LE Error
50
8 6
40 4 30
2
Percentage Error
6 40
8
50
5
60
Percentage Error
8
Percentage Error
50
10
60
10
Simulation Conv. LE Modified LE Conv. LE Error Mod. LE Error
60
Buffer Delay (ps)
Buffer Delay (ps)
4 30
8
10
Percentage Error
6 40
50
Simulation Conv. LE Modified LE Conv. LE Error Mod. LE Error
60
Percentage Error
8
10
Simulation Conv. LE Modified LE Conv. LE Error Mod. LE Error
60
Percentage Error
50
20
Buffer Delay (ps)
10
Simulation Conv. LE Modified LE Con. LE Error Mod. LE Error
60
Buffer Delay (ps)
384
20 2
3
5
2
3
4
20
5
2
3
4
Number of Stage (N)
Number of Stage (N)
(d) Buffer-B_x1
(e) Buffer-B_x2
(f) Buffer-B_x3
30
2
2
3
4
5
0
50
8 6
40 4 30 20
2
2
3
4
5
0
60
5
10
Simulation Conv. LE Modified LE Conv. LE Error Mod. LE Error
50
0
8 6
40 4 30 20
2
Percentage Error
4
10
Simulation Conv. LE Modified LE Conv. LE Error Mod. LE Error
Percentage Error
6 40
Percentage Error
8
60
Buffer Delay (ps)
10
Simulation Conv. LE Modified LE Conv. LE Error Mod. LE Error
50
20
0
0
Number of Stage (N)
60
Buffer Delay (ps)
4
Buffer Delay (ps)
20
0 2
3
4
Number of Stage (N)
Number of Stage (N)
Number of Stage (N)
(g) Buffer-C_x1
(h) Buffer-C_x2
(i) Buffer-C_x3
5
Fig. 5. Simulated and calculated (using conventional and modified logical efforts) buffer delays for three types of buffers of defferent drive strength. Magnitude of percentage error in calculated buffer delays w.r.t. simulated delay is also shown for comparison.
of clock/driver network, etc. [27] their better design is crucial in performance improvement.
violations of the timing constraints, thereby improving the robustness of a circuit and enhancing the circuit performance.
6. Conclusion
References
In this work we have analyzed and modeled the impact of layout dependent effects variability arising from the use of stressors. We first determined the relationship between average drive current per finger and number of fingers in strain-engineered multifingered MOSFETs. Using this relationship we derived a modified expression for the logical effort of inverters as a function of number of fingers in multi-fingered devices. We use our logical effort model to modify the buffer delay model which estimates buffer delay more accurately and reduces delay uncertainty. Uncertainty in the propagation delay of the clock/data path can cause violations of timing constraints. Therefore, reducing delay uncertainty by considering the effects that cause uncertainty can prevent the
[1] Shahidi GG. Design-technology interaction for post-32 nm node CMOS technologies. In: Symposium on VLSI technology; 2010. p. 143–4. [2] Song Y, Zhou H, Xu Q, Luo J, Yin H, Yan J, et al. Mobility enhancement technology for scaling of CMOS devices: overview and status. J Electron Mater 2011;40(7):1584–612. [3] Washington L, Nouri F, Thirupapuliyur S, Eneman G, Verheyen P, Moroz V, et al. PMOSFET With 200% mobility enhancement induced by multiple stressors. IEEE Electron Dev Lett 2006;27(6):511–3. [4] Ghani T, Armstrong M, Auth C, Bost M, Charvat P, Glass G, et al. A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors. IEDM Tech Dig 2003:978–80. [5] Hornung B, Khamankar R, Niimi H, Goodwin M, Robertson L, Miles D, Kirkpatrick B, AlShareef H, Varghese A, Bevan M, Nicollian P, Chidambaram PR, Chakravarthi S, Gurba A, Zhang X, Blatchford J, Smith B, Lu JP, Deloach J, Rathsack B, Bowen C, Thakar G, Machala C, Grider T. A high performance 90 nm logic technology with a 37 nm gate length, dual plasma nitrided gate dielectric
N. Alam et al. / Microelectronics Reliability 53 (2013) 379–385
[6] [7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
and differential offset spacer. In: Symposium on VLSI technology; 2003. p. 85– 6. Frank YB, Ming C. Advanced strain engineering for state-of-the-art nanoscale CMOS technology. Sci China: Inform Sci 2011;54(5):946–58. Flachowsky S, Wei A, Illgen R, Herrmann T, Hontschel J, Hostmann M, et al. Understanding strain-induced drive-current enhancement in strained-silicon NMOSFET and PMOSFET. IEEE Trans Electron Dev 2010;57(6):1343–54. Choi YS, Lian G, Vartuli C, Olubuyide O, Chung J, Riley D, et al. Layout variation effects in advanced MOSFETs: STI-induced embedded SiGe strain relaxation and dual-stress-liner boundary proximity effect. IEEE Trans Electron Dev 2010;57(11):2886–91. Alam N, Anand B, Dasgupta S. Process induced mechanical stress aware poly-pitch optimization for enhanced circuit performance. In: International symposium quality electronic design; 2012. p. 717–20. Grudowski P, Adams V, Bo Xiang-Zheng, Loiko K, Filipiak S, Hackenberg J et al. 1-D and 2-D geometry effects in uniaxially-strained dual etch stop layer stressor integrations. In: Symposium on VLSI technology; 2006. p. 62–3. Xu N, Wang LTN, Neureuther AR, Liu TJK. Physically based modeling of stressinduced variation in nano-scale transistor performance. IEEE Trans Dev Mater Reliab 2011;11(3):378–86. Xue J, Deng Y, Ye Z, Wang H, Yang L, Yu Z. A framework for layout-dependent STI stress analysis and stress-aware circuit optimization. IEEE Trans Very Large Scale Integr (VLSI) Syst 2012;20(3):498–511. Bianchi RA, Bouche G, Roux-dit-Buisson O. Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance. IEDM Tech Dig 2002:117–20. Youssef S, Dupuis D, Iskander R, Louerat MM. Automatic stress effects computation based on a layout generation tool for analog IC. In: IEEE international behavioral modeling and simulation conference; 2010. p. 7–12. TCAD Sentaurus, Synopsys, Version D-2010.03.
385
[16] Wu J, Wang X. Stress engineering for 32 nm CMOS technology node. In: International conference on solid-state and integrated-circuit technology; 2008. p. 113–6. [17] Synopsys Sentaurus Sdevice user guide; March 2010. [18] Li R, Yu L, Xin H, Dong Y, Tao K, Wang C. A comprehensive study of reducing the STI mechanical stress effect on channel-width-dependent Idsat. Semicond Sci Technol 2007;22:1292–7. [19] Yeh K-L, Guo J–C. The impact of layout-dependent STI stress and effective width on low-frequency noise and high-frequency performance in nanoscale NMOSFETs. IEEE Trans Electron Dev 2010;57(11):3092–100. [20] Steegen An, Maex K. Silicide induced stress in Si: origin and consequences for MOS technologies. Mater Sci Eng R 2002;38:1–53. [21] Na MH, Nowak EJ, Haensch W, Cai J. The effective drive current in CMOS inverters. IEDM Tech Dig 2002:121–4. [22] Wang CC, Zhao W, Liu F, Chen M, Cao Y. Modeling of layout-dependent stress effect in CMOS design. In: International conference on computer aided design; 2009. p. 513-20. [23] Sutherland I, Sproull B, Harris D. Logical effort: designing fast CMOS circuits. Morgan Kaufmann; 1999. [24] Lasbouygues B, Engels S, Wilson R, Maurine P, Azemard N, Auvergne D. Logical effort model extension to propagation delay representation. IEEE Trans Comput-Aided Des Integr Circ Syst 2006;25(9):1677–84. [25] Morgenshtein A, Friedman EG, Ginosar R, Kolodny A. Unified logical effort – a method for delay evaluation and minimization in logic paths with RC interconnect. IEEE Trans Very Large Scale Integr (VLSI) Syst 2010;18(5):689–96. [26] Chang MH, Hsieh CY, Chen MW, Hwang W. Logical effort models with voltage and temperature extensions in super-/near-/sub-threshold regions. In: Symposium on VLSI design, automation and test; 2011. p. 1–4. [27] Rabaey JM, Chandrakasan A, Nikolic B. Digital integrated circuits: a design perspective. 2nd ed. India: Prentice-Hall; 2003.
Contents lists available at SciVerse ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
The impact of process-induced mechanical stress on CMOS buffer design using multi-fingered devices Naushad Alam, Bulusu Anand, S. Dasgupta ⇑ Microelectronics and VLSI Group, ECE Department, Indian Institute of Technology Roorkee, Roorkee 247 667, India
a r t i c l e
i n f o
Article history: Received 7 June 2012 Received in revised form 9 August 2012 Accepted 18 September 2012 Available online 15 October 2012
a b s t r a c t In this paper we propose a modified model of logical effort for designing optimized buffers in multifingered layout scenario in the presence of process induced mechanical stress. It is observed that mechanical stresses induced by tensile and compressive Etch Stop Liner (t-ESL and c-ESL), embedded SiGe (eSiGe) and Shallow Trench Isolation (STI) are not uniform in all the fingers sharing an active region. As a result there is an unaccounted change in the drive current with the number of fingers; thereby causing an unaccounted change in the performance of logic gates implemented using multi-fingered layouts. We explore the impact of mechanical stress induced variability in inverters with multi-fingered devices and derive relationship between the logical effort (LE) and number of fingers (NFs). We use this relationship for predicting CMOS buffer delays more accurately and thus reducing the need for post-layout resizing of their transistors. Ó 2012 Elsevier Ltd. All rights reserved.
1. Introduction Deep submicron technology faces several process and performance related challenges which pose as a roadblock for miniaturization of the transistors [1]. The rate of supply voltage scaling has been reduced to maintain a required gate overdrive to meet performance requirement. This has resulted into increased lateral as well as transverse electric field in the channel. Also channel doping requirement in modern devices is very high to suppress short channel effects. Therefore, increased electric field and high doping in the channel results into degraded carrier mobility. Strain engineering has helped process engineers to makeup for this loss [2]. Mobility enhancement through strain engineering has emerged as an attractive solution for the device performance increase commensurately with dimensional scaling. Strain engineering delivers a performance gain that is equivalent to generations of technology scaling [3]. Therefore, it has become an integral part of a stateof-the-art CMOS process flow since its inception at 90 nm technology node [4,5]. Over a decade, various strain engineering techniques [6] have been proposed and are being used for introducing favourable stress [7] in the channel of a transistor. On a standard wafer with orientation (1 0 0)/h1 1 0i, for electron mobility (NMOSFET), tensile stress in the longitudinal and transverse direction and compressive stress in the vertical (to the wafer plane) direction is beneficial. On the other hand, compressive
⇑ Corresponding author. Tel./fax: +91 1332 285666. E-mail addresses: [email protected] (N. Alam), [email protected] (B. Anand), [email protected] (S. Dasgupta). 0026-2714/$ - see front matter Ó 2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.microrel.2012.09.011
stress in the longitudinal direction and tensile stress in the transverse and vertical direction improves the hole mobility (PMOSFET). Favorable stress itself in the channel is beneficial; however, the layout-dependent variability due to the use of stressors is a problem. Stress introduced in the channel through Stress Memorization (SMT), gate metal, and spacer material is least dependent on the layout. But, other major stressors that are essentially used in modern technologies add to the variability issues. Stress induced in the channel of a transistor through stressors like tensile/compressive Etch Stop Liner (t/c-ESL), embedded Silicon–Germanium/Carbon (eSiGe/eSiC) source/drain depends on various layout parameters such as source/drain length (LSD), poly-pitch (LPP), number of fingers (NFs) sharing an active region and ESL boundary [8–10]. Apart from the intentional sources of stress mentioned above, stress originating from Shallow Trench Isolation (STI) is inherent in the process technology and adds to the layout-dependent effects (LDEs) variability due to the use of stressors. LDE variability due to the use of stressors has led to various modeling and optimization issues at circuit and physical design stages [9,11–13]. While, most of the modeling and optimization work consider the average stress in a single finger in isolated or nested configuration, the impact of number of fingers (NFs) on the drive current of strain engineered multi-fingered devices remains unexplored. It has been reported that in nested configuration the stress in all the fingers are not equal and the drive current of a finger depends on the position of the finger in a nested layout [8]. The issue, that we intend to study and address in this paper, originates from this very fact that there is an unaccounted change in the drive current of fingers (of equal width) sharing an active region depending on the position of the finger and number of fingers
380
N. Alam et al. / Microelectronics Reliability 53 (2013) 379–385
(NFs) sharing an active region in a multi-fingered layout. Recently, the impact of NF on a multi-fingered device performance has been reported in [12,14] while considering only STI stress. However, none of the above work proposes a model that relates the effective drive current and number of fingers in multi-fingered devices. In this paper we investigate and model the number of fingers dependent stress-induced drive current and logical effort variability in multi-fingered layouts and its implication on CMOS buffer design. Buffers are widely employed to drive highly capacitive loads, and hence they frequently lie in the critical path. For this reason, it is important to understand how their delay is affected by LDE variability due to the use of stressors. We analyze the delay variability as a function of the number of stages N and the number of fingers NF in multi-fingered devices. We propose a modified model of CMOS buffer delay in terms of modified logical effort of inverters designed using multi-fingered devices. We organize our paper as follows: In Section 2 we describe our TCAD simulation setup. In Section 3 we study the variations in the channel stress and effective drive current of multi-fingered devices quantitatively and derive a physics based semi-empirical relationship between stress and drive current. In Section 4 we present a modified model for logical effort considering the impact of stress on multi-fingered layouts. We use our modified model of logical effort for predicting buffer delay and compare it with HSPICE simulation results in Sections 5 and 6 concludes our paper.
2. TCAD simulation setup We study the strain induced performance enhancement in multi-fingered devices in a 45 nm technology flow using well calibrated Synopsys Sentaurus TCAD tool [15]. We generate N/P MOSFET device structures with a physical gate length of 25 nm, spacer width of 30 nm and 60 nm tall poly gate on a (1 0 0) silicon wafer with h1 1 0i channel orientation using Sentaurus process simulation. A 60 nm thick t/c-ESL of 1.7 GPa (3.3 GPa) intrinsic stress is deposited on N/P MOSFET using multi-layer model for stressor deposition. A 50 nm thick eSiGe (with 25% Ge) source/ drain with 10 nm proximity to channel is used for PMOSFET. While STI and NiSi stress is modeled by assigning intrinsic stresses of 500 MPa compressive and 300 MPa tensile respectively; poly gate and spacer materials are modeled as stress free materials in our process simulation setup. Contacted gate pitch is taken to be 160 nm as suggested for 45 nm technology node. We assume a fixed separation of 210 nm between the finger located at the edge and t/c-ESL boundary. We calculate the longitudinal channel stress (rxx) and vertical channel stress (ryy) using 2D process simulation where all intentional stress sources such as t/c-ESL, poly SMT (for NMOSFET only), eSiGe (for PMOSFET only) and unintentional (STI) stress sources is taken into account. For large finger widths, plain strain condition in width direction can be assumed; therefore, a 2D process simulation for stress calculation is justified [16]. A simplified layout of an inverter using multi-fingered devices and a cross-sectional view of a typical four finger MOSFET structure which forms part of an inverter is shown in Fig. 1a and b respectively. Similar structures with number of fingers varying from one to seven and with different stress sources were also generated using process simulations. We use appropriate physical models [17] in Sentaurus device simulation to account for the ionized impurity scattering, carrier–carrier scattering, lateral field dependence and perpendicular field dependence effects on carrier mobility. We also include deformation potential and piezoresistance carrier mobility model that accounts for the bandgap narrowing and mobility enhancement due to mechanical stress. To include carrier quantization effects, we use density-gradient transport model.
3. Multi-fingered devices In integrated circuits, MOSFETs are generally realized in multifingered layouts. This is true in particular in standard cell based designs where the device finger widths are also mostly kept constant. Fingering is extensively used in full-custom design, too, to minimize area of layout. In strain engineered devices the number of fingers has an impact on the channel stress of fingers sharing an active region. We observe that the average value of channel stress per finger varies with number of fingers in multi-finger gate structures. Linear relationship between mobility enhancement and stress through piezoresistive coefficients is widely accepted for modeling and analysis purpose [18,19]; therefore, we use average stress per finger in multi-fingered devices for our analysis and modeling purpose. We plot the normalized average longitudinal channel stress per finger in multi-fingered devices in Fig. 2a. Please note that STI stress is inherent for each case shown in the figure and, therefore, we have not mentioned it exclusively. The stress in this figure is normalized to that in a corresponding single finger device. Stress variation amongst multi-fingered NMOSFET with t-ESL and SMT is small because t-ESL and STI induced stresses act in opposite direction and SMT induced longitudinal channel stress is uniform in all the fingers. Average stress per finger in multi-fingered PMOSFETs with eSiGe source/drain increases with number of fingers as the total volume of eSiGe surrounding the fingers increases. Average stress per finger in multi-fingered PMOSFETs with c-ESL decreases with number of fingers because every new finger added to the device has relatively smaller c-ESL and STI induced stress. The simulated stress shown in Fig. 2a can be described by the following equation [20]:
rxx;NF NF ¼ y0 þ A1 exp t1 rxx;ref
ð1Þ
where rxx,NF represents the average longitudinal stress in the fingers of a multi-fingered device with NF number of fingers. The symbol rxx,ref represents the longitudinal stress in the channel of the reference single-finger device and y0, A1, and t1 are fitting parameters specific to a given process technology. Stress and carrier mobility in the channel of a stressed device is related by the following equation [18]:
lstress l0 ¼ Pk rxx l0
ð2Þ
where l0 and lstress are the carrier mobility in unstressed and stressed devices respectively and Pk is piezoresistive coefficient. Please note that we consider only longitudinal stress in Eq. (2) for the reason as follows: The combined stress of t-ESL and poly SMT in vertical direction is much smaller than the stress in longitudinal direction. Our assumption (rxx ryy) in context of NMOSFET is also supported by the reported data in [16]. Ignoring vertical stress (ryy) is valid for PMOSFET also; however, for a different reason. The hole mobility is least sensitive (1% per 1 GPa) to the vertical stress [16]. Regarding transverse stress (width direction), we have already stated that for a wide finger width plain strain condition can be assumed in the width direction. The effective drive current in a CMOS inverter for delay estimation is given by [21]:
Ieff ¼
I H þ IL 2
ð3Þ
where IL = Ids (at Vgs = Vdd/2 and Vds = Vdd), and IH = Ids (at Vgs = Vdd and Vds = Vdd/2) Mechanical stress induced change in effective drive current is given by [11]:
381
N. Alam et al. / Microelectronics Reliability 53 (2013) 379–385
S/D
S/D
Gate
ESL
Gate
ESL
ESL
Gate
ESL
Gate
ESL
S/D
S/D
ESL S/D
STI
STI
σzz σxx σyy
Silicon Substrate
(a)
(b)
Fig. 1. (a) Simplified layout of an inverter using multi-fingered devices. (b) Cross-sectional view of a four finger device structure with stress components appropriately marked. Dotted lines in (a) represent the TCAD 2D simulation region.
eSiGe + c-ESL c-ESL eSiGe t-ESL + poly SMT
1.4 1.2
eSiGe + c-ESL c-ESL eSiGe t-ESL + poly SMT
1.14
(a)
1.0 0.8 0.6 0.4
Normalized Ieff
Normalized Stress
1.6
1.08
(b)
1.02 0.96 0.90 0.84
0.2 1
2
3
4
5
6
7
Number of Fingers
1
2
3
4
5
6
7
Number of Fingers
Fig. 2. (a) Average stress (rxx,NF) per finger in multi-fingered MOSFETs normalized to the stress (rxx,ref) in single finger reference MOSFET. Please note that STI stress is inherent to the layout for each case shown in figure. Symbols represent simulated data and lines represent Eq. (1). (b) Average effective drive current (Ieff,NF) per finger in multi-fingered MOSFETs normalized to the effective drive current (Ieff,ref) in the reference single finger MOSFET. Symbols represent the simulated data and lines represent Eq. (5).
Ieff;Stress Ieff l l0 DV th;Stress ¼ K 2 stress Ieff l0 ð3 dÞ V4dd V th
ð4aÞ
where Ieff,Stress is the effective drive current of a strain engineered device, Ieff is the effective drive current in reference device, K2 is a constant equal to 0.85 [11], d is drain-induced barrier lowering, Vth is the threshold voltage and DVth,Stress is stress induced change in the threshold voltage of reference device. Using widely accepted linear relationship between DVth,Stress and channel stress [22], we write above equation as:
Ieff;Stress Ieff ¼ Ieff
K2
ð3 dÞ V4dd V th
Ieff;Stress Ieff ¼ K 4 Pk rxx ; Ieff where K 4 ¼
K2
!
K3
K3 ð3 dÞ V4dd V th
Pk rxx
ð4bÞ
! ð4cÞ
Using (4c), we derive the value of the average effective drive current per finger in strain engineered multi-fingered devices with NF number of fingers, Ieff,NF. We express the value of Ieff,NF in terms of the current in reference strain engineered single-finger device, Ieff,ref. This derived value of Ieff,NF is:
Ieff;NF 1 þ K 4 Pk rxx;NF ¼ Ieff;ref 1 þ K 4 Pk rxx;ref
ð5Þ
The above equation models the average effective drive current in the fingers of multi-fingered devices in terms of the effective drive current in strain engineered single-finger device. Eq. (5) fits well on simulated values of effective drive current (Ieff,NF), as we show in Fig. 2b.
4. Logical effort modeling The method of logical effort is simple yet accurate way to estimate the delay in a CMOS circuit. Logical effort (g) of a gate is defined as the ratio of the input capacitance of the gate to the input capacitance of an inverter that can deliver the same output current [23]. According to the method of LE, the delay of any logic gate is decomposed in two components; (a) a fixed part of the delay of any logic gate is called the parasitic delay (p), and (b) another part that is proportional to the load connected at the output is called the effort delay (f). Further, the effort delay depends upon the logical effort (g) and fan-out (h) of the driver and is given as f = gh. The total delay (d) measured is a sum of parasitic delay (p) and effort delay (f). Therefore, the delay of any logic gate in units of s (a technology specific parameter) is given as d = gh + p. In the conventional logical effort approach [23] all inverters of a given technology with a constant aspect ratio (WP/WN) are assigned a logical effort of 1 regardless of the size of inverters. However, from our observation in the previous section, the effective drive current of strain engineered multi-fingered devices is a function of NF. Therefore, the logical effort of inverters designed using strain engineered multi-fingered devices shall also be a function of NF and cannot be assigned a fixed value of 1. Several modified models has been reported to increase the accuracy of the method of logical effort by considering the effects such as input-slope, temperature and voltage variations, and RC interconnects [24–26]. However, modified model of logical effort considering the layout dependent effect (LDE) variability due to the use of stressors has not been reported earlier. The layout dependent effect of variability due to the use of stressors causes significant variation in device performance [8,10]. Therefore, not considering its impact on the logical effort of a gate can result into inaccuracy in delay estimation and optimization.
382
N. Alam et al. / Microelectronics Reliability 53 (2013) 379–385
In this section we present a modified model for logical effort of CMOS inverters designed using multi-fingered devices. The value of logical effort of a logic gate is proportional to its Cin/Iout, where Cin is the input capacitance of the gate and Iout is the effective drive current (Ieff) charging/discharging the output capacitor. This is because the slope of delay versus Cout/Cin is assumed constant for all such inverters. However, we observe that this assumption is not valid in multi-fingered devices with mechanical stress. This is because of an unaccounted change in the drive current and Cin/Iout with the number of fingers in strain engineered multi-fingered devices. Please note that Cin normalized to number of fingers remains constant. Therefore, logical effort of inverters using multi-fingered devices (with respect to the reference inverter using single-finger device) in terms of effective drive current can be expressed as:
g NF ¼
Ieff;ref Ieff;NF
ð6aÞ
where gNF is the logical effort of inverters with multi-fingered device having NF number of fingers, Ieff,ref is the effective drive current of the reference single-finger device and Ieff,NF is the effective drive current per finger in multi-fingered devices. From (5) and (6a), we express logical effort in terms of stress as follows:
g NF ¼
1 þ K 4 Pk rxx;ref 1 þ K 4 Pk rxx;NF
ð6bÞ
where K4 is the parameter that relates change in effective drive current for a given relative change in carrier mobility. We express logical effort of an inverter designed with strain engineered multifingered devices using (1) and (6b) as:
g NF ¼
1 þ K 4 Pk rxx;ref 1 þ K 4 Pk rxx;ref y0 þ A1 exp NF t1
finger width constant. This constant finger width is equal to that in corresponding single finger Inverters. We plot the pull-up and pull-down logical effort of multi-fingered inverters as a function of number of fingers, computed using (6c) in Fig. 4. In the same figure we also show the logical effort extracted from mixed mode simulations. It is evident from the plot that the logical effort estimated using our model closely matches with that extracted from simulation. Thus, using our approach the logical efforts of inverters of all sizes can be estimated using stress parameters for a given technology. 5. Delay model of CMOS buffer In high speed CMOS circuits, tapered buffers are extensively used for clock and data signals distribution. Tapering factor is usually achieved through increase in the number of fingers in the inverters of successive stages. However, in strain engineered multi-fingered devices, increase in the number of fingers results into unaccounted change in the drive strength which subsequently causes unaccounted change in delays. Deviations of signal propagation delay from a target value (often called as delay uncertainty) can be critical for high speed circuits. Therefore, reducing delay uncertainty improves the robustness of a circuit and enhances the circuit performance. In order to develop design methodologies that reduce delay uncertainty, the effects that cause uncertainty in the signal propagation delay should be included in the model. In this section we present a buffer delay model while accounting for the logical effort variability arising from the use of strain engineered multi-fingered devices. An N stage buffer delay in the units of ‘s’ is given by [27]:
Buffer delay ¼ N ðg h þ pÞ
ð7aÞ
ð6cÞ
where NF is the number of fingers in multi-fingered devices and y0, A1, and t1 are fitting parameters obtained by fitting (1) into measured values of stresses (shown in Fig. 2a). To validate our modified model for LE, we measure logical efforts of CMOS inverters with different number of fingers in the devices while keeping the aspect ratio (WP/WN) of inverters constant. We define the logical effort of multi-fingered inverters as the ratio of the slope of its delay versus fan-out curve divided by the slope of the reference single finger inverter’s delay versus fan-out curve. We simulated inverters using mixed-mode simulations with number of fingers in both N and P devices varying from one to seven. For each of these inverters the load capacitance (Cout) values are kept proportional to the number of fingers. We adjust input signal slope to keep the input–output transition times equal (<5% error) in each case. Fig. 3a–d shows the pull-down and pull-up delays respectively of various inverters with respect to normalized load. We name our inverters on the basis of stressors used for performance enhancement as follows: Type-A inverter (PMOSFET with c-ESL and NMOSFET with t-ESL + SMT), Type-B inverter (PMOSFET with eSiGe and NMOSFET with t-ESL + SMT) and TypeC inverter (PMOSFET with c-ESL + eSiGe and NMOSFET with t-ESL + SMT). We repeat above mentioned simulations to extract the logical effort of all types of inverters defined above. For each type of Inverters (i.e. Type-A, Type-B, and Type-C) with single finger devices, equal transition time at the output is achieved through finger width adjustment. We keep finger width of NMOSFET constant and adjust PMOSFET finger widths for achieving equal pullup and pull-down transition time at the output of each type of Inverters with single finger devices. Thereafter, we implement the methodology of width increase (or drive strength increase) by increasing the number of fingers in the devices while keeping
where g, h, and p are logical effort, fan-out and parasitic delay respectively of each stage. In inverters with strain engineered multi-fingered devices, logical effort depends upon the number of fingers (NF). Therefore, the above expression for delay estimation needs to be modified. We write the buffer delay in terms of modified logical efforts as follows:
Buffer delay ¼ h
N X
g NF¼jhði1Þ þ N p
ð7bÞ
i¼1
where ‘gNF’ is the logical effort of inverters with ‘NF’ number of fingers, ‘N’ is the number of stages in the buffer, ‘h’ is fan-out of each stage, ‘p’ is parasitic delay and ‘j’ is the number of fingers in the first stage of any buffer. To validate our CMOS buffer delay model, we simulate different types of buffers using TCAD calibrated HSPICE simulation setup described in [9]. We name buffers as Buffer-A, Buffer-B and Buffer-C after the names of inverters as defined in Section 4. For each buffer we consider number of stages (N) varying from two to five. We also consider three differently sized buffers for each type such as Buffer-A_x1, Buffer-A_x2, and Buffer-A_x3. Here x1, x2, and x3 represent the number of fingers in the first stage inverter of a buffer. We show the measured delay of each type of buffers from HSPICE simulations in Fig. 5. In the same figure we also show the delay calculated using conventional logical effort (7a) and modified logical effort (7b). We also show the magnitude of error in calculated delays w.r.t. the measured delays in the same figure. We observe that for buffers using Type-A and Type-C Inverters (i.e. Buffer-A and Buffer-C) conventional logical effort model underestimates the delay. This is because in conventional logical effort model the logical effort of Inverters is considered independent of the number of fingers in the devices; whereas, from Fig. 4a, b and d it is clear that the logical effort increases with increase in number of fingers. On the
383
1 Finger 2 Finger 3 Finger 4 Finger 5 Finger 6 Finger 7 Finger
28 24 20 16
(a) NMOSFET with t-ESL and SMT
12 8 4
2
4
6
8
24 20 16 12
4
10
1 Finger 2 Finger 3 Finger 4 Finger 5 Finger 6 Finger 7 Finger
20 16
(c) PMOSFET with eSiGe
8 2
4
6
8
4
6
8
10
1 Finger 2 Finger 3 Finger 4 Finger 5 Finger 6 Finger 7 Finger
24
12
4
2
Load Capacitance (xCin)
Pull-Up Delay (ps)
Pull-Up Delay (ps)
24
(b) PMOSFET with c-ESL
8
Load Capacitance (xCin) 28
1 Finger 2 Finger 3 Finger 4 Finger 5 Finger 6 Finger 7 Finger
28
Pull-Up Delay (ps)
Pull-Down Delay (ps)
N. Alam et al. / Microelectronics Reliability 53 (2013) 379–385
20 16 12
4
10
(d) PMOSFET with eSiGe and c-ESL
8
Load Capacitance (xCin)
2
4
6
8
10
Load Capacitance (xCin)
Fig. 3. (a) Pull-down delay of inverters (NMOSFET with t-ESL + SMT). (b)–(d) Pull-up delay of inverters (PMOSFET with c-ESL, eSiGe and c-ESL + eSiGe) as a function of load capacitance normalized to input capacitance.
Simulation
1.04 1.03 1.02 1.01
1
2
3
4
5
6
1.15 1.10 1.05
(a) NMOSFET with t-ESL
1.00
Model
1.20
Pull-up LE
Pull-down LE
1.25
Simulation Model
1.05
(b) PMOSFET with c-ESL
1.00
7
1
Number of Fingers
3
4
5
6
7
Number of Fingers 1.08
Model Simulation
1.00
2
Model Simulation
0.96
(c) PMOSFET with eSiGe
0.92 0.88 0.84
Pull-up LE
Pull-up LE
1.06
1.04
(d) PMOSFET with eSiGe and c-ESL
1.02
1.00 1
2
3
4
5
6
7
Number of Fingers
1
2
3
4
5
6
7
Number of Fingers
Fig. 4. Logical effort of inverters as a function of number of fingers in the inverters. (a) Pull-down logical. (b)–(d) Pull-up logical effort. Symbols show the values of logical effort extracted through simulations and lines represent calculated values using (6c).
other hand, for buffer using Type-B Inverter (i.e. Buffer-B) conventional method overestimates the delay because it does not take into account the decrease in logical effort with increase in number of fingers; please see Fig. 4c. Since our modified model of logical effort accounts for the change in logical effort with increase in
number of fingers, therefore, the estimated delays are in close agreement with the simulated delays. It is apparent from the results that CMOS buffer delay estimation using modified logical effort (7b) is more accurate than the conventional method (7a). Since buffers are essentially required to drive loads widely used as a part
N. Alam et al. / Microelectronics Reliability 53 (2013) 379–385
2
3
4
5
Buffer Delay (ps)
2 0
6 40 4 30 20
2
2
3
4
0
5
50
8 6
40 4 30 20
2
2
3
4
Number of Stage (N)
Number of Stage (N)
Number of Stage (N)
(a) Buffer-A_x1
(b) Buffer-A_x2
(c) Buffer-A_x3
30
2
Simulation Conv. LE Modified LE Conv. LE Error Mod. LE Error
30
4 2
Buffer Delay (ps)
4
6
40
0
10 Simulation Conv. LE Modified LE Conv. LE Error Mod. LE Error
50
8 6
40 4 30
2
Percentage Error
6 40
8
50
5
60
Percentage Error
8
Percentage Error
50
10
60
10
Simulation Conv. LE Modified LE Conv. LE Error Mod. LE Error
60
Buffer Delay (ps)
Buffer Delay (ps)
4 30
8
10
Percentage Error
6 40
50
Simulation Conv. LE Modified LE Conv. LE Error Mod. LE Error
60
Percentage Error
8
10
Simulation Conv. LE Modified LE Conv. LE Error Mod. LE Error
60
Percentage Error
50
20
Buffer Delay (ps)
10
Simulation Conv. LE Modified LE Con. LE Error Mod. LE Error
60
Buffer Delay (ps)
384
20 2
3
5
2
3
4
20
5
2
3
4
Number of Stage (N)
Number of Stage (N)
(d) Buffer-B_x1
(e) Buffer-B_x2
(f) Buffer-B_x3
30
2
2
3
4
5
0
50
8 6
40 4 30 20
2
2
3
4
5
0
60
5
10
Simulation Conv. LE Modified LE Conv. LE Error Mod. LE Error
50
0
8 6
40 4 30 20
2
Percentage Error
4
10
Simulation Conv. LE Modified LE Conv. LE Error Mod. LE Error
Percentage Error
6 40
Percentage Error
8
60
Buffer Delay (ps)
10
Simulation Conv. LE Modified LE Conv. LE Error Mod. LE Error
50
20
0
0
Number of Stage (N)
60
Buffer Delay (ps)
4
Buffer Delay (ps)
20
0 2
3
4
Number of Stage (N)
Number of Stage (N)
Number of Stage (N)
(g) Buffer-C_x1
(h) Buffer-C_x2
(i) Buffer-C_x3
5
Fig. 5. Simulated and calculated (using conventional and modified logical efforts) buffer delays for three types of buffers of defferent drive strength. Magnitude of percentage error in calculated buffer delays w.r.t. simulated delay is also shown for comparison.
of clock/driver network, etc. [27] their better design is crucial in performance improvement.
violations of the timing constraints, thereby improving the robustness of a circuit and enhancing the circuit performance.
6. Conclusion
References
In this work we have analyzed and modeled the impact of layout dependent effects variability arising from the use of stressors. We first determined the relationship between average drive current per finger and number of fingers in strain-engineered multifingered MOSFETs. Using this relationship we derived a modified expression for the logical effort of inverters as a function of number of fingers in multi-fingered devices. We use our logical effort model to modify the buffer delay model which estimates buffer delay more accurately and reduces delay uncertainty. Uncertainty in the propagation delay of the clock/data path can cause violations of timing constraints. Therefore, reducing delay uncertainty by considering the effects that cause uncertainty can prevent the
[1] Shahidi GG. Design-technology interaction for post-32 nm node CMOS technologies. In: Symposium on VLSI technology; 2010. p. 143–4. [2] Song Y, Zhou H, Xu Q, Luo J, Yin H, Yan J, et al. Mobility enhancement technology for scaling of CMOS devices: overview and status. J Electron Mater 2011;40(7):1584–612. [3] Washington L, Nouri F, Thirupapuliyur S, Eneman G, Verheyen P, Moroz V, et al. PMOSFET With 200% mobility enhancement induced by multiple stressors. IEEE Electron Dev Lett 2006;27(6):511–3. [4] Ghani T, Armstrong M, Auth C, Bost M, Charvat P, Glass G, et al. A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors. IEDM Tech Dig 2003:978–80. [5] Hornung B, Khamankar R, Niimi H, Goodwin M, Robertson L, Miles D, Kirkpatrick B, AlShareef H, Varghese A, Bevan M, Nicollian P, Chidambaram PR, Chakravarthi S, Gurba A, Zhang X, Blatchford J, Smith B, Lu JP, Deloach J, Rathsack B, Bowen C, Thakar G, Machala C, Grider T. A high performance 90 nm logic technology with a 37 nm gate length, dual plasma nitrided gate dielectric
N. Alam et al. / Microelectronics Reliability 53 (2013) 379–385
[6] [7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
and differential offset spacer. In: Symposium on VLSI technology; 2003. p. 85– 6. Frank YB, Ming C. Advanced strain engineering for state-of-the-art nanoscale CMOS technology. Sci China: Inform Sci 2011;54(5):946–58. Flachowsky S, Wei A, Illgen R, Herrmann T, Hontschel J, Hostmann M, et al. Understanding strain-induced drive-current enhancement in strained-silicon NMOSFET and PMOSFET. IEEE Trans Electron Dev 2010;57(6):1343–54. Choi YS, Lian G, Vartuli C, Olubuyide O, Chung J, Riley D, et al. Layout variation effects in advanced MOSFETs: STI-induced embedded SiGe strain relaxation and dual-stress-liner boundary proximity effect. IEEE Trans Electron Dev 2010;57(11):2886–91. Alam N, Anand B, Dasgupta S. Process induced mechanical stress aware poly-pitch optimization for enhanced circuit performance. In: International symposium quality electronic design; 2012. p. 717–20. Grudowski P, Adams V, Bo Xiang-Zheng, Loiko K, Filipiak S, Hackenberg J et al. 1-D and 2-D geometry effects in uniaxially-strained dual etch stop layer stressor integrations. In: Symposium on VLSI technology; 2006. p. 62–3. Xu N, Wang LTN, Neureuther AR, Liu TJK. Physically based modeling of stressinduced variation in nano-scale transistor performance. IEEE Trans Dev Mater Reliab 2011;11(3):378–86. Xue J, Deng Y, Ye Z, Wang H, Yang L, Yu Z. A framework for layout-dependent STI stress analysis and stress-aware circuit optimization. IEEE Trans Very Large Scale Integr (VLSI) Syst 2012;20(3):498–511. Bianchi RA, Bouche G, Roux-dit-Buisson O. Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance. IEDM Tech Dig 2002:117–20. Youssef S, Dupuis D, Iskander R, Louerat MM. Automatic stress effects computation based on a layout generation tool for analog IC. In: IEEE international behavioral modeling and simulation conference; 2010. p. 7–12. TCAD Sentaurus, Synopsys, Version D-2010.03.
385
[16] Wu J, Wang X. Stress engineering for 32 nm CMOS technology node. In: International conference on solid-state and integrated-circuit technology; 2008. p. 113–6. [17] Synopsys Sentaurus Sdevice user guide; March 2010. [18] Li R, Yu L, Xin H, Dong Y, Tao K, Wang C. A comprehensive study of reducing the STI mechanical stress effect on channel-width-dependent Idsat. Semicond Sci Technol 2007;22:1292–7. [19] Yeh K-L, Guo J–C. The impact of layout-dependent STI stress and effective width on low-frequency noise and high-frequency performance in nanoscale NMOSFETs. IEEE Trans Electron Dev 2010;57(11):3092–100. [20] Steegen An, Maex K. Silicide induced stress in Si: origin and consequences for MOS technologies. Mater Sci Eng R 2002;38:1–53. [21] Na MH, Nowak EJ, Haensch W, Cai J. The effective drive current in CMOS inverters. IEDM Tech Dig 2002:121–4. [22] Wang CC, Zhao W, Liu F, Chen M, Cao Y. Modeling of layout-dependent stress effect in CMOS design. In: International conference on computer aided design; 2009. p. 513-20. [23] Sutherland I, Sproull B, Harris D. Logical effort: designing fast CMOS circuits. Morgan Kaufmann; 1999. [24] Lasbouygues B, Engels S, Wilson R, Maurine P, Azemard N, Auvergne D. Logical effort model extension to propagation delay representation. IEEE Trans Comput-Aided Des Integr Circ Syst 2006;25(9):1677–84. [25] Morgenshtein A, Friedman EG, Ginosar R, Kolodny A. Unified logical effort – a method for delay evaluation and minimization in logic paths with RC interconnect. IEEE Trans Very Large Scale Integr (VLSI) Syst 2010;18(5):689–96. [26] Chang MH, Hsieh CY, Chen MW, Hwang W. Logical effort models with voltage and temperature extensions in super-/near-/sub-threshold regions. In: Symposium on VLSI design, automation and test; 2011. p. 1–4. [27] Rabaey JM, Chandrakasan A, Nikolic B. Digital integrated circuits: a design perspective. 2nd ed. India: Prentice-Hall; 2003.