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Determination of DC equivalent hot carrier stress times in scaled CMOS devices using novel AC stress methodology
Microelectronics Reliability 93 (2019) 98–101
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Determination of DC equivalent hot carrier stress times in scaled CMOS devices using novel AC stress methodology
T
⁎
Andreas Kerber , Tanya Nigam Reliability Engineering, GLOBALFOUNDRIES Inc., 400 Stone Break Road Extension, Malta, NY 12020, USA
A R T I C LE I N FO
A B S T R A C T
Keywords: Bias temperature instability Metal gate High-k dielectrics CMOS devices
A new AC hot carrier injection (HCI) test methodology replicating the switching in digital CMOS circuits is introduced to correlate HCI in discrete scaled CMOS devices to HCI in logic circuits. This technique allows us to demonstrate that the historic 50× reduction for definition of DC HCI lifetime targets for mid-Vg stress in scaled devices should be uplifted to 1000× based on the correlation with RO degradation for poly-Si/SiON and 14 nm FinFET data. This brings significant HCI relief for device optimization in scaled technology nodes.
1. Introduction The bias temperature instability (BTI) and the hot carrier injection with contributions from conducting (HCI or c-HCI) and non-conducting (nc-HCI) stress mode are considered the most critical device degradation mechanisms in scaled CMOS technologies. While at elevated test temperature BTI is the dominant contributor to the frequency degradation in logic CMOS circuits for scaled nodes, HCI impact also needs careful review to ensure long term product reliability as the time exponent for HCI (~0.4) [1,2] is about 2× that of BTI (~0.2) [3]. In logic CMOS circuits HCI occurs during the switching events. Traditionally, DC stress has been translated to an equivalent AC stress time based on work done in earlier technology nodes. Some recent publications [4,5], have questioned this DC to AC translation in sub-100 nm gate length. A clear correlation of DC HCI to AC HCI using on-chip or [6] off-chip [7] signal generation is needed and ultimately demonstration of ring oscillator circuit degradation is required. In scaled technologies extracting purely the HCI component gets challenging due to BTI contribution and self-heating in bulk FinFET and SOI based technologies [8,9]. In this work we introduce a novel AC HCI characterization methodology that allows one to mimic device slew rates under different load condition by using synchronized waveforms and independently controlling the gate and drain input. This is an enhancement over the historical technique of applying trapezoidal signals using pulse generator units and only controlling the overlap time between gate and drain pulses [10–12]. In addition using this technique the self-heating induced enhanced degradation is reduced as current flow occurs only during switching. Contribution due to BTI in ON state cannot be
⁎
Corresponding author. E-mail address: [email protected] (A. Kerber).
https://doi.org/10.1016/j.microrel.2018.12.012 Received 1 September 2018; Accepted 27 December 2018 0026-2714/ © 2018 Published by Elsevier Ltd.
eliminated but are significantly reduced due to 1) BTI recovery during AC operation (~2× for NBTI) and 2) the ability to modulate the stress frequency and slew rate to enhance HCI. 2. Experimental setup Discrete thin oxide transistors based on 14 nm replacement metal gate (RMG) bulk-FinFET technology and a scaled poly-Si/SiON CMOS technology were subjected to conventional DC HCI (Fig. 1a), AC BTI stress and the newly introduced AC HCI stress methodology at T = 125 °C or T = 30 °C. The conventional DC HCI stress methodology applied to ultra-scaled CMOS devices uses either Vg = Vd = Vstress or Vg = mid-Vd stress. When the gate is biased using Vg = Vstress the BTI component and potential self-heating contributions in FinFET and SOI devices are enhanced which needs close attention. The Vg = mid-Vd stress condition is favored since BTI and self-heating contributions are reduced and it yields a better representation of an equivalent HCI stress condition for digital CMOS circuits like RO [13]. A typical applied voltage waveform on drain and gate terminal during AC stress is shown in Fig. 1b. In the AC HCI stress mode, a digital waveform is applied to the gate and an inverted waveform to the drain of a discrete MOSFET with specified frequency, duty cycle, rise & fall time. To modulate the HCI contribution, the gate and drain voltage signals are offset by a time Δ using synchronized remote sense amplifier units, as outlined in Fig. 1c, which determines the point (Vx) where the gate and drain voltage cross over. The transition time is defined as the duration for switching the drain voltage between the stress bias and ground which for symmetric gate and drain voltage waveforms is equal to the rise and fall times of the digital signal. A frequency range of 5 Hz
Microelectronics Reliability 93 (2019) 98–101
A. Kerber, T. Nigam
Fig. 1. Schematic illustration of conventional DC hot carrier stress (a) and the device degradation during operation of logic CMOS circuits (b). To mimic the device degradation during switching of logic CMOS circuits an AC hot carrier stress is introduced which can be modulated by shifting the gate and drain waveforms (c).
to 50 kHz was explored employing a 50% duty cycle. No frequency dependence in AC HCI degradation is observed when a constant ratio of on-time over transition-time is used. For the nc-HCI stress mode, degradation was found to be negligible for the short channel devices, referred to as core devices, at given stress condition and will not be discussed further in this paper, while in the BTI mode degradation is measurable and yields a lower bound for demonstrating HCI degradation. The measured HCI degradation under AC stress as outlined above is an integral of the various Vg and Vd bias combinations during the rise and fall transition of digital CMOS circuit operation. The Vx point represents the highest AC stress voltage at gate and drain simultaneously and thus is the critical parameter for determining the AC HCI contribution due to the high voltage acceleration of the HCI mechanism. For a cross point Vx = VDD, the complete Vg is swept at high VDD leading to worst case AC HCI for core transistors in ultra-scaled CMOS technologies [14]. It should be noted that Vx = VDD never occurs in typical logic CMOS circuits with a limited load and thus it is not a representative condition for HCI [13]. Fig. 2. Comparison of 14 nm core device AC HCI degradation to Vg = Vd and Vg = mid-Vd stress condition. AC HCI (f = 50 kHz) shows similar time evolution as DC HCI condition. The AC HCI degradation is reducing with decreasing Vx and becomes masked by xBTI.
3. Results and discussion Conventional DC HCI data taken at Vg = Vd and Vg = mid-Vd stress condition are show in Fig. 2 for 14 nm core FinFET devices using the standard ΔIdsat degradation metric for nFET and pFET devices measured at T = 125 °C. The DC HCI data is plotted versus the stress time. For Vg = Vd both device types follow a power law time evolution with time exponent, n, of ~0.45 up to degradation levels of ~20% with saturation at higher degradation [4] for the used stress voltage. For Vg = mid-Vd stress condition, nFET devices continue to show well behaved power law dependence with similar kinetic as for Vg = Vd. For pFET devices stressed at Vg = mid-Vd, however, the degradation kinetic is impacted by charge trapping causing competing effects of electron trapping and interface degradation. As result the degradation kinetic at short stress times shows significant deviation from the expected long term time evolution.
In addition, AC BTI degradation was measured with drain terminal grounded and gate terminal being altered between stress and ground (red symbols in Fig. 2) exhibiting a time slope of n ~ 0.2 for both device types. The AC BTI data is plotted versus the power-on-time which is half the stress time as a 50% duty cycle was used. It should be noted as AC BTI degradation is ranging from 0.1% to 5% it will mask HCI contributions at low degradation levels and likely dominate the kinetic behavior for such stress conditions. For AC HCI stress the measured ΔIdsat degradation is plotted versus the cumulative transition time for 3 different Vx value ranging from 0.6·VDD to 0.8·VDD (blue symbols in Fig. 2). The cumulative transition time allows one to eliminate the impact of stress frequency on the AC 99
Microelectronics Reliability 93 (2019) 98–101
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HCI data. To enhance the HCI contribution the transition time was chosen ~30% of the stress period to reduce the BTI component. For AC HCI the degradation monotonically decreases with decreasing Vx value. The AC HCI degradation kinetic is consistent with the DC stress conditions for nFET (Vg = Vd and Vg = mid-Vd) with the power law time exponent (~0.45) in agreement with the HCI literature [1,2]. For pFET AC HCI degradation follows the power law time exponent (~0.45) and shows no electron trapping consistent with Vg = Vd stress and typical nFET HCI degradation. This demonstrates that the proposed AC HCI stress methodology captures HCI time evolution for nFET and pFET devices. For both n-channel and p-channel FinFET devices the BTI degradation mode masks the HCI degradation for Vx ≤ 0.6·VDD as evident from the data in Fig. 2. This limits the ability of the method to determine the HCI component for small Vx values. In order to expand the Vx range to lower values a reduced stress temperature is recommended since BTI activation energy exceeds the HCI activation energy. The AC HCI data at Vx ~ 0.8·VDD overlaps the DC HCI data measured at Vg = mid-Vd for nFET devices. This indicates that Vg = midVd is an appropriate choice to capture HCI degradation in logic circuits with a standard load. Note that for pFET device such correlation cannot be established due to the electron trapping component stated previously, while kinetic and degradation is consistent with Vg = Vd stress. To confirm that Vx ~ 0.8·VDD is an appropriate choice for HCI assessment in logic circuits we simulated the voltage waveforms for an inverter RO with an asymmetric strength of nFET and pFET devices having a ratio of 0.5 and 2 (see Fig. 3). As can be seen when the pFET device is strong (upper panel of Fig. 3) the pFET crossover point Vx is 0.75·VDD compared to the case of a weak pFET (0.85·VDD) and vice versa for nFET devices. This indicates that mid-Vg DC HCI with lifetime similar to Vx = 0.8·VDD is a good reference for AC HCI contribution in an RO. Thus, one can predict the HCI contribution in RO frequency degradation by accounting for the transition time and stress frequency to extract the total mid-Vg stress time. To correlate the AC HCI in discrete device to logic CMOS circuit degradation 14 nm core FinFET device ROs were stressed at typical accelerated stress conditions beyond 2× the nominal use voltage (V1 < V2 < V3) utilizing the time resolved RO stress-and-sense methodology introduced in [15]. The RO degradation in Fig. 4 is plotted versus the stress time unlike the AC BTI and AC HCI data in
Fig. 4. Frequency degradation for inverter, NAND and NOR based RO at T = 125 °C (left) and T = 30 °C (right) using acceleration conditions > 2× nominal use voltage (V1′ < V2′ < V3′). Negligible impact of inverter load (fan-out of 1 to 4) and circuit type on frequency degradation is observed and no increase in time-slope at T = 125 °C while at T = 30 °C an increase in time slope for medium and high stress voltage is seen indicating contributions from hot carrier degradation.
Fig. 5. Comparison of RO frequency degradation with projected core nFET and pFET AC HCI (f = 5 kHz) impact for a cross-point Vx = 0.8. The gap between stress and transition time is ~105× considering combined contribution for nFET and pFET devices.
Fig. 2. At T = 125 °C the frequency degradation follows a single power law time evolution with a slope of ~0.25 obtained by linear regression stressed up to 105 s consistent with BTI being the dominant degradation mechanism (left panel of Fig. 4) for various circuit types, loads and different # of stages. The frequency degradation is independent of circuit types, loads and different # of stages suggesting negligible HCI contribution even so the time slope is slightly higher compare to AC BTI in Fig. 2. The lack of HCI is further explored by reducing the stress temperature to T = 30 °C. When the oscillators are stressed at T = 30 °C a ~10× reduction in frequency degradation is observed consistent with thermal activation of BTI for VDD = V1′. As the stress voltage is increased a change in time evolution can be observed allowing one to assess the HCI degradation in a digital CMOS circuit (right panel of
Fig. 3. Simulated voltage waveforms in a standard inverter based ring oscillator with nFet to pFET ratio of 0.5 and 2. The Vx cross-point ranges from 0.7 to 0.85. 100
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and yields a similar level of degradation as the Vg = mid-Vd HCI stress. Based on our RO and DC/AC HCI data we demonstrated that the 50× reduction for scaled devices is very conservative for a Vg = mid-Vd condition and the new DC HCI target can be reduced by 1000× for recent poly-Si/SiON technologies and potentially more for 14 nm FinFETs and beyond. Acknowledgment The author would like to acknowledge the stimulating discussions with the Reliability Engineering team at GLOBALFOUNDRIES. References [1] P. Heremans, R. Bellens, G. Groeseneken, H.-E. Maes, Consistent model for the hotcarrier degradation in n-channel and p-channel MOSFET's, IEEE Trans. Electron Devices 35 (12) (1988) 2194–2209, https://doi.org/10.1109/16.8794. [2] P. Fang, J. Tao, J.-F. Chen, C. Hu, Design in hot-carrier reliability for higher performance logic applications, IEEE Custom Integrated Circuits Conference, 1998, pp. 525–531, , https://doi.org/10.1109/CICC.1998.695033. [3] S. Mahapatra, V. Huard, A. Kerber, V. Reddy, S. Kalpat, A. Haggag, Universality of NBTI – From Devices to Circuits and Products, IRPS, 2014, pp. 3B.1.1–3B.1.8, https://doi.org/10.1109/IRPS.2014.6860615. [4] T. Nigam, B. Parameshwaran, G. Krause, Accurate Product Lifetime Predictions Based on Device-level Measurements, IRPS, 2009, pp. 634–639, https://doi.org/10. 1109/IRPS.2009.5173322. [5] A. Kerber, S. Cimino, F. Guarin, T. Nigam, Assessing Device Reliability Margin in Scaled CMOS Technologies Using Ring Oscillator Circuits, IEEE EDTM, 2017, https://doi.org/10.1109/EDTM.2017.7947495. [6] Leonhard Heiß, Andreas Lachmann, Reiner Schwab, Georgios Panagopoulos, Peter Baumgartner, Mamatha Yakkegondi Virupakshappaa, Doris SchmittLandsiedel, New Methodology for On-chip RF Reliability Assessment, IRPS, 2016, pp. 4C-5.1–4C-5.7, https://doi.org/10.1109/IRPS.2016.7574541. [7] Christian Schlünder, F. Proebster, J. Berthold, Katja Puschkarsky, Georg Georgakos, Wolfgang Gustin, Hans Reisinger, Circuit Relevant HCS Lifetime Assessments at Single Transistors With Emulated Variable Loads, IRPS, 2017, pp. 2D-2.1–2D-2.7, https://doi.org/10.1109/IRPS.2017.7936262. [8] C. Prasad, L. Jiang, D. Singh, M. Agostinelli, C. Auth, P. Bai, T. Eiles, J. Hicks, C.H. Jan, K. Mistry, S. Natarajan, B. Niu, P. Packan, D. Pantuso, I. Post, S. Ramey, A. Schmitz, B. Sell, S. Suthram, J. Thomas, C. Tsai, P. Vandervoorn, Self-heat reliability considerations on Intel's 22nm Tri-Gate technology, Proc. Int. Rel. Phys. Symp, 2013, pp. 5D.1.1–5D.1.5, , https://doi.org/10.1109/IRPS.2013.6532036. [9] S. Mittl, F. Guarin, Self-heating and its implications on hot carrier reliability evaluations, Proc. Int. Rel. Phys. Symp, 2015, pp. 4A.4.1–4A.4.6, , https://doi.org/10. 1109/IRPS.2015.7112726. [10] W. Weber, C. Werner, A.v. Schwerin, Lifetimes and substrate currents in static and dynamic hot-carrier degradation, International Electron Devices Meeting, 1986, pp. 390–393, , https://doi.org/10.1109/IEDM.1986.191200. [11] W. Weber, C. Werner, G. Dorda, Degradation of n-MOS-transistors after pulsed stress, IEEE Electron Device Lett. 5 (12) (1984) 518–520, https://doi.org/10.1109/ EDL.1984.26010. [12] R. Bellens, G. Groeseneken, P. Heremans, H.E. Maes, Hot-carrier degradation behavior of N- and P-channel MOSFET's under dynamic operation conditions, IEEE Trans. Electron Devices 41 (8) (1994) 1421–1428, https://doi.org/10.1109/16. 297738. [13] A. Kerber, P. Srinivasan, S. Cimino, P. Paliwoda, S. Chandrashekhar, Z. Chbili, S. Uppal, R. Ranjan, M.-I. Mahmud, F. Guarin, T. Nigam, B. Parameshwaran, Device Reliability Metric for End-of-life Performance Optimization Based on Circuit Level Assessment, IRPS, 2017, pp. 2D-3.1–2D-3.8, https://doi.org/10.1109/IRPS.2017. 7936263 (invited). [14] E. Li, E. Rosenbaum, J. Tao, G.C.-F. Yeap, M.-R. Lin, P. Fang, Hot Carrier Effects in nMOSFETs in 0.1 μm CMOS Technology, IRPS, 1998, pp. 253–258, https://doi.org/ 10.1109/RELPHY.1999.761622. [15] A. Kerber, X. Wan, Y. Liu, T. Nigam, Fast wafer-level stress-and-sense methodology for characterization of Ring-Oscillator degradation in advanced CMOS technologies, IEEE Trans. Electron Devices 62 (5) (2015) 1427–1432, https://doi.org/10.1109/ TED.2015.2415414. [16] A. Kerber, S.A. Krishnan, E.A. Cartier, Voltage ramp stress for bias temperature instability testing of metal-gate/high-k stacks, IEEE Electron Device Lett. 30 (12) (2009) 1347–1349, https://doi.org/10.1109/LED.2009.2032790. [17] A. Kerber, W. McMahon, E.A. Cartier, Voltage ramp stress for hot-carrier screening of scaled CMOS devices, IEEE Electron Device Lett. 33 (6) (2012) 749–751, https:// doi.org/10.1109/LED.2012.2189931. [18] P.M. Lee, P.K. Ko, C. Hu, Relating CMOS inverter lifetime to DC hot-carrier lifetime of NMOSFET's, IEEE Electron Device Lett. 11 (1) (1990) 39–41, https://doi.org/10. 1109/55.46924.
Fig. 6. Frequency degradation of poly-Si/SiON RO for stress voltages up to ~2× nominal use voltage (upper panel) including power law models for NBTI and HCI contributions. Comparison of projected core nFET AC HCI (f = 50 kHz) for a Vx cross-point of 0.8 to RO frequency degradation (lower panel). The gap between stress and transition time is ~1000× only considering nFET contributions.
Fig. 4) [5,13]. The change in the frequency degradation at T = 30 °C can simply be modeled by adding the power law degradation components related to BTI with a time slope of ~0.19 to describe the short stress data (dashed line) and HCI with a time slope of ~0.45 (dotted line) and a voltage dependence consistent with the literature [16,17]. To model the HCI in RO circuits with discrete devices, AC HCI test were also carried out at T = 30 °C and VDD = V2′ in Fig. 5. The projected frequency degradation (solid black symbols in Fig. 5) of discrete devices (Δf/f = ΔIdsatnFET / 2 + ΔIdsatpFET / 2), considering equal strength, is plotted together with the measured RO frequency degradation. The projected HCI contribution to match the measured RO degradation (solid line) is 105 times shorter than the AC HCI with Vx ~ 0.8·VDD which is matched with the Vg = mid-Vd DC HCI stress (see Fig. 2). The historical assumption of 50× reduction for the Vg = mid-Vd HCI contribution to RO degradation is not applicable for ultra-scaled devices while it remains valid for long channel device with gate length of 150 nm and above [18]. The physical understanding for the reduced HCI contribution in an RO for 14 nm core FinFET devices needs further investigation. The RO degradation work was further extended to a 28 nm poly-Si/ SiON technology as summarized in Fig. 6 (top panel) for 2 different stress voltages. Lack of PBTI in poly-Si/SiON gate stacks allows one to assess the HCI contribution in an RO even at T = 125 °C. The AC HCI degradation for discrete devices and the projected frequency degradation is reduced to 1000× (bottom panel of Fig. 6). The reduction in the gap between measured discrete device degradation using the AC HCI methodology and de-convoluted HCI component in RO circuits is attributed to the longer gate length as compared to 14 nm core devices. 4. Conclusion A novel AC HCI stress methodology was introduced to measure HCI degradation in discrete devices mimicking switching in logic CMOS circuits. The new methodology allows one to modulate the HCI contribution by adjusting the gate and drain waveform offsets which determines the cross-point (Vx) of Vg and Vd during circuit switching. The AC HCI test at Vx ~ 0.8·VDD yields a consistent HCI degradation kinetic
101
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Determination of DC equivalent hot carrier stress times in scaled CMOS devices using novel AC stress methodology
T
⁎
Andreas Kerber , Tanya Nigam Reliability Engineering, GLOBALFOUNDRIES Inc., 400 Stone Break Road Extension, Malta, NY 12020, USA
A R T I C LE I N FO
A B S T R A C T
Keywords: Bias temperature instability Metal gate High-k dielectrics CMOS devices
A new AC hot carrier injection (HCI) test methodology replicating the switching in digital CMOS circuits is introduced to correlate HCI in discrete scaled CMOS devices to HCI in logic circuits. This technique allows us to demonstrate that the historic 50× reduction for definition of DC HCI lifetime targets for mid-Vg stress in scaled devices should be uplifted to 1000× based on the correlation with RO degradation for poly-Si/SiON and 14 nm FinFET data. This brings significant HCI relief for device optimization in scaled technology nodes.
1. Introduction The bias temperature instability (BTI) and the hot carrier injection with contributions from conducting (HCI or c-HCI) and non-conducting (nc-HCI) stress mode are considered the most critical device degradation mechanisms in scaled CMOS technologies. While at elevated test temperature BTI is the dominant contributor to the frequency degradation in logic CMOS circuits for scaled nodes, HCI impact also needs careful review to ensure long term product reliability as the time exponent for HCI (~0.4) [1,2] is about 2× that of BTI (~0.2) [3]. In logic CMOS circuits HCI occurs during the switching events. Traditionally, DC stress has been translated to an equivalent AC stress time based on work done in earlier technology nodes. Some recent publications [4,5], have questioned this DC to AC translation in sub-100 nm gate length. A clear correlation of DC HCI to AC HCI using on-chip or [6] off-chip [7] signal generation is needed and ultimately demonstration of ring oscillator circuit degradation is required. In scaled technologies extracting purely the HCI component gets challenging due to BTI contribution and self-heating in bulk FinFET and SOI based technologies [8,9]. In this work we introduce a novel AC HCI characterization methodology that allows one to mimic device slew rates under different load condition by using synchronized waveforms and independently controlling the gate and drain input. This is an enhancement over the historical technique of applying trapezoidal signals using pulse generator units and only controlling the overlap time between gate and drain pulses [10–12]. In addition using this technique the self-heating induced enhanced degradation is reduced as current flow occurs only during switching. Contribution due to BTI in ON state cannot be
⁎
Corresponding author. E-mail address: [email protected] (A. Kerber).
https://doi.org/10.1016/j.microrel.2018.12.012 Received 1 September 2018; Accepted 27 December 2018 0026-2714/ © 2018 Published by Elsevier Ltd.
eliminated but are significantly reduced due to 1) BTI recovery during AC operation (~2× for NBTI) and 2) the ability to modulate the stress frequency and slew rate to enhance HCI. 2. Experimental setup Discrete thin oxide transistors based on 14 nm replacement metal gate (RMG) bulk-FinFET technology and a scaled poly-Si/SiON CMOS technology were subjected to conventional DC HCI (Fig. 1a), AC BTI stress and the newly introduced AC HCI stress methodology at T = 125 °C or T = 30 °C. The conventional DC HCI stress methodology applied to ultra-scaled CMOS devices uses either Vg = Vd = Vstress or Vg = mid-Vd stress. When the gate is biased using Vg = Vstress the BTI component and potential self-heating contributions in FinFET and SOI devices are enhanced which needs close attention. The Vg = mid-Vd stress condition is favored since BTI and self-heating contributions are reduced and it yields a better representation of an equivalent HCI stress condition for digital CMOS circuits like RO [13]. A typical applied voltage waveform on drain and gate terminal during AC stress is shown in Fig. 1b. In the AC HCI stress mode, a digital waveform is applied to the gate and an inverted waveform to the drain of a discrete MOSFET with specified frequency, duty cycle, rise & fall time. To modulate the HCI contribution, the gate and drain voltage signals are offset by a time Δ using synchronized remote sense amplifier units, as outlined in Fig. 1c, which determines the point (Vx) where the gate and drain voltage cross over. The transition time is defined as the duration for switching the drain voltage between the stress bias and ground which for symmetric gate and drain voltage waveforms is equal to the rise and fall times of the digital signal. A frequency range of 5 Hz
Microelectronics Reliability 93 (2019) 98–101
A. Kerber, T. Nigam
Fig. 1. Schematic illustration of conventional DC hot carrier stress (a) and the device degradation during operation of logic CMOS circuits (b). To mimic the device degradation during switching of logic CMOS circuits an AC hot carrier stress is introduced which can be modulated by shifting the gate and drain waveforms (c).
to 50 kHz was explored employing a 50% duty cycle. No frequency dependence in AC HCI degradation is observed when a constant ratio of on-time over transition-time is used. For the nc-HCI stress mode, degradation was found to be negligible for the short channel devices, referred to as core devices, at given stress condition and will not be discussed further in this paper, while in the BTI mode degradation is measurable and yields a lower bound for demonstrating HCI degradation. The measured HCI degradation under AC stress as outlined above is an integral of the various Vg and Vd bias combinations during the rise and fall transition of digital CMOS circuit operation. The Vx point represents the highest AC stress voltage at gate and drain simultaneously and thus is the critical parameter for determining the AC HCI contribution due to the high voltage acceleration of the HCI mechanism. For a cross point Vx = VDD, the complete Vg is swept at high VDD leading to worst case AC HCI for core transistors in ultra-scaled CMOS technologies [14]. It should be noted that Vx = VDD never occurs in typical logic CMOS circuits with a limited load and thus it is not a representative condition for HCI [13]. Fig. 2. Comparison of 14 nm core device AC HCI degradation to Vg = Vd and Vg = mid-Vd stress condition. AC HCI (f = 50 kHz) shows similar time evolution as DC HCI condition. The AC HCI degradation is reducing with decreasing Vx and becomes masked by xBTI.
3. Results and discussion Conventional DC HCI data taken at Vg = Vd and Vg = mid-Vd stress condition are show in Fig. 2 for 14 nm core FinFET devices using the standard ΔIdsat degradation metric for nFET and pFET devices measured at T = 125 °C. The DC HCI data is plotted versus the stress time. For Vg = Vd both device types follow a power law time evolution with time exponent, n, of ~0.45 up to degradation levels of ~20% with saturation at higher degradation [4] for the used stress voltage. For Vg = mid-Vd stress condition, nFET devices continue to show well behaved power law dependence with similar kinetic as for Vg = Vd. For pFET devices stressed at Vg = mid-Vd, however, the degradation kinetic is impacted by charge trapping causing competing effects of electron trapping and interface degradation. As result the degradation kinetic at short stress times shows significant deviation from the expected long term time evolution.
In addition, AC BTI degradation was measured with drain terminal grounded and gate terminal being altered between stress and ground (red symbols in Fig. 2) exhibiting a time slope of n ~ 0.2 for both device types. The AC BTI data is plotted versus the power-on-time which is half the stress time as a 50% duty cycle was used. It should be noted as AC BTI degradation is ranging from 0.1% to 5% it will mask HCI contributions at low degradation levels and likely dominate the kinetic behavior for such stress conditions. For AC HCI stress the measured ΔIdsat degradation is plotted versus the cumulative transition time for 3 different Vx value ranging from 0.6·VDD to 0.8·VDD (blue symbols in Fig. 2). The cumulative transition time allows one to eliminate the impact of stress frequency on the AC 99
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HCI data. To enhance the HCI contribution the transition time was chosen ~30% of the stress period to reduce the BTI component. For AC HCI the degradation monotonically decreases with decreasing Vx value. The AC HCI degradation kinetic is consistent with the DC stress conditions for nFET (Vg = Vd and Vg = mid-Vd) with the power law time exponent (~0.45) in agreement with the HCI literature [1,2]. For pFET AC HCI degradation follows the power law time exponent (~0.45) and shows no electron trapping consistent with Vg = Vd stress and typical nFET HCI degradation. This demonstrates that the proposed AC HCI stress methodology captures HCI time evolution for nFET and pFET devices. For both n-channel and p-channel FinFET devices the BTI degradation mode masks the HCI degradation for Vx ≤ 0.6·VDD as evident from the data in Fig. 2. This limits the ability of the method to determine the HCI component for small Vx values. In order to expand the Vx range to lower values a reduced stress temperature is recommended since BTI activation energy exceeds the HCI activation energy. The AC HCI data at Vx ~ 0.8·VDD overlaps the DC HCI data measured at Vg = mid-Vd for nFET devices. This indicates that Vg = midVd is an appropriate choice to capture HCI degradation in logic circuits with a standard load. Note that for pFET device such correlation cannot be established due to the electron trapping component stated previously, while kinetic and degradation is consistent with Vg = Vd stress. To confirm that Vx ~ 0.8·VDD is an appropriate choice for HCI assessment in logic circuits we simulated the voltage waveforms for an inverter RO with an asymmetric strength of nFET and pFET devices having a ratio of 0.5 and 2 (see Fig. 3). As can be seen when the pFET device is strong (upper panel of Fig. 3) the pFET crossover point Vx is 0.75·VDD compared to the case of a weak pFET (0.85·VDD) and vice versa for nFET devices. This indicates that mid-Vg DC HCI with lifetime similar to Vx = 0.8·VDD is a good reference for AC HCI contribution in an RO. Thus, one can predict the HCI contribution in RO frequency degradation by accounting for the transition time and stress frequency to extract the total mid-Vg stress time. To correlate the AC HCI in discrete device to logic CMOS circuit degradation 14 nm core FinFET device ROs were stressed at typical accelerated stress conditions beyond 2× the nominal use voltage (V1 < V2 < V3) utilizing the time resolved RO stress-and-sense methodology introduced in [15]. The RO degradation in Fig. 4 is plotted versus the stress time unlike the AC BTI and AC HCI data in
Fig. 4. Frequency degradation for inverter, NAND and NOR based RO at T = 125 °C (left) and T = 30 °C (right) using acceleration conditions > 2× nominal use voltage (V1′ < V2′ < V3′). Negligible impact of inverter load (fan-out of 1 to 4) and circuit type on frequency degradation is observed and no increase in time-slope at T = 125 °C while at T = 30 °C an increase in time slope for medium and high stress voltage is seen indicating contributions from hot carrier degradation.
Fig. 5. Comparison of RO frequency degradation with projected core nFET and pFET AC HCI (f = 5 kHz) impact for a cross-point Vx = 0.8. The gap between stress and transition time is ~105× considering combined contribution for nFET and pFET devices.
Fig. 2. At T = 125 °C the frequency degradation follows a single power law time evolution with a slope of ~0.25 obtained by linear regression stressed up to 105 s consistent with BTI being the dominant degradation mechanism (left panel of Fig. 4) for various circuit types, loads and different # of stages. The frequency degradation is independent of circuit types, loads and different # of stages suggesting negligible HCI contribution even so the time slope is slightly higher compare to AC BTI in Fig. 2. The lack of HCI is further explored by reducing the stress temperature to T = 30 °C. When the oscillators are stressed at T = 30 °C a ~10× reduction in frequency degradation is observed consistent with thermal activation of BTI for VDD = V1′. As the stress voltage is increased a change in time evolution can be observed allowing one to assess the HCI degradation in a digital CMOS circuit (right panel of
Fig. 3. Simulated voltage waveforms in a standard inverter based ring oscillator with nFet to pFET ratio of 0.5 and 2. The Vx cross-point ranges from 0.7 to 0.85. 100
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and yields a similar level of degradation as the Vg = mid-Vd HCI stress. Based on our RO and DC/AC HCI data we demonstrated that the 50× reduction for scaled devices is very conservative for a Vg = mid-Vd condition and the new DC HCI target can be reduced by 1000× for recent poly-Si/SiON technologies and potentially more for 14 nm FinFETs and beyond. Acknowledgment The author would like to acknowledge the stimulating discussions with the Reliability Engineering team at GLOBALFOUNDRIES. References [1] P. Heremans, R. Bellens, G. Groeseneken, H.-E. Maes, Consistent model for the hotcarrier degradation in n-channel and p-channel MOSFET's, IEEE Trans. Electron Devices 35 (12) (1988) 2194–2209, https://doi.org/10.1109/16.8794. [2] P. Fang, J. Tao, J.-F. Chen, C. Hu, Design in hot-carrier reliability for higher performance logic applications, IEEE Custom Integrated Circuits Conference, 1998, pp. 525–531, , https://doi.org/10.1109/CICC.1998.695033. [3] S. Mahapatra, V. Huard, A. Kerber, V. Reddy, S. Kalpat, A. Haggag, Universality of NBTI – From Devices to Circuits and Products, IRPS, 2014, pp. 3B.1.1–3B.1.8, https://doi.org/10.1109/IRPS.2014.6860615. [4] T. Nigam, B. Parameshwaran, G. Krause, Accurate Product Lifetime Predictions Based on Device-level Measurements, IRPS, 2009, pp. 634–639, https://doi.org/10. 1109/IRPS.2009.5173322. [5] A. Kerber, S. Cimino, F. Guarin, T. Nigam, Assessing Device Reliability Margin in Scaled CMOS Technologies Using Ring Oscillator Circuits, IEEE EDTM, 2017, https://doi.org/10.1109/EDTM.2017.7947495. [6] Leonhard Heiß, Andreas Lachmann, Reiner Schwab, Georgios Panagopoulos, Peter Baumgartner, Mamatha Yakkegondi Virupakshappaa, Doris SchmittLandsiedel, New Methodology for On-chip RF Reliability Assessment, IRPS, 2016, pp. 4C-5.1–4C-5.7, https://doi.org/10.1109/IRPS.2016.7574541. [7] Christian Schlünder, F. Proebster, J. Berthold, Katja Puschkarsky, Georg Georgakos, Wolfgang Gustin, Hans Reisinger, Circuit Relevant HCS Lifetime Assessments at Single Transistors With Emulated Variable Loads, IRPS, 2017, pp. 2D-2.1–2D-2.7, https://doi.org/10.1109/IRPS.2017.7936262. [8] C. Prasad, L. Jiang, D. Singh, M. Agostinelli, C. Auth, P. Bai, T. Eiles, J. Hicks, C.H. Jan, K. Mistry, S. Natarajan, B. Niu, P. Packan, D. Pantuso, I. Post, S. Ramey, A. Schmitz, B. Sell, S. Suthram, J. Thomas, C. Tsai, P. Vandervoorn, Self-heat reliability considerations on Intel's 22nm Tri-Gate technology, Proc. Int. Rel. Phys. Symp, 2013, pp. 5D.1.1–5D.1.5, , https://doi.org/10.1109/IRPS.2013.6532036. [9] S. Mittl, F. Guarin, Self-heating and its implications on hot carrier reliability evaluations, Proc. Int. Rel. Phys. Symp, 2015, pp. 4A.4.1–4A.4.6, , https://doi.org/10. 1109/IRPS.2015.7112726. [10] W. Weber, C. Werner, A.v. Schwerin, Lifetimes and substrate currents in static and dynamic hot-carrier degradation, International Electron Devices Meeting, 1986, pp. 390–393, , https://doi.org/10.1109/IEDM.1986.191200. [11] W. Weber, C. Werner, G. Dorda, Degradation of n-MOS-transistors after pulsed stress, IEEE Electron Device Lett. 5 (12) (1984) 518–520, https://doi.org/10.1109/ EDL.1984.26010. [12] R. Bellens, G. Groeseneken, P. Heremans, H.E. Maes, Hot-carrier degradation behavior of N- and P-channel MOSFET's under dynamic operation conditions, IEEE Trans. Electron Devices 41 (8) (1994) 1421–1428, https://doi.org/10.1109/16. 297738. [13] A. Kerber, P. Srinivasan, S. Cimino, P. Paliwoda, S. Chandrashekhar, Z. Chbili, S. Uppal, R. Ranjan, M.-I. Mahmud, F. Guarin, T. Nigam, B. Parameshwaran, Device Reliability Metric for End-of-life Performance Optimization Based on Circuit Level Assessment, IRPS, 2017, pp. 2D-3.1–2D-3.8, https://doi.org/10.1109/IRPS.2017. 7936263 (invited). [14] E. Li, E. Rosenbaum, J. Tao, G.C.-F. Yeap, M.-R. Lin, P. Fang, Hot Carrier Effects in nMOSFETs in 0.1 μm CMOS Technology, IRPS, 1998, pp. 253–258, https://doi.org/ 10.1109/RELPHY.1999.761622. [15] A. Kerber, X. Wan, Y. Liu, T. Nigam, Fast wafer-level stress-and-sense methodology for characterization of Ring-Oscillator degradation in advanced CMOS technologies, IEEE Trans. Electron Devices 62 (5) (2015) 1427–1432, https://doi.org/10.1109/ TED.2015.2415414. [16] A. Kerber, S.A. Krishnan, E.A. Cartier, Voltage ramp stress for bias temperature instability testing of metal-gate/high-k stacks, IEEE Electron Device Lett. 30 (12) (2009) 1347–1349, https://doi.org/10.1109/LED.2009.2032790. [17] A. Kerber, W. McMahon, E.A. Cartier, Voltage ramp stress for hot-carrier screening of scaled CMOS devices, IEEE Electron Device Lett. 33 (6) (2012) 749–751, https:// doi.org/10.1109/LED.2012.2189931. [18] P.M. Lee, P.K. Ko, C. Hu, Relating CMOS inverter lifetime to DC hot-carrier lifetime of NMOSFET's, IEEE Electron Device Lett. 11 (1) (1990) 39–41, https://doi.org/10. 1109/55.46924.
Fig. 6. Frequency degradation of poly-Si/SiON RO for stress voltages up to ~2× nominal use voltage (upper panel) including power law models for NBTI and HCI contributions. Comparison of projected core nFET AC HCI (f = 50 kHz) for a Vx cross-point of 0.8 to RO frequency degradation (lower panel). The gap between stress and transition time is ~1000× only considering nFET contributions.
Fig. 4) [5,13]. The change in the frequency degradation at T = 30 °C can simply be modeled by adding the power law degradation components related to BTI with a time slope of ~0.19 to describe the short stress data (dashed line) and HCI with a time slope of ~0.45 (dotted line) and a voltage dependence consistent with the literature [16,17]. To model the HCI in RO circuits with discrete devices, AC HCI test were also carried out at T = 30 °C and VDD = V2′ in Fig. 5. The projected frequency degradation (solid black symbols in Fig. 5) of discrete devices (Δf/f = ΔIdsatnFET / 2 + ΔIdsatpFET / 2), considering equal strength, is plotted together with the measured RO frequency degradation. The projected HCI contribution to match the measured RO degradation (solid line) is 105 times shorter than the AC HCI with Vx ~ 0.8·VDD which is matched with the Vg = mid-Vd DC HCI stress (see Fig. 2). The historical assumption of 50× reduction for the Vg = mid-Vd HCI contribution to RO degradation is not applicable for ultra-scaled devices while it remains valid for long channel device with gate length of 150 nm and above [18]. The physical understanding for the reduced HCI contribution in an RO for 14 nm core FinFET devices needs further investigation. The RO degradation work was further extended to a 28 nm poly-Si/ SiON technology as summarized in Fig. 6 (top panel) for 2 different stress voltages. Lack of PBTI in poly-Si/SiON gate stacks allows one to assess the HCI contribution in an RO even at T = 125 °C. The AC HCI degradation for discrete devices and the projected frequency degradation is reduced to 1000× (bottom panel of Fig. 6). The reduction in the gap between measured discrete device degradation using the AC HCI methodology and de-convoluted HCI component in RO circuits is attributed to the longer gate length as compared to 14 nm core devices. 4. Conclusion A novel AC HCI stress methodology was introduced to measure HCI degradation in discrete devices mimicking switching in logic CMOS circuits. The new methodology allows one to modulate the HCI contribution by adjusting the gate and drain waveform offsets which determines the cross-point (Vx) of Vg and Vd during circuit switching. The AC HCI test at Vx ~ 0.8·VDD yields a consistent HCI degradation kinetic
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