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Effective work function modulation by sacrificial gate aluminum diffusion on HfON-based 14 nm NMOS devices
Microelectronic Engineering 147 (2015) 113–116
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Effective work function modulation by sacrificial gate aluminum diffusion on HfON-based 14 nm NMOS devices C. Suarez-Segovia a,b,c,⇑, C. Leroux b, P. Caubet a, F. Domengie a, G. Reimbold b, G. Romano a,b, O. Gourhant a, V. Joseph a, G. Ghibaudo c a b c
STMicroelectronics, 850 rue Jean Monnet, 38926 Crolles cedex, France CEA-LETI Minatec, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France IMEP-LAHC, Minatec/INPG, BP 257, 38016 Grenoble, France
a r t i c l e
i n f o
Article history: Received 21 February 2015 Received in revised form 27 March 2015 Accepted 8 April 2015 Available online 16 April 2015 Keywords: Metal gate Effective work function Dipole Aluminum diffusion CV measurements
a b s t r a c t Sacrificial gate first process efficiency to further increase effective work function (WFeff) towards P+ by metallic aluminum diffusion is demonstrated in this work by combining capacitance vs voltage (CV) measurements on beveled oxides with different spectroscopic techniques. Aluminum diffusion role on WFeff is evidenced and is found to be simultaneously dependent of as-deposited aluminum dose and annealing temperature. Ó 2015 Elsevier B.V. All rights reserved.
1. Introduction The scaling of MOS transistors while keeping overall performances led to the inclusion of high-j metal gate (HKMG) stack in the conventional SiO2/Poly-Si gate stack. The effective work function (WFeff) values of metal electrodes must satisfy the VTH requirements of specific devices. In undoped-channel 14 nm Fully-Depleted Silicon on Insulator (FD-SOI) devices, WFeff at only 100 mV from the midgap are required [1,2]. In order to reach the DWFeff specification for PMOS, deposition of Al2O3 as high-j dielectric, or above the high-j layer [3] and insertion of metallic aluminum in TiN gate [4] have already been proposed to shift the WFeff towards P+. Nevertheless, opposite shift of the Al-based metal workfunction towards N+ limits the benefit of dipoles induced by Al diffusion to the high-j/SiO2 interface. Even though aluminum ion implantation is very effective in achieving PMOS low VTH, it can induce gate leakage degradation by Al diffusion too deeply near SiO2/channel interface [5]. In this work, we evaluate the impact of Al on WFeff and Equivalent Oxide Thickness (EOT) in a sacrificial metal gate-first approach. Moreover, the Al diffusion is studied by X-ray Photoelectron Spectroscopy (XPS) and X-ray
⇑ Corresponding author at: STMicroelectronics, 850 rue Jean Monnet, 38926 Crolles cedex, France. E-mail address: [email protected] (C. Suarez-Segovia). http://dx.doi.org/10.1016/j.mee.2015.04.062 0167-9317/Ó 2015 Elsevier B.V. All rights reserved.
Fluorescence (XRF) measurements as a function of the aluminum dose, the composition of the TiN layers and the annealing temperature. 2. Device fabrication Silicon trench isolation (STI) and P-Well implants were carried out on Si (1 0 0) wafers before HKMG stack deposition. The gate dielectrics consist of interlayer dielectric followed by a 2 nm thick HfO2 layer deposited by Atomic Layer Deposition, and decoupled plasma nitridation. Interlayer dielectric is either 1 nm thick SiON for nominal devices or a beveled thermally grown SiO2 (Fig. 1) to get rid of Si/SiO2 interface fixed charges ðQ Si02 =Si Þ in WFeff extraction. Then, the sacrificial Si/TiN/Al/TiN gate stacks (Si on top) with different Al doses (0 Å, 2 Å, 6 Å) and TiN compositions ([N2]/ ([N2] + [Ar])) = 0.5, 0.7 and 1) were deposited, followed by a thermal treatment under N2 atmosphere at 900 °C or 1000 °C in order to activate the diffusion of Al into the HfON/SiON stack. The sacrificial gate stack is then removed by wet etching. Finally, a Poly-Si/TiN electrode is deposited, followed by gate patterning, as illustrated in Fig 2. All metal layers were deposited in Radio Frequency Physical Vapor Deposition chambers. Samples description is summarized in Table 1. Devices were completed with S/D formation, S/D dopant activation annealing at 1005 °C, NiPt silicide and a 400 °C forming gas annealing.
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Fig. 1. Ellipsometry and CV measurements on bevel oxide along a 300 mm wafer.
Sacrificial gate deposition & diffusion annealing
Sacrificial gate wet removal
Fig. 3. WFeff vs EOT for devices with beveled oxide: with Al (annealed at 1000 °C) and without Al (annealed at 900 °C) in sacrificial gate and w/o sacrificial gate. TiN and Al thicknesses are in Å.
Final gate deposition & Anneal S/D
Poly-Si
Si-cap Sacrificial
Final
HfON
HfON
HfON
SiON
SiON
SiON
substrate
substrate
substrate
Fig. 2. Sacrificial gate first approach scheme.
Table 1 Description of devices with aluminum in sacrificial gate.
No sacrificial TiN80-w/o Al TiN/Al2.0/TiN TiN/Al2.0/TiN TiN/Al6.0/TiN PS/Al2.0/PS PS/Al6.0/PS FN/Al2.0/FN FN/Al6.0/FN
Fig. 4. Impact of Al thickness inserted in final gate electrode.
IL oxide
TiN composition Al dose (Å) Diffusion N2/(Ar + N2) annealing
Bevel Bevel Bevel Nominal Nominal Nominal Nominal Nominal Nominal
– 0.5 (51.3 N-at%) 0.5 (51.3 N-at%) 0.5 (51.3 N-at%) 0.5 (51.3 N-at%) 0.7 (52.6 N-at%) 0.7 (52.6 N-at%) 1 (54.6 N-at%) 1 (54.6 N-at%)
– 0 2.0 2.0 6.0 2.0 6.0 2.0 6.0
Only S/D annealing 900 °C 1000 °C 900 °C 900 °C 900 °C 900 °C 900 °C 900 °C
3. Electrical characterization EOT and Vfb were extracted by fitting Poisson Schrödinger quantum simulations with experimental CV measurements on different dies along the wafer [6]. Assuming (1) no bulk charge in the dielectrics and (2) independence of Vfb with HK thickness, Vfb dependence with EOT is given by Eq. (1), where eox is the dielectric permittivity of SiO2, WF m and WFSi are the metal and silicon work function relative to vacuum, respectively, and d denotes the sum of interfacial dipoles [7]. WFeff expression is then calculated from Vfb using Eq. (2):
qVfb ¼ WFm þ d Q SiO2 =Si WFeff ¼ qVfb þ WFSi
EOT
eox
WFSi
ð1Þ ð2Þ
Fig. 5. CV curve as a function of Al thickness in sacrificial gate approach (diffusion annealing at 900 °C). TiN and Al thicknesses are in Å.
The plot WFeff vs EOT for devices with beveled oxide is shown in Fig. 3. The extrapolation of WFeff to zero EOT allows the assessment of only WFm and d, without the impact of Si/SiO2 interface fixed charges [8]. Compared to devices for which Al was not included in sacrificial gate stack, we note that Al in sacrificial gate shifts the WFeff 150 meV towards P+. Compared to the final metal approach (Fig. 4), (i.e., metallic aluminum deposited in the PolySi/TiN final electrode and no sacrificial gate), the WFeff shift
C. Suarez-Segovia et al. / Microelectronic Engineering 147 (2015) 113–116
115
Fig. 6. WFeff vs EOT for devices with nominal dielectric and different Al thicknesses (annealed at 900 °C). Blue (purple) symbols refer to 2 Å (6 Å) of Al. (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)
Fig. 9. Quantification of Al amount by X-ray Fluorescence on as-deposited wafers compared to those annealed at 900 °C and 1000 °C after wet sacrificial gate removal.
Fig. 7. WFeff vs EOT for nominal devices with different TiN composition (Stoeichio, PS for N-rich TiN and FN for N-rich+ TiN, with or without Al (annealed at 900 °C).
Fig. 10. ToF-SIMS depth profiles of 2 Å-thick Al in 20 nm-thick HfO2 as a function of annealing temperature. Si+, Ti+ and HfO+ ions spectra (not shown here) were used to place Si/TiN and TiN/HfO2 interfaces.
gates may still not linearly increase with Al thickness for devices with nominal dielectric, as observed in Figs. 5 and 6. On the other hand, no impact of nitrogen composition of TiN layers was reported on WFeff (Fig 7), in agreement with our previous results [9]. 4. Diffusion characterization on blanket wafers
Fig. 8. X ray Photoelectron Spectroscopy Al2p peak of HfON/SiON stack after sacrificial gate deposition, annealing and wet removal for different Al doses and annealing temperatures.
induced by the insertion of 2 Å of Al is 100 mV larger with the sacrificial gate approach. Since sacrificial gate stack is totally removed, the opposite shift towards N+ of the Al-based metal work function (see WFm effect in Fig. 4) is cancelled; consequently the dipole benefit induced by Al diffusion is stronger with sacrificial gate approach. However, we report for the first time that the WFeff shift obtained with sacrificial
This dependence with Al thickness has been clarified by XPS (Fig. 8) and XRF (Fig. 9) measurements performed (a) after sacrificial gate stack deposition and (b) after diffusion annealing and sacrificial gate stack removal. We notice a substantially lower Al diffusion at 900 °C in the case of a 6 Å-thick Al layer, corroborating the CV measurements of Fig. 5. An annealing at 1000 °C is necessary to drive significantly Al in gate stack. Indeed, XRF measurements show that Al diffusion into the HfON/SiON stack is limited even after annealing at 900 °C: only 30% for 2 Å of Al and 5–10% for 6 Å and 10 Å of Al. In contrast, with annealing at 1000 °C, Al driven in dielectric increases with the Al thickness inserted in sacrificial gate. This reduction of Al diffusion at lower temperatures for thicker Al thicknesses could be related to Al precipitation in TiN already seen for Al thicker layers [10]. ToF-SIMS (Fig. 10) has confirmed the crucial role of annealing temperature on Al diffusion profile in gate stack. 5. Conclusion Sacrificial gate-first approach is effective to further increase WFeff towards P+ by aluminum diffusion, avoiding the undesirable
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C. Suarez-Segovia et al. / Microelectronic Engineering 147 (2015) 113–116
opposite shift towards N+ of the Al-based metal work function. However, CV measurements have shown that unexpected WFeff decrease may still be observed with sacrificial gate. The crucial impact of diffusion annealing on Al driven in HfON/SiON stack has been highlighted through different spectroscopic techniques (XPS, XRF and ToF-SIMS). Acknowledgements Authors would like to acknowledge E. Martinez from CEA-LETI for XPS training. We want also to acknowledge M. Juhel and K. Dabertrand from STMicroelectronics for SIMS and XRF measurements, respectively. This work was carried out in the frame of LETI/ST joint program and PLACES2BE project.
References [1] [2] [3] [4] [5] [6] [7] [8] [9]
O. Weber, et al., Proc. IEDM (2010, San Francisco, CA, USA), 58–61. H. Shimada et al., IEEE TED 44 (1997) 1903–1907. M. Charbonnier, et al., VLSI-TSA (2010), pp. 84. S. Baudot et al., Microelectron. Eng. 88 (2011) 1305–1308. Y. Chen et al., IEEE-EDL 31 (2010) 1290–1292. C. Leroux et al., Microelectron. Eng. 84 (2007) 2408–2411. M. Charbonnier et al., IEEE-TED (2010) 1809–1819. V.S. Kaushik et al., IEEE-TED 53 (2006) 2627–2633. C. Suarez-Segovia et al., Ext. Abstracts of SSDM (2014, Tsukuba, Japan), pp. 838–839. [10] F. Panciera et al., APL 100 (2012) 201909.
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Effective work function modulation by sacrificial gate aluminum diffusion on HfON-based 14 nm NMOS devices C. Suarez-Segovia a,b,c,⇑, C. Leroux b, P. Caubet a, F. Domengie a, G. Reimbold b, G. Romano a,b, O. Gourhant a, V. Joseph a, G. Ghibaudo c a b c
STMicroelectronics, 850 rue Jean Monnet, 38926 Crolles cedex, France CEA-LETI Minatec, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France IMEP-LAHC, Minatec/INPG, BP 257, 38016 Grenoble, France
a r t i c l e
i n f o
Article history: Received 21 February 2015 Received in revised form 27 March 2015 Accepted 8 April 2015 Available online 16 April 2015 Keywords: Metal gate Effective work function Dipole Aluminum diffusion CV measurements
a b s t r a c t Sacrificial gate first process efficiency to further increase effective work function (WFeff) towards P+ by metallic aluminum diffusion is demonstrated in this work by combining capacitance vs voltage (CV) measurements on beveled oxides with different spectroscopic techniques. Aluminum diffusion role on WFeff is evidenced and is found to be simultaneously dependent of as-deposited aluminum dose and annealing temperature. Ó 2015 Elsevier B.V. All rights reserved.
1. Introduction The scaling of MOS transistors while keeping overall performances led to the inclusion of high-j metal gate (HKMG) stack in the conventional SiO2/Poly-Si gate stack. The effective work function (WFeff) values of metal electrodes must satisfy the VTH requirements of specific devices. In undoped-channel 14 nm Fully-Depleted Silicon on Insulator (FD-SOI) devices, WFeff at only 100 mV from the midgap are required [1,2]. In order to reach the DWFeff specification for PMOS, deposition of Al2O3 as high-j dielectric, or above the high-j layer [3] and insertion of metallic aluminum in TiN gate [4] have already been proposed to shift the WFeff towards P+. Nevertheless, opposite shift of the Al-based metal workfunction towards N+ limits the benefit of dipoles induced by Al diffusion to the high-j/SiO2 interface. Even though aluminum ion implantation is very effective in achieving PMOS low VTH, it can induce gate leakage degradation by Al diffusion too deeply near SiO2/channel interface [5]. In this work, we evaluate the impact of Al on WFeff and Equivalent Oxide Thickness (EOT) in a sacrificial metal gate-first approach. Moreover, the Al diffusion is studied by X-ray Photoelectron Spectroscopy (XPS) and X-ray
⇑ Corresponding author at: STMicroelectronics, 850 rue Jean Monnet, 38926 Crolles cedex, France. E-mail address: [email protected] (C. Suarez-Segovia). http://dx.doi.org/10.1016/j.mee.2015.04.062 0167-9317/Ó 2015 Elsevier B.V. All rights reserved.
Fluorescence (XRF) measurements as a function of the aluminum dose, the composition of the TiN layers and the annealing temperature. 2. Device fabrication Silicon trench isolation (STI) and P-Well implants were carried out on Si (1 0 0) wafers before HKMG stack deposition. The gate dielectrics consist of interlayer dielectric followed by a 2 nm thick HfO2 layer deposited by Atomic Layer Deposition, and decoupled plasma nitridation. Interlayer dielectric is either 1 nm thick SiON for nominal devices or a beveled thermally grown SiO2 (Fig. 1) to get rid of Si/SiO2 interface fixed charges ðQ Si02 =Si Þ in WFeff extraction. Then, the sacrificial Si/TiN/Al/TiN gate stacks (Si on top) with different Al doses (0 Å, 2 Å, 6 Å) and TiN compositions ([N2]/ ([N2] + [Ar])) = 0.5, 0.7 and 1) were deposited, followed by a thermal treatment under N2 atmosphere at 900 °C or 1000 °C in order to activate the diffusion of Al into the HfON/SiON stack. The sacrificial gate stack is then removed by wet etching. Finally, a Poly-Si/TiN electrode is deposited, followed by gate patterning, as illustrated in Fig 2. All metal layers were deposited in Radio Frequency Physical Vapor Deposition chambers. Samples description is summarized in Table 1. Devices were completed with S/D formation, S/D dopant activation annealing at 1005 °C, NiPt silicide and a 400 °C forming gas annealing.
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C. Suarez-Segovia et al. / Microelectronic Engineering 147 (2015) 113–116
Fig. 1. Ellipsometry and CV measurements on bevel oxide along a 300 mm wafer.
Sacrificial gate deposition & diffusion annealing
Sacrificial gate wet removal
Fig. 3. WFeff vs EOT for devices with beveled oxide: with Al (annealed at 1000 °C) and without Al (annealed at 900 °C) in sacrificial gate and w/o sacrificial gate. TiN and Al thicknesses are in Å.
Final gate deposition & Anneal S/D
Poly-Si
Si-cap Sacrificial
Final
HfON
HfON
HfON
SiON
SiON
SiON
substrate
substrate
substrate
Fig. 2. Sacrificial gate first approach scheme.
Table 1 Description of devices with aluminum in sacrificial gate.
No sacrificial TiN80-w/o Al TiN/Al2.0/TiN TiN/Al2.0/TiN TiN/Al6.0/TiN PS/Al2.0/PS PS/Al6.0/PS FN/Al2.0/FN FN/Al6.0/FN
Fig. 4. Impact of Al thickness inserted in final gate electrode.
IL oxide
TiN composition Al dose (Å) Diffusion N2/(Ar + N2) annealing
Bevel Bevel Bevel Nominal Nominal Nominal Nominal Nominal Nominal
– 0.5 (51.3 N-at%) 0.5 (51.3 N-at%) 0.5 (51.3 N-at%) 0.5 (51.3 N-at%) 0.7 (52.6 N-at%) 0.7 (52.6 N-at%) 1 (54.6 N-at%) 1 (54.6 N-at%)
– 0 2.0 2.0 6.0 2.0 6.0 2.0 6.0
Only S/D annealing 900 °C 1000 °C 900 °C 900 °C 900 °C 900 °C 900 °C 900 °C
3. Electrical characterization EOT and Vfb were extracted by fitting Poisson Schrödinger quantum simulations with experimental CV measurements on different dies along the wafer [6]. Assuming (1) no bulk charge in the dielectrics and (2) independence of Vfb with HK thickness, Vfb dependence with EOT is given by Eq. (1), where eox is the dielectric permittivity of SiO2, WF m and WFSi are the metal and silicon work function relative to vacuum, respectively, and d denotes the sum of interfacial dipoles [7]. WFeff expression is then calculated from Vfb using Eq. (2):
qVfb ¼ WFm þ d Q SiO2 =Si WFeff ¼ qVfb þ WFSi
EOT
eox
WFSi
ð1Þ ð2Þ
Fig. 5. CV curve as a function of Al thickness in sacrificial gate approach (diffusion annealing at 900 °C). TiN and Al thicknesses are in Å.
The plot WFeff vs EOT for devices with beveled oxide is shown in Fig. 3. The extrapolation of WFeff to zero EOT allows the assessment of only WFm and d, without the impact of Si/SiO2 interface fixed charges [8]. Compared to devices for which Al was not included in sacrificial gate stack, we note that Al in sacrificial gate shifts the WFeff 150 meV towards P+. Compared to the final metal approach (Fig. 4), (i.e., metallic aluminum deposited in the PolySi/TiN final electrode and no sacrificial gate), the WFeff shift
C. Suarez-Segovia et al. / Microelectronic Engineering 147 (2015) 113–116
115
Fig. 6. WFeff vs EOT for devices with nominal dielectric and different Al thicknesses (annealed at 900 °C). Blue (purple) symbols refer to 2 Å (6 Å) of Al. (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)
Fig. 9. Quantification of Al amount by X-ray Fluorescence on as-deposited wafers compared to those annealed at 900 °C and 1000 °C after wet sacrificial gate removal.
Fig. 7. WFeff vs EOT for nominal devices with different TiN composition (Stoeichio, PS for N-rich TiN and FN for N-rich+ TiN, with or without Al (annealed at 900 °C).
Fig. 10. ToF-SIMS depth profiles of 2 Å-thick Al in 20 nm-thick HfO2 as a function of annealing temperature. Si+, Ti+ and HfO+ ions spectra (not shown here) were used to place Si/TiN and TiN/HfO2 interfaces.
gates may still not linearly increase with Al thickness for devices with nominal dielectric, as observed in Figs. 5 and 6. On the other hand, no impact of nitrogen composition of TiN layers was reported on WFeff (Fig 7), in agreement with our previous results [9]. 4. Diffusion characterization on blanket wafers
Fig. 8. X ray Photoelectron Spectroscopy Al2p peak of HfON/SiON stack after sacrificial gate deposition, annealing and wet removal for different Al doses and annealing temperatures.
induced by the insertion of 2 Å of Al is 100 mV larger with the sacrificial gate approach. Since sacrificial gate stack is totally removed, the opposite shift towards N+ of the Al-based metal work function (see WFm effect in Fig. 4) is cancelled; consequently the dipole benefit induced by Al diffusion is stronger with sacrificial gate approach. However, we report for the first time that the WFeff shift obtained with sacrificial
This dependence with Al thickness has been clarified by XPS (Fig. 8) and XRF (Fig. 9) measurements performed (a) after sacrificial gate stack deposition and (b) after diffusion annealing and sacrificial gate stack removal. We notice a substantially lower Al diffusion at 900 °C in the case of a 6 Å-thick Al layer, corroborating the CV measurements of Fig. 5. An annealing at 1000 °C is necessary to drive significantly Al in gate stack. Indeed, XRF measurements show that Al diffusion into the HfON/SiON stack is limited even after annealing at 900 °C: only 30% for 2 Å of Al and 5–10% for 6 Å and 10 Å of Al. In contrast, with annealing at 1000 °C, Al driven in dielectric increases with the Al thickness inserted in sacrificial gate. This reduction of Al diffusion at lower temperatures for thicker Al thicknesses could be related to Al precipitation in TiN already seen for Al thicker layers [10]. ToF-SIMS (Fig. 10) has confirmed the crucial role of annealing temperature on Al diffusion profile in gate stack. 5. Conclusion Sacrificial gate-first approach is effective to further increase WFeff towards P+ by aluminum diffusion, avoiding the undesirable
116
C. Suarez-Segovia et al. / Microelectronic Engineering 147 (2015) 113–116
opposite shift towards N+ of the Al-based metal work function. However, CV measurements have shown that unexpected WFeff decrease may still be observed with sacrificial gate. The crucial impact of diffusion annealing on Al driven in HfON/SiON stack has been highlighted through different spectroscopic techniques (XPS, XRF and ToF-SIMS). Acknowledgements Authors would like to acknowledge E. Martinez from CEA-LETI for XPS training. We want also to acknowledge M. Juhel and K. Dabertrand from STMicroelectronics for SIMS and XRF measurements, respectively. This work was carried out in the frame of LETI/ST joint program and PLACES2BE project.
References [1] [2] [3] [4] [5] [6] [7] [8] [9]
O. Weber, et al., Proc. IEDM (2010, San Francisco, CA, USA), 58–61. H. Shimada et al., IEEE TED 44 (1997) 1903–1907. M. Charbonnier, et al., VLSI-TSA (2010), pp. 84. S. Baudot et al., Microelectron. Eng. 88 (2011) 1305–1308. Y. Chen et al., IEEE-EDL 31 (2010) 1290–1292. C. Leroux et al., Microelectron. Eng. 84 (2007) 2408–2411. M. Charbonnier et al., IEEE-TED (2010) 1809–1819. V.S. Kaushik et al., IEEE-TED 53 (2006) 2627–2633. C. Suarez-Segovia et al., Ext. Abstracts of SSDM (2014, Tsukuba, Japan), pp. 838–839. [10] F. Panciera et al., APL 100 (2012) 201909.