Sensor on silicon gate NMOS multi-project chips

Sensor on silicon gate NMOS multi-project chips by M. R. Haskard S. Australia Institute of Technology, Adelaide, S.Australia

To interface VLSI chips to the real or physical world sensors are required. A range of sensors including thermal, optical, magnetic and strain devices were incorporated on experimental multi-project chips and results are reported.

Symbols ot

B Cox E

Temperature coefficient of the threshold voltage Normal component of magnetic field Gate oxide capacity/unit area Axial strain

Generation rate of electron hole pairs 1 Average current k Boltzmann's constant K Proportionality constant L Device length Diffusion length for electrons and holes L1,Lh Carrier density n Powers constants ~,Y qa Electrical resistance Hall coefficient RH Device thickness t Temperature ~ T Carder mobility Band gap voltage extrapolated to zero temperature Vgo Bias voltage V~ Width of depletion region W W Device width G

1. Introduction There is a growing interest in including sensors on digital integratedcircuits so that VLSI devices can interface directly with the physical or real world. Since most sensors are analogue in nature, the signals derived from them must normally be convened into a digital form. Assuming that the remainder of the chip has some intelligence, then there are a number of simple techniques that can be used; excluding the obvious approach of using a separate analogue to digital convener. Examples include voltage (or current) to frequency conversion, voltage (or current) to time conversion, ring oscillators and lateral inhibition (8). MICROELECTRONICS JOURNAL Vo115 No 5 9 1984 Benn Electronics Publications Lid, Luton

23

Sensors on silicon gate NMOS multi-project chips continued from page 23

A basic problem in designing smart sensors is to have some appreciation of the properties of integrated sensors. This paper examines the characteristics of a number of sensors fabricated on Australia's first multiproject Chip AUSMPC5/82 (9).

2.

Sensor Types Evaluated

One of the penalties of using multiproject chips is that any one of a number of foundries may be selected by the silicon broker with the net result that large parameter variations can occur (7). In this instance the particular chip was fabricated by two different American founderies so that results provided an indication of device spreads from one fabricator to the next. The experimental sensors fabricated included thermal, optical, magnetic and strain devices.

2.1 Thermal Sensors The simplest temperature dependent components are the N § diffusion and polysilicon resistors. Here the temperature dependent resistance is given by (6). KLT R(T)

.........................................................

-

(1)

qnWt Fig. 1 shows the temperature characteristic of resistors from the two fabricators. Comparing these results with equation (1) and noting that the reference indicates that-0 is also temperature dependent, measured values for r/, over the temperature range 0 to 50~ vary from 0.45 to 0.60 for N + diffused and 0.17 to 0.24 for polysilicon resistors. Inspection of the results suggests that a good approximation for modelling their characteristics could be obtained by simply applying linear regression techniques. Thus for polysilicon the slope is typically 7.58 x 10-4 and intercept 0.775 while for N + diffusion resistors the slope is 1.80 x 10-3 and intercept typically 0.470. An alternative approach to making a thermal sensor is to make use of the reverse or forwrd characteristics of a junction diode. With the NMOS process it is unusual to use a forward biased diode, however measurements made on diodes with a forward bias current of 10-gA/m 2 gave a forward voltage temperature coefficient of -2.26mV/~ Considering now the more usual reverse biased diode. Since the leakage current depends heavily upon minority carriers one would expect considerable variations from one manufacturer to another. Such is the case, (see Fig. 2) for there is a difference of five orders of magnitude between the two manufacturers. An expression often used to model a diode leakage current is I0 = K L W T7 exp I

-

qVgc

kT

1

..............................................

(2)

with y having a typical value of 1.5. Examination of Fig. 2 suggests that the change in current with temperature is dominated by an exponential term (currents approximately double for every 8~ temperature rise) and therefore a simpler expression of

I0 = C1LW exp[-C2qVgc]kT

..............................................

(3)

is a more satisfactory model. For manufacturer 1, C1=0.540, C2=0.768 while for manufacturer 2, C1=0.647 and C2=5.454.

24

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Fig.

1

Temperature

O

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t/~ ta.l ~-.42::~ t o _.,I ta.l ,OC

characteristics

o f N ~" d i f f u s i o n

and polysilicon

resistors.

The final thermal sensor type evaluated was a MOS transistor. The rate of change of the gate gource voltage with respect to temperature is given by (1).

:

/kSxW

.............................

(4)

25

Sensors on silicon gate NMOS multi-project chil~ continued from page 25

READING x I0-19A DIODE DARKCURRENT PER um SQUARE.23/8/83

MANUFACTURER I

I000 DARK CURRENT

§ MANUFACTURER 2

lO0

READING X I0-14A

IO

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20

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TEMPERATURE ~

Fig. 2

R e v e r s e b i a s d i o d e l e a k a g e c u r r e n t s as a f u n c t i o n o f t e m p e r a t u r e .

Thus below some drain current level the temperature coefficient of the gate source voltage is negative while above it, it becomes positive. Measurements made on both enhancement and depletion transistors of drawn width 20/.tm and length 5,urn indicate that the zero temperature coefficient occurred at very low currents, typically 0.3/.tA for the enhancement and 2.5,uA for the depletion transistor. The temperature coefficient for the enhancement transistor in the positive region was typically 12.5p.V/~ 26

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Spectral response of photo diode (a) Variations with batch and manufacture (b) Effect of no overglaze. 27

on silicon gate N M O S multi-project chips continued from page 27

Sensors

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Optical Sensors Diodes can be operated in a photo conductive or photo voltaic mode. The light generated current is given by (5).

2.2

IL = qLWG (Le + Lh + w)

........

. ......................................

(5)

whil6 the open circuit voltage is VL

28

=

kT in q

~

( ~IL Io

\

+

1

................................................

(6)

Two photo diodes were included in the sensor chip, one with overglaze the other without. Meaurements indicated that the overglaze had little effect on the sensitivities and spectral response (Fig. 3). However, it does appear that the thickness of the second 'oxide' layer between the polysilicon and metal does play an important part. This is surprising since capacitive measurements suggest both oxides are of similar thickness. Table I compares typical photo voltaic characteristics of the 100/.tm square diodes. TABLE I Sensitivity of 100/.tm square photo diodes to a tungsten filament lamp. Manufacturer 2 Parameter

Manufacturer l Run 5/82 Overglaze

No overglaze

Overglaze

Vo/r

0.464

0.463

I~/r

1.60

1.25

Run 5/83

No overglaze

Overglaze

0.120

0.123

0.07

0.75

0.80

0.95

2.3 Magnetic S e n s o r s The normal method of designing Hall effect devices is to use the high resistivity epitaxial layer of a bipolar process to achieve a large mobility factor. Unfortunately, this layer is not available on the NMOS process so the implant region of a depletion transistor was used instead. The device designed, and shown on the right in Fig. 4, is unconventional in that it could be operated in either a voltage or current mode. No subsidiary gate region (2) was added to cancel piezo resistance offset effects which occur when the chips are mounted on substrates.

I iiiill

Fig. 4

Experimental Ilall effect and match strain NMOS depletion transistor sensors. 29

Sensors on silicon giite NMOS multi-project c h ~ continued from page 29

In the current drive mode the output Hall effect voltage is given by RHIB VH =

. ........................................................

(7)

t

while with voltage drive (3) V~tLBW v.

=

. ..........

: .............................................

(8)

L When the sensor is operated in an output current configuration (4) the Hall effect current is given by In = C/~BI

............................................................

(9)

Figures 5, 6 and 7 show characteristics of sensors operated in both configurations. For N M O S smart sensors, the current configuration would appear to be the preferred method.

HALL VOLTAGE TAMB : 21.5~

30

20 Vo/c mV

~

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FLUXTESLA

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HALL VOLTAGE OFFSETCORRECTED Vo/c TAMB: 21.5oc OFFSET = lO.9mV (max)

20

OFFSET = 2.9mY (min)

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= uI _

I d = I08~A

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0

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0.05

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1 .DO

FLUXTESLA

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Fig. 5 Spreads in }tall effect output voltage both within a batch and from manufacturer to manufacturer. Bias current 100/~A. 31

Sensors on silicon gate

NMOS multl-project chips continued from page 3 T

HALL CURRENT I -- IOOuA

I

Tamb = 21%

0.6

'

§

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X 11, 12 avg = 12.39pA 0 1I , 12 avg = 13.22~A

-0.10

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0.05

-0.05

0.10 FLUX TESLA

-0.2

-0.4

MRH 8/83

Fig. 6 Variations in Hall effect output voltage with gate bias. Drain'source bias 5 volts.

2.4 Strain Sensors 9 The piezo resistive prope.rties of silicon were investigated using N + diffusion, polysilicon and depletion transistors and resistors in tension. A problem encountered in mounting chips to the alumina substrate, was that the strain gauge adhesive was non conductive and yet an electrical contact had to be made to the rear of the chip to control the back gate voltage. A top surface contact at the beginning of the multiproject chip startingframe would have solved this problem. The gauge factor K for a semiconductor piezo resistance device is given by (10). AR/R KE 32

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Fig. 7

Hall effect current for two manufacturers and two different geometry ratios.

33

m u l t i - p r o j e c t chips continued from page 33

S e n s o r s o n silicon g a t e N M O S

Figures 8 and 9 show the results of these strain measurements for devices made by both manufacturers. Even though measurements were repeated the N i diffusion and polysilicon resistors tended to show very non-linear characteristics at initial low strain levels suggesting that the adhesion material may not be transmitting the correct stress. With the depletion transistor this effect was not evident even though the same strain gauge adhesive was used. Typical measured ranges for gauge factors are shown in Table II while Table III provides matching information on long depletion transistor devices.

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34

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T A B L E II M e a s u r e d gauge factors for various strain gauges. Strain Gauge Device

Gauge Factor Range

N * diffused resistor

-10 to-70

Polysilicon resistor

-10 to -60

Depletion NMOS transistor

-20 to -40

-

35

Sensors on silicon gate NMOS multi-project chips continued from page 35

T A B L E III M e a s u r e d piezo resistance parameters for long depletion mode NMOS transistors. Vbs = 5 volts, Vs ~ub = 0 volts, Ta~b = 20~ Manufacturer I

Manufacturer 2

Parameter Vr~ = 0 Matching initial static drain current Average sensitivity XI0-3%/#m/m Matching of sensitivity

3.

V~ = 5V

V~ = 0

V~ = 5V

i

0.6% 2.9 ---15%

2.0%

42%

3.1 --7.5%

+-52%

1.8

3.8

Conclusions

T h e work undertaken thus far suggests that a range of sensor types is possible on multiproject chips. Circuits incorporating such sensors may have to work with sensor pairs in a differential m o d e to a c c o m m o d a t e the large manufactured p a r a m e t e r variations as well as temperature effects. For absolute value readings, individual calibration will be necessary with scaling factors and linearity p a r a m e t e r s p r o g r a m m e d into the smart sensor.

4.

References

[1] Blauschild, R. A., Tucci, P. A., Muller, R. S. et al. "A new NMOS temperature stable voltage reference", IEEEJ. Solid-State Circuits, Vol. SC-13, (1978), p.767-774. [2] Braun, R. J., Chai, H. D. and Ebert, W. W. "FET I fall transducer with control gates", IBM Tech. Dis. Bullethz, Voi. 17, No. 7 (1974), p.1895-1896. [3] Chein, C. L. and Westgate, C. R. "The Hall effect and its applications", Plenum Press, N.Y. (1980). [4] Davies, L. W. and Barnicoat, G. P. "Integrated Hall current element", International Conference on Microelectronics, Circuits and System Theory, Sydney, Australia (1970), p.32-33. [5] Green, M. A. "Solar Cells", Prentice Hall (1982). [6] Hamilton, D. J. and Howard, W. G. "Basic integrated circuit engineering", McGraw-Hill (1975). [7] Haskard, M. R. "Experiments towards a standard interface to fabrication for analogue circuits", CSIRO VLSI Technical Report, 83-1, (I 983). [8] Lyons, R. F. "The optical mouse", Xerox Corporation TechnicalReport, VLS181-1 (1981). [9] Mudge, J. C., Clarke, R. J., Paltridge, M. L. and Potter, R. J. "Results of AUSMPC 5/82", VLSI Design, (January/February 1983), p.52-56. [I0] Window, A. L. and Holiser, G. S. "Strain gauge technology", Applied Science, (1982).

36