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Effects of polar functional groups and roughness topography of polymer gate dielectric layers on pentacene field-effect transistors
Organic Electronics 8 (2007) 336–342 www.elsevier.com/locate/orgel
Effects of polar functional groups and roughness topography of polymer gate dielectric layers on pentacene field-effect transistors Kwonwoo Shin, Sang Yoon Yang, Chanwoo Yang, Hayoung Jeon, Chan Eon Park * Polymer Research Institute, Department of Chemical Engineering, Pohang University of Science and Technology (POSTECH), Pohang 790-784, Republic of Korea Received 21 August 2006; received in revised form 7 December 2006; accepted 15 December 2006 Available online 8 January 2007
Abstract The present study analyzed the effects of the polar functional groups and rough topography of the gate dielectric layer on the characteristics of pentacene field-effect transistors. For this purpose, prior to deposition of the organic semiconductor, we introduced polar functional groups and created a rough topography onto the poly(methylmethacrylate)/Al2O3 gate dielectric layer using oxygen plasma treatment, and controlled the number of polar groups using an aging process. The mobility decrease observed after oxygen plasma treatment ranged from 0.2 to <0.01 cm2/V s and was related to the many polar functional groups and the rough topography of the gate dielectric, which formed localized trap states in the band gap and created disorder in the crystal structure. In addition, the electric dipole of the polar groups and the fixed interface charges induced a positive shift of the threshold voltage and an increase in the off-state current. After aging of the oxygen plasma-treated gate dielectrics, the reduced number of polar groups led to greatly enhanced charge mobility, a less positive shift of the threshold voltage, a lower off-state current, and lower activation energy compared to layers without aging. However, the mobility still remained lower than for layers without plasma treatment owing to the rough topography of the gate dielectric. Ó 2007 Elsevier B.V. All rights reserved. PACS: 72.20.Jv; 72.80.Le Keywords: Pentacene; Trap; Mobility; Polar groups; Roughness of gate dielectric; Oxygen plasma
1. Introduction
* Corresponding author. Tel.: +82 54 279 2269; fax: +82 54 279 8298. E-mail address: [email protected] (C.E. Park).
The use of organic field-effect transistors (FETs) in many potential applications, such as radiofrequency identification tags [1,2], displays [3,4], chemical sensors [5–7], etc., can be accelerated by the improvement of device performances such as
1566-1199/$ - see front matter Ó 2007 Elsevier B.V. All rights reserved. doi:10.1016/j.orgel.2006.12.007
K. Shin et al. / Organic Electronics 8 (2007) 336–342
the charge carrier mobility and the switching speed. These properties are correlated to interface phenomena between the organic active layer and the gate dielectric layer, which are significantly influenced by the surface characteristics of the gate dielectric. The presence of functional groups and the roughness topography of compounds used as gate dielectrics have dramatic effects on the morphology of organic semiconductor materials and the electrical characteristics of FETs. There have been many studies about the effects of the surface characteristics of gate dielectrics, but only a few of polymer gate dielectric layers [8–15]. Poly(methylmethacrylate) (PMMA) is a polymer substance commonly used in gate dielectrics [15–17]. In this study the effects of polar functional groups and the roughness topography of PMMA gate dielectric layers were analyzed by applying oxygen (O2) plasma treatment on the gate dielectric and measuring the temperature-dependent mobility for pentacene FETs. If a polymer gate dielectric is treated with O2 plasma, the polymer chains on the surface are broken and surface polar functional groups containing oxygen, such as –OH, –CO–, –OCO–, and –COOH, are created. As a result, the surface polarity and surface energy of the gate dielectric are increased, and the etched polymer surface shows roughened topography [18–21]. The extent of these changes during plasma treatment is dependent on the O2 plasma treatment conditions. A longer treatment time results in a greater number of polar functional groups and a much roughened gate dielectric surface. If a plasma-treated gate dielectric with such polar functional groups is exposed to dry air, the polar functional groups diffuse into the gate dielectric layer to reduce its surface polarity and energy [19–21]. During this aging process, almost no changes occur in the morphology of the gate dielectric surface. Thus, this can show the effect of polar functional groups of the PMMA gate dielectric without changing the other gate dielectric properties. In our experiment, the surface properties of PMMA/Al2O3 gate dielectric layers were controlled using O2 plasma treatment and an aging process. Even though a PMMA single layer can be used as gate dielectric layer for pentacene FET, the PMMA/Al2O3 hybrid gate dielectric is superior in insulation and uniform electrical characteristics. It also minimizes possible changes in the bulk properties of the gate dielectric, such as leakage current
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through the gate dielectric layer and capacitance, during the O2 plasma treatment. 2. Experiments All the gate dielectrics used had a dual layer structure of an upper PMMA layer and a lower anodized Al2O3 layer. The lower Al2O3 layer was fabricated by anodizing the surface of an aluminum gate electrode in aqueous ammonium phosphate solution, created by neutralizing 0.1 M phosphoric acid to pH 6 with 0.1 M ammonium hydroxide. The resulting Al2O3 had a thickness of approximately 100 nm when the voltage applied was 80 V. The upper PMMA layer was produced by spin coating of 3 wt.% PMMA in toluene at a spin speed of 4000 rpm. The PMMA thickness was approximately 120 nm with an rms roughness of approximately 0.7–0.9 nm. The structure of the gate dielectric and a schematic structure of the FET are shown in Fig. 1. The prepared gate dielectric layer was dried for over 1 day in a vacuum oven at 80 °C, and then treated with O2 plasma. Some of the O2 plasmatreated gate dielectrics were aged for 1 week in a 60 °C convection oven. D0s, D20s and D40s denote gate dielectrics which were O2 plasma-treated for 0, 20, and 40 s, respectively. DA20s (DA40s) is the aged gate dielectric after O2 plasma treatment for 20 s (40 s). A pentacene film was deposited onto the gate ˚ /s dielectric layer at a deposition rate of 0.2–0.3 A with a substrate temperature of room temperature. The fabrication of a pentacene FET with top-contact geometry was completed by evaporating gold
Fig. 1. (a) Schematic structure of pentacene FET. (b) Scanning electron micrograph (SEM) of the dual-layer gate dielectric. The lower Al2O3 layer was obtained by anodizing an aluminum gate electrode and the upper PMMA layer was formed by spincoating.
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through a shadow mask to define the source and drain electrodes. P0s, P20s (PA20s) and P40s (PA40s) denote pentacene FETs with D0s, D20s (DA20s), D40s (DA40s) as gate dielectric layers, respectively. The gate dielectric surface and morphologies of the pentacene films were analyzed by atomic force microscopy (AFM; Multimode IIIa, Digital Instruments) operating in tapping mode. Synchrotron X-ray diffraction (XRD) analyses for pentacene films on the prepared gate dielectrics were performed at 10C1 beam line of Pohang Accelerator Laboratory (PAL). The electrical properties of the FETs were characterized using a semiconductor characterization system (Keithley 2400 and 236). The activation energy for charge transport was obtained by measuring mobilities changes in the range of temperature from 80 K to room temperature, using a cryostat system with liquid nitrogen. 3. Results and discussion To examine the changes in surface properties of PMMA/Al2O3 gate dielectrics resulting from O2 plasma treatment and aging, we investigated the
surface morphology of each specimen using AFM. When the O2 plasma treatment time was increased, the surface was etched to a greater extent and roughened, as shown in Fig. 2. An increase in PMMA roughness induced by O2 plasma treatment was reported in previous experiments [18,19], but its extent is slightly different, depending on the experimental conditions. In our case, the gate dielectric did not show much increase in roughness topography with plasma treatment time up to 20 s. However, the topography after 40 s of treatment became much rougher, even if the rms roughness obtained from AFM analysis remained at approximately 0.7–0.9 nm. The topography of the roughness formed by O2 plasma etching is very different from that formed by spin coating on an underlying rough substrate. The O2 plasma-etched surface is rough with sharp, pointed ends and edges. In contrast, the roughness after spin-coating has a smoothly curved surface. This discrepancy can induce very different effects on the pentacene film morphology and the electrical properties of FETs. The changes in surface energy after O2 plasma treatment were calculated by measuring the contact angles of water and diiodomethane. The contact
Fig. 2. Tapping-mode AFM topographic images of the dual layer gate dielectric surfaces: (a) D0s; (b) D20s; (c) D40s; (d) DA20s; and (e) DA40s. The upper and lower images show the three-dimensional and the cross-sectional view of the gate dielectrics, respectively.
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angle is influenced by the polar functional groups and roughness of the gate dielectric. The calculated surface energy increased from 47 to 68 mJ/m2. This is because the introduced polar functional groups and the enlarged surface area increased the surface energy of the gate dielectric. When O2 plasma-treated gate dielectrics were aged, the surface energy decreased to approximately 52–55 mJ/m2 after sufficient aging. However, AFM analyses indicate that almost no change occurred in the surface topography of the gate dielectric layers as a result of the aging process, as shown in Fig. 2. Therefore, the surface energy change on aging process mainly originates from a reduction in the number of polar functional groups. The surface energy of each gate dielectric is shown in Fig. 5c. Fig. 3a–c show the morphologies of pentacene films on D0s, D20s, and D40s, respectively. As the O2 plasma treatment time increased, the grain size of pentacene film decreased. The decrease in gain size can be attributed to the increased surface energy and the roughened gate dielectric layer from O2 plasma treatment. Fig. 3d and e show the morphologies of pentacene films on DA20s and DA40s. Since surface topography does not change during aging process, the smaller grains on D20s (D40s) than those on DA20s (DA40s) indicate that the higher surface energy of the gate dielectrics can disturb the crystallization of pentacene. However, a smaller grain was still observed in the pentacene film on DA40s, even though the surface energy of DA40s was reduced by aging process. This suggests that the sharply edged and pointed surface also restricts the crystallization of pentacene. In our previous study [15], we already reported that the
Fig. 3. Tapping-mode AFM topographic images of 40 nm thick pentacene films on: (a) gate dielectrics D0s, (b) D20s, (c) D40s, (d) DA20s, and (e) DA40s.
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Fig. 4. Out-of-plane X-ray diffraction profiles of 10 nm thick pentacene films on gate dielectrics with O2 plasma treatment time and the aging process.
smoothly curved roughness (Rq: 0.45–1.51 nm) prepared by spin-coating polymer films on an underlying rough surface did not cause a noticeable reduction in grain size in pentacene film. Therefore, these two results demonstrate that the morphology of pentacene film can be mainly determined by the topographical characteristics of roughened surface rather than by the rms roughness itself of polymer gate dielectrics. The out-of-plane XRD profiles in Fig. 4 exhibit series of diffraction patterns of pentacene films grown on the various gate dielectrics shown in Fig. 2. Each peak corresponding to (0 0 l) indicates that pentacene thin films on the gate dielectrics with various topographies and surface energies have thin-film phase characterized by d0 0 l-spacing of ˚ . The variation of peak intensity shows that 15.5 A the ordering of the layered crystal structure is dependent upon O2 plasma treatment time and aging process of gate dielectrics. To compare the ordering of each specimen, the rocking curve measurement was carried out on (0 0 2) peaks as shown in the inset of Fig. 4. The highest peak intensity in the rocking curve was observed in pentacene films grown on D0s, and a dramatic decrease of peak intensity of pentacene films appeared as O2 plasma treatment time increased (see the rocking curves of D20s and D40s in the inset of Fig. 4). The implication of this result is that the O2 plasma treatment on the PMMA dielectrics decreases the out-of-plane ordering of pentacene molecules in thin film. The lower intensity of rocking scan of D20s (D40s) than that of DA20s (DA40s) reveals that the reduction of out-of-plane ordering is caused by the polar func-
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tional groups introduced from O2 plasma treatment, because both dielectrics have similar topographies but different surface energy. Also, DA40s with lowered surface energy has lower intensity of rocking scan than DA20s, which indicates that the rough topography with sharp and pointed edges also decreases the ordering of pentacene molecules in the film. Therefore, the peak disappearance on D40s can be attributed to both the highest surface energy and the pronounced rough topography of gate dielectric layer, resulting in severely disturbed ordering of pentacene molecules. To examine the effects of polar functional groups and the roughness topography of the gate dielectrics on the electrical characteristics of the pentacene FETs, we obtained the transfer characteristics of pentacene FETs, such as mobility, threshold voltage, and sub threshold swing. Also, by measuring mobilities at different temperature, we calculated the activation energy (EA), which indicates the distribution of the widths of the localized trap states [8], and the trap-free mobility (l0) from the Arrhenius relation l = l0 exp( EA/kT). In cases for which plasma treatment was carried out without aging, i.e., P20s and P40s, the mobility at room temperature fell sharply to approximately 0.01 cm2/V s, the threshold voltage (Vth) and turnon voltage (Von) shifted positively, and the off-state
Fig. 5. Electrical characteristics of pentacene FETs depending on O2 plasma treatment time and the aging process: (a), (b) the transfer curves for pentacene FETs; (c) the change of charge mobility of pentacene FETs and surface energy of gate dielectrics; and (d) the change of threshold voltage and subthreshold swing of pentacene FETs.
Fig. 6. Temperature-dependent charge mobility measurements, in which a linear relationship between ln(l) and 1/T was revealed for all samples, indicating the occurrence of thermally activated transport. The activation energy (EA) and the trap-free mobility (l0) were determined from the Arrhenius relation l = l0 exp( EA/kT).
current (Ioff) and subthreshold swing (SS) increased, as shown in Fig. 5. Temperature-dependent mobility measurements revealed a linear relationship between ln(l) and 1/T for all samples, which indicates the occurrence of thermally activated transport. As a result of the O2 plasma treatment, EA increased from 59.5 to 108.1 meV, as shown in Fig. 6. The decrease in mobility resulting from O2 plasma treatment is partly caused by the formation of many hole trap states in the band gap [8,22]. The electric dipoles of the polar functional groups and interface charges that arise in the gate dielectric layer as a result of the O2 plasma treatment induce split energy levels in the band gap and broaden the Gaussian distribution of the energy levels around the HOMO level edge. As a consequence, energy levels are formed that can function as hole trap states in the band gap [23]. Thus, the width of the localized trap state increases, as reflected in the increase in EA [8], so trap filling at bias values below Vth and the capacitance of trapped interface charges result in an increase in SS. This result exactly coincides with the results of simulations reported by Bolognesi et al. and Scheinert et al., who examined the relationships between interface traps and transfer curve behavior [24,25]. The decrease in mobility also originates from the decrease in l0, as shown by Fig. 6. The increased level of crystal imperfections, the smaller grain size, and the resulting restriction of charge transport in
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the charge channel lead to a decrease in l0. The polar functional groups and rough topography of the gate dielectrics can hinder the diffusion of pentacene molecules and result in the production of smaller grains. Moreover, the sharp, pointed ends and valleys in the topography disturb the growth of pentacene crystals, resulting in many defects and vacancies in the pentacene film. Grain boundaries, crystal defects, and rough interfaces can restrict the flow of charges and cause scattering [8,9]. According to Steudel et al., a rough topography also produces valley effects that result in a pronounced decrease in l0 [11]. Regarding the positive shift of Vth and Von in the transfer curve shown in Fig. 5, the electric dipoles and fixed interface charges produced by the plasma treatment cause a surface potential change that induces a bending of the HOMO level at the interface and increases the carrier density in the channel, which have the same effect as applying a negative gate bias [24–28]. As a result, many mobile charges are present at zero gate bias, so a more positive gate voltage is needed to switch off the FET. In addition, the increased number of carriers and the broad potential distribution of the gate dielectric layer result in an increase in Ioff. However, the transfer curves indicate that the positive shifts in Vth and Von and the increase in Ioff for P40s are smaller than those for P20s. As shown in Fig. 6, longer plasma treatment time induces more and deeper trap states, which reduce the number of mobile carriers, resulting in a smaller positive shift of Vth and Von and a smaller increase in Ioff. In the study by Yang et al., O2 plasma treatment (t > 30 s) was found to induce deep trap states in the band gap [28]. The simulations carried out by Bolognesi et al. and Scheinert et al. examined the effect of the depth of trap states on the transfer characteristics, and their conclusions support our experimental results [24,25]. This phenomenon can also be related to lower l0. The rough topography of the gate dielectric in P40s reduces l0, as shown in Fig. 6, and the resulting lowered charge mobility induces smaller positive shifts of Vth and Von and a smaller increase in Ioff. On the other hand, in PA20s and PA40s using aged gate dielectrics, the fewer polar functional groups in the gate dielectrics reduce bending of the HOMO level at the interface, thus inducing smaller positive Vth and Von values than for P20s and P40s, as shown in Fig. 5. The fewer split energy states around the HOMO edge that result from a less
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polar surface, homogeneous chemical state, and resulting increased ordering of pentacene reduce the number of trap states, and leads to higher mobility and lower EA, SS, and Ioff. However, the mobility in PA40s is still lower than that of PA20s, although they have similar EA values. This is because the rougher topography of the gate dielectric is maintained even after aging, as is the disturbed crystallization of pentacene. Accordingly, it is presumed that the low trap-free mobility in PA40s is caused by scattering at the rough interface [8] and the roughness valley effect [11] rather than by the formation of trap states. The effects of the surface properties of the gate dielectrics and the grain boundaries on the distribution of trap states have been intensively studied by many groups. In our experiments, both the surface properties of the gate dielectric and the grain size were changed by plasma treatment and aging of the gate dielectrics. Aging of the gate dielectrics resulted in a decrease in EA and SS and an increase in the grain size of pentacene, however, the results for PA20s and PA40s, with similar surface energy but different topographies, show that the gate dielectric topography did not change EA and SS, even though the samples had pentacene of different grain sizes. Thus, the distribution of trap states is determined more by the polar functional groups on the gate dielectric than by its topography. This result also indicates that the distribution of trap sites is not localized in the grain boundaries of the pentacene film. 4. Summary This study analyzed the effects of polar functional groups and a rough topography of polymer gate dielectrics on the characteristics of FETs. As a result of O2 plasma treatment and aging of PMMA/Al2O3 gate dielectrics, we identified several mobility-reducing factors, i.e., polar functional groups, interface charges, and rough topography. Surface polar groups and surface polarity led to a smaller grain size, a greater number of trap states, and a positive shift of the threshold voltage. Rough topography of the dielectric surface reduced the grain size and the trap-free mobility. Analysis showed that O2 plasma treatment and aging could change the surface energy of PMMA to a wider range, and the effects of polar functional groups on different surface topography could be examined.
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Acknowledgement This work was supported by Grant No. RTI0401-04 from the Regional Technology Innovation Program of the Ministry of Commerce, Industry, and Energy (MOCIE) of Korea. References [1] P.F. Baude, D.A. Ender, M.A. Haase, T.W. Kelly, D.V. Muyres, S.D. Theiss, Appl. Phys. Lett. 82 (2003) 3964. [2] H. Klauk, M. Halik, U. Zschieschang, E.F. Ute, G. Schmid, C. Dehm, Appl. Phys. Lett. 82 (2003) 4175. [3] A. Dodabalapur, Z. Bao, A. Makhija, J.G. Laquindanum, V.R. Raju, Y. Feng, H.E. Katz, J. Rogers, Appl. Phys. Lett. 73 (1998) 142. [4] H. Sirringhaus, N. Tessler, R.H. Friend, Synth. Met. 102 (1999) 857. [5] B. Crone, A. Dodabalapur, A. Gelperin, L. Torsi, H.E. Katz, A.J. Lovinger, Z. Bao, Appl. Phys. Lett. 78 (2001) 2229. [6] C. Bartic, A. Campitelli, S. Borghs, Appl. Phys. Lett. 82 (2003) 475. [7] L. Wang, D. Fine, A. Dodabalapur, Appl. Phys. Lett. 85 (2004) 6386. [8] D. Knipp, R.A. Street, A.R. Vo¨lkel, Appl. Phys. Lett. 82 (2003) 3907. [9] D. Knipp, R.A. Street, A. Vo¨lkel, J. Ho, J. Appl. Phys. 93 (2003) 347. [10] S.E. Fritz, T.W. Kelley, C.D. Frisbie, J. Phys. Chem. B 109 (2005) 10574. [11] S. Steudel, S. De Vusser, S. De Jonge, D. Janssen, S. Verlaak, J. Genoe, P. Heremans, Appl. Phys. Lett. 85 (2004) 4400. [12] L.A. Majewski, R. Schroeder, M. Grell, P.A. Glarvey, M.L. Turner, J. Appl. Phys. 96 (2004) 5781.
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Effects of polar functional groups and roughness topography of polymer gate dielectric layers on pentacene field-effect transistors Kwonwoo Shin, Sang Yoon Yang, Chanwoo Yang, Hayoung Jeon, Chan Eon Park * Polymer Research Institute, Department of Chemical Engineering, Pohang University of Science and Technology (POSTECH), Pohang 790-784, Republic of Korea Received 21 August 2006; received in revised form 7 December 2006; accepted 15 December 2006 Available online 8 January 2007
Abstract The present study analyzed the effects of the polar functional groups and rough topography of the gate dielectric layer on the characteristics of pentacene field-effect transistors. For this purpose, prior to deposition of the organic semiconductor, we introduced polar functional groups and created a rough topography onto the poly(methylmethacrylate)/Al2O3 gate dielectric layer using oxygen plasma treatment, and controlled the number of polar groups using an aging process. The mobility decrease observed after oxygen plasma treatment ranged from 0.2 to <0.01 cm2/V s and was related to the many polar functional groups and the rough topography of the gate dielectric, which formed localized trap states in the band gap and created disorder in the crystal structure. In addition, the electric dipole of the polar groups and the fixed interface charges induced a positive shift of the threshold voltage and an increase in the off-state current. After aging of the oxygen plasma-treated gate dielectrics, the reduced number of polar groups led to greatly enhanced charge mobility, a less positive shift of the threshold voltage, a lower off-state current, and lower activation energy compared to layers without aging. However, the mobility still remained lower than for layers without plasma treatment owing to the rough topography of the gate dielectric. Ó 2007 Elsevier B.V. All rights reserved. PACS: 72.20.Jv; 72.80.Le Keywords: Pentacene; Trap; Mobility; Polar groups; Roughness of gate dielectric; Oxygen plasma
1. Introduction
* Corresponding author. Tel.: +82 54 279 2269; fax: +82 54 279 8298. E-mail address: [email protected] (C.E. Park).
The use of organic field-effect transistors (FETs) in many potential applications, such as radiofrequency identification tags [1,2], displays [3,4], chemical sensors [5–7], etc., can be accelerated by the improvement of device performances such as
1566-1199/$ - see front matter Ó 2007 Elsevier B.V. All rights reserved. doi:10.1016/j.orgel.2006.12.007
K. Shin et al. / Organic Electronics 8 (2007) 336–342
the charge carrier mobility and the switching speed. These properties are correlated to interface phenomena between the organic active layer and the gate dielectric layer, which are significantly influenced by the surface characteristics of the gate dielectric. The presence of functional groups and the roughness topography of compounds used as gate dielectrics have dramatic effects on the morphology of organic semiconductor materials and the electrical characteristics of FETs. There have been many studies about the effects of the surface characteristics of gate dielectrics, but only a few of polymer gate dielectric layers [8–15]. Poly(methylmethacrylate) (PMMA) is a polymer substance commonly used in gate dielectrics [15–17]. In this study the effects of polar functional groups and the roughness topography of PMMA gate dielectric layers were analyzed by applying oxygen (O2) plasma treatment on the gate dielectric and measuring the temperature-dependent mobility for pentacene FETs. If a polymer gate dielectric is treated with O2 plasma, the polymer chains on the surface are broken and surface polar functional groups containing oxygen, such as –OH, –CO–, –OCO–, and –COOH, are created. As a result, the surface polarity and surface energy of the gate dielectric are increased, and the etched polymer surface shows roughened topography [18–21]. The extent of these changes during plasma treatment is dependent on the O2 plasma treatment conditions. A longer treatment time results in a greater number of polar functional groups and a much roughened gate dielectric surface. If a plasma-treated gate dielectric with such polar functional groups is exposed to dry air, the polar functional groups diffuse into the gate dielectric layer to reduce its surface polarity and energy [19–21]. During this aging process, almost no changes occur in the morphology of the gate dielectric surface. Thus, this can show the effect of polar functional groups of the PMMA gate dielectric without changing the other gate dielectric properties. In our experiment, the surface properties of PMMA/Al2O3 gate dielectric layers were controlled using O2 plasma treatment and an aging process. Even though a PMMA single layer can be used as gate dielectric layer for pentacene FET, the PMMA/Al2O3 hybrid gate dielectric is superior in insulation and uniform electrical characteristics. It also minimizes possible changes in the bulk properties of the gate dielectric, such as leakage current
337
through the gate dielectric layer and capacitance, during the O2 plasma treatment. 2. Experiments All the gate dielectrics used had a dual layer structure of an upper PMMA layer and a lower anodized Al2O3 layer. The lower Al2O3 layer was fabricated by anodizing the surface of an aluminum gate electrode in aqueous ammonium phosphate solution, created by neutralizing 0.1 M phosphoric acid to pH 6 with 0.1 M ammonium hydroxide. The resulting Al2O3 had a thickness of approximately 100 nm when the voltage applied was 80 V. The upper PMMA layer was produced by spin coating of 3 wt.% PMMA in toluene at a spin speed of 4000 rpm. The PMMA thickness was approximately 120 nm with an rms roughness of approximately 0.7–0.9 nm. The structure of the gate dielectric and a schematic structure of the FET are shown in Fig. 1. The prepared gate dielectric layer was dried for over 1 day in a vacuum oven at 80 °C, and then treated with O2 plasma. Some of the O2 plasmatreated gate dielectrics were aged for 1 week in a 60 °C convection oven. D0s, D20s and D40s denote gate dielectrics which were O2 plasma-treated for 0, 20, and 40 s, respectively. DA20s (DA40s) is the aged gate dielectric after O2 plasma treatment for 20 s (40 s). A pentacene film was deposited onto the gate ˚ /s dielectric layer at a deposition rate of 0.2–0.3 A with a substrate temperature of room temperature. The fabrication of a pentacene FET with top-contact geometry was completed by evaporating gold
Fig. 1. (a) Schematic structure of pentacene FET. (b) Scanning electron micrograph (SEM) of the dual-layer gate dielectric. The lower Al2O3 layer was obtained by anodizing an aluminum gate electrode and the upper PMMA layer was formed by spincoating.
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through a shadow mask to define the source and drain electrodes. P0s, P20s (PA20s) and P40s (PA40s) denote pentacene FETs with D0s, D20s (DA20s), D40s (DA40s) as gate dielectric layers, respectively. The gate dielectric surface and morphologies of the pentacene films were analyzed by atomic force microscopy (AFM; Multimode IIIa, Digital Instruments) operating in tapping mode. Synchrotron X-ray diffraction (XRD) analyses for pentacene films on the prepared gate dielectrics were performed at 10C1 beam line of Pohang Accelerator Laboratory (PAL). The electrical properties of the FETs were characterized using a semiconductor characterization system (Keithley 2400 and 236). The activation energy for charge transport was obtained by measuring mobilities changes in the range of temperature from 80 K to room temperature, using a cryostat system with liquid nitrogen. 3. Results and discussion To examine the changes in surface properties of PMMA/Al2O3 gate dielectrics resulting from O2 plasma treatment and aging, we investigated the
surface morphology of each specimen using AFM. When the O2 plasma treatment time was increased, the surface was etched to a greater extent and roughened, as shown in Fig. 2. An increase in PMMA roughness induced by O2 plasma treatment was reported in previous experiments [18,19], but its extent is slightly different, depending on the experimental conditions. In our case, the gate dielectric did not show much increase in roughness topography with plasma treatment time up to 20 s. However, the topography after 40 s of treatment became much rougher, even if the rms roughness obtained from AFM analysis remained at approximately 0.7–0.9 nm. The topography of the roughness formed by O2 plasma etching is very different from that formed by spin coating on an underlying rough substrate. The O2 plasma-etched surface is rough with sharp, pointed ends and edges. In contrast, the roughness after spin-coating has a smoothly curved surface. This discrepancy can induce very different effects on the pentacene film morphology and the electrical properties of FETs. The changes in surface energy after O2 plasma treatment were calculated by measuring the contact angles of water and diiodomethane. The contact
Fig. 2. Tapping-mode AFM topographic images of the dual layer gate dielectric surfaces: (a) D0s; (b) D20s; (c) D40s; (d) DA20s; and (e) DA40s. The upper and lower images show the three-dimensional and the cross-sectional view of the gate dielectrics, respectively.
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angle is influenced by the polar functional groups and roughness of the gate dielectric. The calculated surface energy increased from 47 to 68 mJ/m2. This is because the introduced polar functional groups and the enlarged surface area increased the surface energy of the gate dielectric. When O2 plasma-treated gate dielectrics were aged, the surface energy decreased to approximately 52–55 mJ/m2 after sufficient aging. However, AFM analyses indicate that almost no change occurred in the surface topography of the gate dielectric layers as a result of the aging process, as shown in Fig. 2. Therefore, the surface energy change on aging process mainly originates from a reduction in the number of polar functional groups. The surface energy of each gate dielectric is shown in Fig. 5c. Fig. 3a–c show the morphologies of pentacene films on D0s, D20s, and D40s, respectively. As the O2 plasma treatment time increased, the grain size of pentacene film decreased. The decrease in gain size can be attributed to the increased surface energy and the roughened gate dielectric layer from O2 plasma treatment. Fig. 3d and e show the morphologies of pentacene films on DA20s and DA40s. Since surface topography does not change during aging process, the smaller grains on D20s (D40s) than those on DA20s (DA40s) indicate that the higher surface energy of the gate dielectrics can disturb the crystallization of pentacene. However, a smaller grain was still observed in the pentacene film on DA40s, even though the surface energy of DA40s was reduced by aging process. This suggests that the sharply edged and pointed surface also restricts the crystallization of pentacene. In our previous study [15], we already reported that the
Fig. 3. Tapping-mode AFM topographic images of 40 nm thick pentacene films on: (a) gate dielectrics D0s, (b) D20s, (c) D40s, (d) DA20s, and (e) DA40s.
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Fig. 4. Out-of-plane X-ray diffraction profiles of 10 nm thick pentacene films on gate dielectrics with O2 plasma treatment time and the aging process.
smoothly curved roughness (Rq: 0.45–1.51 nm) prepared by spin-coating polymer films on an underlying rough surface did not cause a noticeable reduction in grain size in pentacene film. Therefore, these two results demonstrate that the morphology of pentacene film can be mainly determined by the topographical characteristics of roughened surface rather than by the rms roughness itself of polymer gate dielectrics. The out-of-plane XRD profiles in Fig. 4 exhibit series of diffraction patterns of pentacene films grown on the various gate dielectrics shown in Fig. 2. Each peak corresponding to (0 0 l) indicates that pentacene thin films on the gate dielectrics with various topographies and surface energies have thin-film phase characterized by d0 0 l-spacing of ˚ . The variation of peak intensity shows that 15.5 A the ordering of the layered crystal structure is dependent upon O2 plasma treatment time and aging process of gate dielectrics. To compare the ordering of each specimen, the rocking curve measurement was carried out on (0 0 2) peaks as shown in the inset of Fig. 4. The highest peak intensity in the rocking curve was observed in pentacene films grown on D0s, and a dramatic decrease of peak intensity of pentacene films appeared as O2 plasma treatment time increased (see the rocking curves of D20s and D40s in the inset of Fig. 4). The implication of this result is that the O2 plasma treatment on the PMMA dielectrics decreases the out-of-plane ordering of pentacene molecules in thin film. The lower intensity of rocking scan of D20s (D40s) than that of DA20s (DA40s) reveals that the reduction of out-of-plane ordering is caused by the polar func-
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tional groups introduced from O2 plasma treatment, because both dielectrics have similar topographies but different surface energy. Also, DA40s with lowered surface energy has lower intensity of rocking scan than DA20s, which indicates that the rough topography with sharp and pointed edges also decreases the ordering of pentacene molecules in the film. Therefore, the peak disappearance on D40s can be attributed to both the highest surface energy and the pronounced rough topography of gate dielectric layer, resulting in severely disturbed ordering of pentacene molecules. To examine the effects of polar functional groups and the roughness topography of the gate dielectrics on the electrical characteristics of the pentacene FETs, we obtained the transfer characteristics of pentacene FETs, such as mobility, threshold voltage, and sub threshold swing. Also, by measuring mobilities at different temperature, we calculated the activation energy (EA), which indicates the distribution of the widths of the localized trap states [8], and the trap-free mobility (l0) from the Arrhenius relation l = l0 exp( EA/kT). In cases for which plasma treatment was carried out without aging, i.e., P20s and P40s, the mobility at room temperature fell sharply to approximately 0.01 cm2/V s, the threshold voltage (Vth) and turnon voltage (Von) shifted positively, and the off-state
Fig. 5. Electrical characteristics of pentacene FETs depending on O2 plasma treatment time and the aging process: (a), (b) the transfer curves for pentacene FETs; (c) the change of charge mobility of pentacene FETs and surface energy of gate dielectrics; and (d) the change of threshold voltage and subthreshold swing of pentacene FETs.
Fig. 6. Temperature-dependent charge mobility measurements, in which a linear relationship between ln(l) and 1/T was revealed for all samples, indicating the occurrence of thermally activated transport. The activation energy (EA) and the trap-free mobility (l0) were determined from the Arrhenius relation l = l0 exp( EA/kT).
current (Ioff) and subthreshold swing (SS) increased, as shown in Fig. 5. Temperature-dependent mobility measurements revealed a linear relationship between ln(l) and 1/T for all samples, which indicates the occurrence of thermally activated transport. As a result of the O2 plasma treatment, EA increased from 59.5 to 108.1 meV, as shown in Fig. 6. The decrease in mobility resulting from O2 plasma treatment is partly caused by the formation of many hole trap states in the band gap [8,22]. The electric dipoles of the polar functional groups and interface charges that arise in the gate dielectric layer as a result of the O2 plasma treatment induce split energy levels in the band gap and broaden the Gaussian distribution of the energy levels around the HOMO level edge. As a consequence, energy levels are formed that can function as hole trap states in the band gap [23]. Thus, the width of the localized trap state increases, as reflected in the increase in EA [8], so trap filling at bias values below Vth and the capacitance of trapped interface charges result in an increase in SS. This result exactly coincides with the results of simulations reported by Bolognesi et al. and Scheinert et al., who examined the relationships between interface traps and transfer curve behavior [24,25]. The decrease in mobility also originates from the decrease in l0, as shown by Fig. 6. The increased level of crystal imperfections, the smaller grain size, and the resulting restriction of charge transport in
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the charge channel lead to a decrease in l0. The polar functional groups and rough topography of the gate dielectrics can hinder the diffusion of pentacene molecules and result in the production of smaller grains. Moreover, the sharp, pointed ends and valleys in the topography disturb the growth of pentacene crystals, resulting in many defects and vacancies in the pentacene film. Grain boundaries, crystal defects, and rough interfaces can restrict the flow of charges and cause scattering [8,9]. According to Steudel et al., a rough topography also produces valley effects that result in a pronounced decrease in l0 [11]. Regarding the positive shift of Vth and Von in the transfer curve shown in Fig. 5, the electric dipoles and fixed interface charges produced by the plasma treatment cause a surface potential change that induces a bending of the HOMO level at the interface and increases the carrier density in the channel, which have the same effect as applying a negative gate bias [24–28]. As a result, many mobile charges are present at zero gate bias, so a more positive gate voltage is needed to switch off the FET. In addition, the increased number of carriers and the broad potential distribution of the gate dielectric layer result in an increase in Ioff. However, the transfer curves indicate that the positive shifts in Vth and Von and the increase in Ioff for P40s are smaller than those for P20s. As shown in Fig. 6, longer plasma treatment time induces more and deeper trap states, which reduce the number of mobile carriers, resulting in a smaller positive shift of Vth and Von and a smaller increase in Ioff. In the study by Yang et al., O2 plasma treatment (t > 30 s) was found to induce deep trap states in the band gap [28]. The simulations carried out by Bolognesi et al. and Scheinert et al. examined the effect of the depth of trap states on the transfer characteristics, and their conclusions support our experimental results [24,25]. This phenomenon can also be related to lower l0. The rough topography of the gate dielectric in P40s reduces l0, as shown in Fig. 6, and the resulting lowered charge mobility induces smaller positive shifts of Vth and Von and a smaller increase in Ioff. On the other hand, in PA20s and PA40s using aged gate dielectrics, the fewer polar functional groups in the gate dielectrics reduce bending of the HOMO level at the interface, thus inducing smaller positive Vth and Von values than for P20s and P40s, as shown in Fig. 5. The fewer split energy states around the HOMO edge that result from a less
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polar surface, homogeneous chemical state, and resulting increased ordering of pentacene reduce the number of trap states, and leads to higher mobility and lower EA, SS, and Ioff. However, the mobility in PA40s is still lower than that of PA20s, although they have similar EA values. This is because the rougher topography of the gate dielectric is maintained even after aging, as is the disturbed crystallization of pentacene. Accordingly, it is presumed that the low trap-free mobility in PA40s is caused by scattering at the rough interface [8] and the roughness valley effect [11] rather than by the formation of trap states. The effects of the surface properties of the gate dielectrics and the grain boundaries on the distribution of trap states have been intensively studied by many groups. In our experiments, both the surface properties of the gate dielectric and the grain size were changed by plasma treatment and aging of the gate dielectrics. Aging of the gate dielectrics resulted in a decrease in EA and SS and an increase in the grain size of pentacene, however, the results for PA20s and PA40s, with similar surface energy but different topographies, show that the gate dielectric topography did not change EA and SS, even though the samples had pentacene of different grain sizes. Thus, the distribution of trap states is determined more by the polar functional groups on the gate dielectric than by its topography. This result also indicates that the distribution of trap sites is not localized in the grain boundaries of the pentacene film. 4. Summary This study analyzed the effects of polar functional groups and a rough topography of polymer gate dielectrics on the characteristics of FETs. As a result of O2 plasma treatment and aging of PMMA/Al2O3 gate dielectrics, we identified several mobility-reducing factors, i.e., polar functional groups, interface charges, and rough topography. Surface polar groups and surface polarity led to a smaller grain size, a greater number of trap states, and a positive shift of the threshold voltage. Rough topography of the dielectric surface reduced the grain size and the trap-free mobility. Analysis showed that O2 plasma treatment and aging could change the surface energy of PMMA to a wider range, and the effects of polar functional groups on different surface topography could be examined.
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